xref: /netbsd/sys/arch/sparc/sparc/memeccreg.h (revision 6550d01e)
1 /*	$NetBSD: memeccreg.h,v 1.2 2008/04/28 20:23:36 martin Exp $	*/
2 
3 /*-
4  * Copyright (c) 1998 The NetBSD Foundation, Inc.
5  * All rights reserved.
6  *
7  * This code is derived from software contributed to The NetBSD Foundation
8  * by Paul Kranenburg.
9  *
10  * Redistribution and use in source and binary forms, with or without
11  * modification, are permitted provided that the following conditions
12  * are met:
13  * 1. Redistributions of source code must retain the above copyright
14  *    notice, this list of conditions and the following disclaimer.
15  * 2. Redistributions in binary form must reproduce the above copyright
16  *    notice, this list of conditions and the following disclaimer in the
17  *    documentation and/or other materials provided with the distribution.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  * POSSIBILITY OF SUCH DAMAGE.
30  */
31 
32 /*
33  * ECC memory control.
34  */
35 
36 /* Register offsets */
37 #define ECC_EN_REG	0
38 #define ECC_FSR_REG	8
39 #define ECC_AFR0_REG	16
40 #define ECC_AFR1_REG	20
41 #define ECC_DIAG_REG	24
42 
43 /* ECC Memory Enable register */
44 #define ECC_EN_EE	0x00000001	/* Enable ECC checking */
45 #define ECC_EN_EI	0x00000002	/* Interrupt on correctable error */
46 #define ECC_EN_VER	0x0f000000	/* Version */
47 #define ECC_EN_IMPL	0xf0000000	/* Implementation Id */
48 
49 /* ECC Memory Fault Status register */
50 #define ECC_FSR_CE	0x00000001	/* Correctable error */
51 #define ECC_FSR_TO	0x00000004	/* Timeout on write */
52 #define ECC_FSR_UE	0x00000008	/* Uncorrectable error */
53 #define ECC_FSR_DW	0x000000f0	/* Index of double word in block */
54 #define ECC_FSR_SYND	0x0000ff00	/* Syndrome for correctable error */
55 #define ECC_FSR_ME	0x00010000	/* Multiple errors */
56 #define ECC_FSR_BITS	"\177\020"				\
57 			"b\0CE\0b\2TO\0b\3UE\0"			\
58 			"f\4\4DW\0f\10\10SYNDROME\0b\20ME\0"
59 
60 /*
61  * ECC Memory Fault Address registers
62  * There are two of these. The first has bits 32-35 of the faulting
63  * physical address and assorted MBus bits. The second has bits
64  * 0-31 of the faulting physical address.
65  */
66 #define ECC_AFR_PAH	0x0000000f	/* PA[31-35] */
67 #define ECC_AFR_TYPE	0x000000f0	/* Transaction type */
68 #define ECC_AFR_SIZE	0x00000700	/* Transaction size */
69 #define ECC_AFR_C	0x00000800	/* Mapped cacheable */
70 #define ECC_AFR_LOCK	0x00001000	/* Error occurred in atomic cycle */
71 #define ECC_AFR_MBL	0x00002000	/* Boot mode */
72 #define ECC_AFR_VA	0x003fc000	/* VA[12-19] (superset bits) */
73 #define ECC_AFR_S	0x08000000	/* Access was in supervisor mode */
74 #define ECC_AFR_MID	0xf0000000	/* Module code */
75 #define ECC_AFR_BITS	"\177\020"				\
76 			"f\0\4VAH\0f\4\4TYPE\0f\10\3SIZE\0"	\
77 			"b\13C\0b\14LOCK\0b\15MBL\0"		\
78 			"f\16\10VA\0b\33S\0f\34\4MID\0"
79 
80 /* ECC Diagnostic register */
81 #define ECC_DR_CBX	0x00000001
82 #define ECC_DR_CB0	0x00000002
83 #define ECC_DR_CB1	0x00000004
84 #define ECC_DR_CB2	0x00000008
85 #define ECC_DR_CB4	0x00000010
86 #define ECC_DR_CB8	0x00000020
87 #define ECC_DR_CB16	0x00000040
88 #define ECC_DR_CB32	0x00000080
89 #define ECC_DR_DMODE	0x00000c00
90 #define ECC_DR_BITS	"\177\020"					\
91 			"f\12\2DMODE\0=\0NORMAL\0=\1GEN\0=\2DETECT\0"	\
92 			"f\0\8CHECK BITS\0"
93 
94