1 /* $NetBSD: memeccreg.h,v 1.1 1998/09/18 20:18:10 pk Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * ECC memory control. 41 */ 42 43 /* Register offsets */ 44 #define ECC_EN_REG 0 45 #define ECC_FSR_REG 8 46 #define ECC_AFR0_REG 16 47 #define ECC_AFR1_REG 20 48 #define ECC_DIAG_REG 24 49 50 /* ECC Memory Enable register */ 51 #define ECC_EN_EE 0x00000001 /* Enable ECC checking */ 52 #define ECC_EN_EI 0x00000002 /* Interrupt on correctable error */ 53 #define ECC_EN_VER 0x0f000000 /* Version */ 54 #define ECC_EN_IMPL 0xf0000000 /* Implementation Id */ 55 56 /* ECC Memory Fault Status register */ 57 #define ECC_FSR_CE 0x00000001 /* Correctable error */ 58 #define ECC_FSR_TO 0x00000004 /* Timeout on write */ 59 #define ECC_FSR_UE 0x00000008 /* Uncorrectable error */ 60 #define ECC_FSR_DW 0x000000f0 /* Index of double word in block */ 61 #define ECC_FSR_SYND 0x0000ff00 /* Syndrome for correctable error */ 62 #define ECC_FSR_ME 0x00010000 /* Multiple errors */ 63 #define ECC_FSR_BITS "\177\020" \ 64 "b\0CE\0b\2TO\0b\3UE\0" \ 65 "f\4\4DW\0f\10\10SYNDROME\0b\20ME\0" 66 67 /* 68 * ECC Memory Fault Address registers 69 * There are two of these. The first has bits 32-35 of the faulting 70 * physical address and assorted MBus bits. The second has bits 71 * 0-31 of the faulting physical address. 72 */ 73 #define ECC_AFR_PAH 0x0000000f /* PA[31-35] */ 74 #define ECC_AFR_TYPE 0x000000f0 /* Transaction type */ 75 #define ECC_AFR_SIZE 0x00000700 /* Transaction size */ 76 #define ECC_AFR_C 0x00000800 /* Mapped cacheable */ 77 #define ECC_AFR_LOCK 0x00001000 /* Error occurred in atomic cycle */ 78 #define ECC_AFR_MBL 0x00002000 /* Boot mode */ 79 #define ECC_AFR_VA 0x003fc000 /* VA[12-19] (superset bits) */ 80 #define ECC_AFR_S 0x08000000 /* Access was in supervisor mode */ 81 #define ECC_AFR_MID 0xf0000000 /* Module code */ 82 #define ECC_AFR_BITS "\177\020" \ 83 "f\0\4VAH\0f\4\4TYPE\0f\10\3SIZE\0" \ 84 "b\13C\0b\14LOCK\0b\15MBL\0" \ 85 "f\16\10VA\0b\33S\0f\34\4MID\0" 86 87 /* ECC Diagnostic register */ 88 #define ECC_DR_CBX 0x00000001 89 #define ECC_DR_CB0 0x00000002 90 #define ECC_DR_CB1 0x00000004 91 #define ECC_DR_CB2 0x00000008 92 #define ECC_DR_CB4 0x00000010 93 #define ECC_DR_CB8 0x00000020 94 #define ECC_DR_CB16 0x00000040 95 #define ECC_DR_CB32 0x00000080 96 #define ECC_DR_DMODE 0x00000c00 97 #define ECC_DR_BITS "\177\020" \ 98 "f\12\2DMODE\0=\0NORMAL\0=\1GEN\0=\2DETECT\0" \ 99 "f\0\8CHECK BITS\0" 100 101