1 /* $NetBSD: msiiepreg.h,v 1.1 2001/12/11 00:18:23 uwe Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Valeriy E. Ushakov 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #ifndef _SPARC_MSIIEP_REG_H_ 31 #define _SPARC_MSIIEP_REG_H_ 32 33 /* 34 * microSPARC-IIep PCI controller registers 35 * 36 * Accessible via PA=0011.0000 0000.110x xxxx.xxxx AAAA.AAAA 37 * where 'x' bits are ignored. We use PA=0x300c.0000 as "canonical". 38 * We map it at a fixed MSIIEP_PCIC_VA (see vaddrs.h). 39 * 40 * Field names are chosen to match relevant OFW forth words. 41 * 42 * NB: Upon reset the PCIC registers and PCI bus accesses are in 43 * little-endian mode. We configure PCIC to do endian-swapping 44 * automagically by setting MSIIEP_PIO_CTRL_BIG_ENDIAN bit in 45 * pcic_pio_ctrl early in the bootstrap process. 46 * 47 * Section numbers in comments refer to: 48 * "microSPARC(TM)-IIep User's Manual" (Sun Part Number: 802-7100-01) 49 */ 50 51 #define MSIIEP_PCIC_PA ((paddr_t)0x300c0000) 52 53 struct msiiep_pcic_reg { 54 /* PCI_ID_REG */ 55 u_int32_t pcic_id; /* @00/4 9.5.2.1 */ 56 57 /* PCI_COMMAND_STATUS_REG */ 58 u_int16_t pcic_cmd; /* @04/2 9.5.2.2 */ 59 u_int16_t pcic_stat; /* @06/2 9.5.2.3 */ 60 61 /* PCI_CLASS_REG */ 62 u_int32_t pcic_class; /* @08/4 9.5.2.1 */ 63 64 /* PCI_BHLC_REG: but with lattimer and cacheline swapped !!! */ 65 u_int32_t pcic_bhlc; /* @0c/4 9.5.2.1, 9.5.3*/ 66 67 /* 9.5.5.1 PCI Base Address Registers */ 68 u_int32_t pcic_ba[6]; /* @10/4 .. @24/4 */ 69 70 u_int32_t pcic_unused_28; 71 u_int32_t pcic_unused_2c; 72 u_int32_t pcic_unused_30; 73 u_int32_t pcic_unused_34; 74 u_int32_t pcic_unused_38; 75 u_int32_t pcic_unused_3c; 76 77 /* 9.5.3 #RETRY and #TRDY counters */ 78 u_int32_t pcic_cntrs; /* @40/4 */ 79 80 /* 9.5.5.2 PCI Base Size Registers */ 81 u_int32_t pcic_sz[6]; /* @44/4 .. @58/4 */ 82 83 u_int32_t pcic_unused_5c; 84 85 86 /* 9.6.3 PIO control */ 87 u_int8_t pcic_pio_ctrl; /* @60/1 (no word?) */ 88 #define MSIIEP_PIO_CTRL_PREFETCH_ENABLE 0x80 89 #define MSIIEP_PIO_CTRL_BURST_ENABLE 0x40 90 #define MSIIEP_PIO_CTRL_BIG_ENDIAN 0x04 91 92 u_int8_t pcic_unused_61; 93 94 /* 9.6.4 DVMA control */ 95 u_int8_t pcic_dvmac; /* @62/1 (no word?) */ 96 97 /* 9.6.5 Arbitration/Interrupt Control */ 98 u_int8_t pcic_arb_intr_ctrl; /* @63/1 */ 99 100 /* 9.7.5 Processor Interrupt Pending */ 101 u_int32_t pcic_proc_ipr; /* @64/4 */ 102 103 /* 9.5.3 Discard Timer */ 104 u_int16_t pcic_discard_tmr; /* @68/2 */ 105 106 /* 9.7.6 Software Interrupt Clear/Set */ 107 u_int16_t pcic_soft_intr_clear; /* @6a/2 */ 108 u_int16_t pcic_unused_6c; 109 u_int16_t pcic_soft_intr_set; /* @6e/2 */ 110 111 /* 9.7.2 System Interrupt Pending */ 112 u_int32_t pcic_sys_ipr; /* @70/4 */ 113 #define MSIIEP_SYS_IPR_PIO_ERR 0x40000000 114 #define MSIIEP_SYS_IPR_DMA_ERR 0x20000000 115 #define MSIIEP_SYS_IPR_SERR 0x10000000 116 #define MSIIEP_SYS_IPR_MEM_FAULT 0x08000000 117 118 119 /* 9.7.4 System Interrupt Target Mask (read/clear/set) */ 120 u_int32_t pcic_sys_itmr; /* @74/4 */ 121 u_int32_t pcic_sys_itmr_clr; /* @78/4 */ 122 u_int32_t pcic_sys_itmr_set; /* @7c/4 */ 123 #define MSIIEP_SYS_ITMR_ALL 0x80000000 124 #define MSIIEP_SYS_ITMR_PIO_ERR 0x40000000 125 #define MSIIEP_SYS_ITMR_DMA_ERR 0x20000000 126 #define MSIIEP_SYS_ITMR_SERR 0x10000000 127 #define MSIIEP_SYS_ITMR_MEM_FAULT 0x08000000 128 #define MSIIEP_SYS_ITMR_RESET 0x04000000 129 130 u_int8_t pcic_unused_80; 131 u_int8_t pcic_unused_81; 132 u_int8_t pcic_unused_82; 133 134 /* 9.7.3 Clear System Interrupt Pending */ 135 u_int8_t pcic_sys_ipr_clr; /* @83/1 */ 136 #define MSIIEP_SYS_IPR_CLR_ALL 0x80 137 #define MSIIEP_SYS_IPR_CLR_PIO_ERR 0x40 138 #define MSIIEP_SYS_IPR_CLR_DMA_ERR 0x20 139 #define MSIIEP_SYS_IPR_CLR_SERR 0x10 140 #define MSIIEP_SYS_IPR_CLR_RESET 0x08 141 142 143 /* 9.5.7.1 IOTLB control (the rest of IOTLB regs is below at 90) */ 144 u_int32_t pcic_iotlb_ctrl; /* @84/4 (no word?) */ 145 146 /* 9.7.1 Interrupt select PCI_INT_L[0..3] (aka pins A to D) */ 147 u_int16_t pcic_intr_asgn_sel; /* @88/2 */ 148 149 /* 9.6.1 Arbitration Assignment Select */ 150 u_int16_t pcic_arbt_asgn_sel; /* @8a/2 */ 151 152 /* 9.7.1 Interrupt Select PCI_INT_L[4..7] */ 153 u_int16_t pcic_intr_asgn_sel_hi; /* @8c/2 */ 154 155 /* 9.7.7 Hardware Interrupt Output */ 156 u_int16_t pcic_intr_out; /* @8e/2 (no word) */ 157 158 /* IOTLB RAM/CAM input/output */ 159 u_int32_t pcic_iotlb_ram_in; /* @90/4 9.5.7.2 */ 160 u_int32_t pcic_iotlb_cam_in; /* @94/4 9.5.7.3 */ 161 u_int32_t pcic_iotlb_ram_out; /* @98/4 9.5.8.1 */ 162 u_int32_t pcic_iotlb_cam_out; /* @9c/4 9.5.8.2 */ 163 164 /* 9.5.4.1 Memory Cycle Translation Register Set 0 */ 165 u_int8_t pcic_smbar0; /* @a0/1 */ 166 u_int8_t pcic_msize0; /* @a1/1 */ 167 u_int8_t pcic_pmbar0; /* @a2/1 */ 168 u_int8_t pcic_unused_a3; 169 170 /* 9.5.4.2 Memory Cycle Translation Register Set 1 */ 171 u_int8_t pcic_smbar1; /* @a4/1 */ 172 u_int8_t pcic_msize1; /* @a5/1 */ 173 u_int8_t pcic_pmbar1; /* @a6/1 */ 174 u_int8_t pcic_unused_a7; 175 176 /* 9.5.4.3 I/O Cycle Translation Register Set */ 177 u_int8_t pcic_sibar; /* @a8/1 */ 178 u_int8_t pcic_iosize; /* @a9/1 */ 179 u_int8_t pcic_pibar; /* @aa/1 */ 180 u_int8_t pcic_unused_ab; 181 182 /* 183 * 9.8 Processor and system counters: 184 * (limit, counter, non-resetting limit) 185 */ 186 187 /* processor counter (xor user timer that we don't use) */ 188 u_int32_t pcic_pclr; /* @ac/4 9.8.1 */ 189 u_int32_t pcic_pccr; /* @b0/4 9.8.2 */ 190 u_int32_t pcic_pclr_nr; /* @b4/4 9.8.3 */ 191 192 /* system counter */ 193 u_int32_t pcic_sclr; /* @b8/4 9.8.4 */ 194 u_int32_t pcic_sccr; /* @bc/4 9.8.5 */ 195 u_int32_t pcic_sclr_nr; /* @c0/4 9.8.6 */ 196 197 /* 9.8.7 User Timer Start/Stop */ 198 u_int8_t pcic_pc_ctl; /* @c4/1 */ 199 200 /* 9.8.8 Processor Counter or User Timer Configuration */ 201 u_int8_t pcic_pc_cfg; /* @c5/1 (no word?) */ 202 203 /* 9.8.9 Counter Interrupt Priority Assignment */ 204 u_int8_t pcic_cipar; /* @c6/1 */ 205 206 207 /* 9.5.9 PIO Error Command and Address Registers */ 208 u_int8_t pcic_pio_err_cmd; /* @c7/1 */ 209 u_int32_t pcic_pio_err_addr; /* @c8/4 */ 210 211 /* 9.5.8.3 IOTLB Error Address */ 212 u_int32_t pcic_iotlb_err_addr; /* @cc/4 */ 213 214 /* 9.9 System Status and System Control (Reset) */ 215 u_int8_t pcic_sys_scr; /* @d0/1 */ 216 217 218 /* pad to 256 bytes */ 219 u_int8_t pcic_unused_d1; 220 u_int8_t pcic_unused_d2; 221 u_int8_t pcic_unused_d3; 222 u_int32_t pcic_unused_pad[11]; 223 }; 224 225 #endif /* _SPARC_MSIIEP_REG_H_ */ 226