1*54015632Smaxv/* $NetBSD: sigcode_state.s,v 1.2 2018/12/19 13:57:50 maxv Exp $ */ 27bb4cfc2Smrg 37bb4cfc2Smrg/* 47bb4cfc2Smrg * Copyright (c) 1996 Paul Kranenburg 57bb4cfc2Smrg * Copyright (c) 1996 67bb4cfc2Smrg * The President and Fellows of Harvard College. All rights reserved. 77bb4cfc2Smrg * Copyright (c) 1992, 1993 87bb4cfc2Smrg * The Regents of the University of California. All rights reserved. 97bb4cfc2Smrg * 107bb4cfc2Smrg * This software was developed by the Computer Systems Engineering group 117bb4cfc2Smrg * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 127bb4cfc2Smrg * contributed to Berkeley. 137bb4cfc2Smrg * 147bb4cfc2Smrg * All advertising materials mentioning features or use of this software 157bb4cfc2Smrg * must display the following acknowledgement: 167bb4cfc2Smrg * This product includes software developed by the University of 177bb4cfc2Smrg * California, Lawrence Berkeley Laboratory. 187bb4cfc2Smrg * This product includes software developed by Harvard University. 197bb4cfc2Smrg * 207bb4cfc2Smrg * Redistribution and use in source and binary forms, with or without 217bb4cfc2Smrg * modification, are permitted provided that the following conditions 227bb4cfc2Smrg * are met: 237bb4cfc2Smrg * 1. Redistributions of source code must retain the above copyright 247bb4cfc2Smrg * notice, this list of conditions and the following disclaimer. 257bb4cfc2Smrg * 2. Redistributions in binary form must reproduce the above copyright 267bb4cfc2Smrg * notice, this list of conditions and the following disclaimer in the 277bb4cfc2Smrg * documentation and/or other materials provided with the distribution. 287bb4cfc2Smrg * 3. All advertising materials mentioning features or use of this software 297bb4cfc2Smrg * must display the following acknowledgement: 307bb4cfc2Smrg * This product includes software developed by the University of 317bb4cfc2Smrg * California, Berkeley and its contributors. 327bb4cfc2Smrg * This product includes software developed by Harvard University. 337bb4cfc2Smrg * This product includes software developed by Paul Kranenburg. 347bb4cfc2Smrg * 4. Neither the name of the University nor the names of its contributors 357bb4cfc2Smrg * may be used to endorse or promote products derived from this software 367bb4cfc2Smrg * without specific prior written permission. 377bb4cfc2Smrg * 387bb4cfc2Smrg * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 397bb4cfc2Smrg * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 407bb4cfc2Smrg * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 417bb4cfc2Smrg * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 427bb4cfc2Smrg * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 437bb4cfc2Smrg * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 447bb4cfc2Smrg * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 457bb4cfc2Smrg * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 467bb4cfc2Smrg * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 477bb4cfc2Smrg * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 487bb4cfc2Smrg * SUCH DAMAGE. 497bb4cfc2Smrg * 507bb4cfc2Smrg * @(#)locore.s 8.4 (Berkeley) 12/10/93 517bb4cfc2Smrg * from: NetBSD: locore.s,v 1.140 2001/05/26 10:22:32 pk Exp 527bb4cfc2Smrg */ 537bb4cfc2Smrg 547bb4cfc2Smrg#include <machine/frame.h> 557bb4cfc2Smrg 567bb4cfc2Smrg/* 57*54015632Smaxv * These defines are here so that locore.s and sunos_sigcode.s can all access 58*54015632Smaxv * them. 597bb4cfc2Smrg */ 607bb4cfc2Smrg 617bb4cfc2Smrg/* 627bb4cfc2Smrg * The following code is copied to the top of the user stack when each 637bb4cfc2Smrg * process is exec'ed, and signals are `trampolined' off it. 647bb4cfc2Smrg * 657bb4cfc2Smrg * When this code is run, the stack looks like: 667bb4cfc2Smrg * [%sp] 64 bytes to which registers can be dumped 677bb4cfc2Smrg * [%sp + 64] signal number (goes in %o0) 687bb4cfc2Smrg * [%sp + 64 + 4] signal code (goes in %o1) 697bb4cfc2Smrg * [%sp + 64 + 8] placeholder 707bb4cfc2Smrg * [%sp + 64 + 12] argument for %o3, currently unsupported (always 0) 717bb4cfc2Smrg * [%sp + 64 + 16] first word of saved state (sigcontext) 727bb4cfc2Smrg * . 737bb4cfc2Smrg * . 747bb4cfc2Smrg * . 757bb4cfc2Smrg * [%sp + NNN] last word of saved state 767bb4cfc2Smrg * (followed by previous stack contents or top of signal stack). 777bb4cfc2Smrg * The address of the function to call is in %g1; the old %g1 and %o0 787bb4cfc2Smrg * have already been saved in the sigcontext. We are running in a clean 797bb4cfc2Smrg * window, all previous windows now being saved to the stack. 807bb4cfc2Smrg * 817bb4cfc2Smrg * Note that [%sp + 64 + 8] == %sp + 64 + 16. The copy at %sp+64+8 827bb4cfc2Smrg * will eventually be removed, with a hole left in its place, if things 837bb4cfc2Smrg * work out. 847bb4cfc2Smrg */ 857bb4cfc2Smrg#define SAVE_STATE \ 867bb4cfc2Smrg /* \ 877bb4cfc2Smrg * XXX the `save' and `restore' below are unnecessary: should \ 887bb4cfc2Smrg * replace with simple arithmetic on %sp \ 897bb4cfc2Smrg * \ 907bb4cfc2Smrg * Make room on the stack for 32 %f registers + %fsr. This comes \ 917bb4cfc2Smrg * out to 33*4 or 132 bytes, but this must be aligned to a multiple \ 927bb4cfc2Smrg * of 8, or 136 bytes. \ 937bb4cfc2Smrg */ \ 947bb4cfc2Smrg save %sp, -CCFSZ - 136, %sp; \ 957bb4cfc2Smrg mov %g2, %l2; /* save globals in %l registers */ \ 967bb4cfc2Smrg mov %g3, %l3; \ 977bb4cfc2Smrg mov %g4, %l4; \ 987bb4cfc2Smrg mov %g5, %l5; \ 997bb4cfc2Smrg mov %g6, %l6; \ 1007bb4cfc2Smrg mov %g7, %l7; \ 1017bb4cfc2Smrg /* \ 1027bb4cfc2Smrg * Saving the fpu registers is expensive, so do it iff the fsr \ 1037bb4cfc2Smrg * stored in the sigcontext shows that the fpu is enabled. \ 1047bb4cfc2Smrg */ \ 1057bb4cfc2Smrg ld [%fp + 64 + 16 + SC_PSR_OFFSET], %l0; \ 1067bb4cfc2Smrg sethi %hi(PSR_EF), %l1; /* FPU enable is too high for andcc */ \ 1077bb4cfc2Smrg andcc %l0, %l1, %l0; /* %l0 = fpu enable bit */ \ 1087bb4cfc2Smrg be 1f; /* if not set, skip the saves */ \ 1097bb4cfc2Smrg rd %y, %l1; /* in any case, save %y */ \ 1107bb4cfc2Smrg /* fpu is enabled, oh well */ \ 1117bb4cfc2Smrg st %fsr, [%sp + CCFSZ + 0]; \ 1127bb4cfc2Smrg std %f0, [%sp + CCFSZ + 8]; \ 1137bb4cfc2Smrg std %f2, [%sp + CCFSZ + 16]; \ 1147bb4cfc2Smrg std %f4, [%sp + CCFSZ + 24]; \ 1157bb4cfc2Smrg std %f6, [%sp + CCFSZ + 32]; \ 1167bb4cfc2Smrg std %f8, [%sp + CCFSZ + 40]; \ 1177bb4cfc2Smrg std %f10, [%sp + CCFSZ + 48]; \ 1187bb4cfc2Smrg std %f12, [%sp + CCFSZ + 56]; \ 1197bb4cfc2Smrg std %f14, [%sp + CCFSZ + 64]; \ 1207bb4cfc2Smrg std %f16, [%sp + CCFSZ + 72]; \ 1217bb4cfc2Smrg std %f18, [%sp + CCFSZ + 80]; \ 1227bb4cfc2Smrg std %f20, [%sp + CCFSZ + 88]; \ 1237bb4cfc2Smrg std %f22, [%sp + CCFSZ + 96]; \ 1247bb4cfc2Smrg std %f24, [%sp + CCFSZ + 104]; \ 1257bb4cfc2Smrg std %f26, [%sp + CCFSZ + 112]; \ 1267bb4cfc2Smrg std %f28, [%sp + CCFSZ + 120]; \ 1277bb4cfc2Smrg std %f30, [%sp + CCFSZ + 128]; \ 1287bb4cfc2Smrg1: 1297bb4cfc2Smrg 1307bb4cfc2Smrg#define RESTORE_STATE \ 1317bb4cfc2Smrg /* \ 1327bb4cfc2Smrg * Now that the handler has returned, re-establish all the state \ 1337bb4cfc2Smrg * we just saved above, then do a sigreturn. \ 1347bb4cfc2Smrg */ \ 1357bb4cfc2Smrg tst %l0; /* reload fpu registers? */ \ 1367bb4cfc2Smrg be 1f; /* if not, skip the loads */ \ 1377bb4cfc2Smrg wr %l1, %g0, %y; /* in any case, restore %y */ \ 1387bb4cfc2Smrg ld [%sp + CCFSZ + 0], %fsr; \ 1397bb4cfc2Smrg ldd [%sp + CCFSZ + 8], %f0; \ 1407bb4cfc2Smrg ldd [%sp + CCFSZ + 16], %f2; \ 1417bb4cfc2Smrg ldd [%sp + CCFSZ + 24], %f4; \ 1427bb4cfc2Smrg ldd [%sp + CCFSZ + 32], %f6; \ 1437bb4cfc2Smrg ldd [%sp + CCFSZ + 40], %f8; \ 1447bb4cfc2Smrg ldd [%sp + CCFSZ + 48], %f10; \ 1457bb4cfc2Smrg ldd [%sp + CCFSZ + 56], %f12; \ 1467bb4cfc2Smrg ldd [%sp + CCFSZ + 64], %f14; \ 1477bb4cfc2Smrg ldd [%sp + CCFSZ + 72], %f16; \ 1487bb4cfc2Smrg ldd [%sp + CCFSZ + 80], %f18; \ 1497bb4cfc2Smrg ldd [%sp + CCFSZ + 88], %f20; \ 1507bb4cfc2Smrg ldd [%sp + CCFSZ + 96], %f22; \ 1517bb4cfc2Smrg ldd [%sp + CCFSZ + 104], %f24; \ 1527bb4cfc2Smrg ldd [%sp + CCFSZ + 112], %f26; \ 1537bb4cfc2Smrg ldd [%sp + CCFSZ + 120], %f28; \ 1547bb4cfc2Smrg ldd [%sp + CCFSZ + 128], %f30; \ 1557bb4cfc2Smrg1: \ 1567bb4cfc2Smrg mov %l2, %g2; \ 1577bb4cfc2Smrg mov %l3, %g3; \ 1587bb4cfc2Smrg mov %l4, %g4; \ 1597bb4cfc2Smrg mov %l5, %g5; \ 1607bb4cfc2Smrg mov %l6, %g6; \ 1617bb4cfc2Smrg mov %l7, %g7 162