1/* $NetBSD: sigcode_state.s,v 1.1 2001/06/08 04:49:46 mrg Exp $ */ 2 3/* 4 * Copyright (c) 1996 Paul Kranenburg 5 * Copyright (c) 1996 6 * The President and Fellows of Harvard College. All rights reserved. 7 * Copyright (c) 1992, 1993 8 * The Regents of the University of California. All rights reserved. 9 * 10 * This software was developed by the Computer Systems Engineering group 11 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 12 * contributed to Berkeley. 13 * 14 * All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by the University of 17 * California, Lawrence Berkeley Laboratory. 18 * This product includes software developed by Harvard University. 19 * 20 * Redistribution and use in source and binary forms, with or without 21 * modification, are permitted provided that the following conditions 22 * are met: 23 * 1. Redistributions of source code must retain the above copyright 24 * notice, this list of conditions and the following disclaimer. 25 * 2. Redistributions in binary form must reproduce the above copyright 26 * notice, this list of conditions and the following disclaimer in the 27 * documentation and/or other materials provided with the distribution. 28 * 3. All advertising materials mentioning features or use of this software 29 * must display the following acknowledgement: 30 * This product includes software developed by the University of 31 * California, Berkeley and its contributors. 32 * This product includes software developed by Harvard University. 33 * This product includes software developed by Paul Kranenburg. 34 * 4. Neither the name of the University nor the names of its contributors 35 * may be used to endorse or promote products derived from this software 36 * without specific prior written permission. 37 * 38 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 39 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 40 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 41 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 42 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 43 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 44 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 45 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 46 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 47 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 48 * SUCH DAMAGE. 49 * 50 * @(#)locore.s 8.4 (Berkeley) 12/10/93 51 * from: NetBSD: locore.s,v 1.140 2001/05/26 10:22:32 pk Exp 52 */ 53 54#include <machine/frame.h> 55 56/* 57 * These defines are here so that locore.s, sunos_sigcode.s and svr4_sigcode.s 58 * can all access them. 59 */ 60 61/* 62 * The following code is copied to the top of the user stack when each 63 * process is exec'ed, and signals are `trampolined' off it. 64 * 65 * When this code is run, the stack looks like: 66 * [%sp] 64 bytes to which registers can be dumped 67 * [%sp + 64] signal number (goes in %o0) 68 * [%sp + 64 + 4] signal code (goes in %o1) 69 * [%sp + 64 + 8] placeholder 70 * [%sp + 64 + 12] argument for %o3, currently unsupported (always 0) 71 * [%sp + 64 + 16] first word of saved state (sigcontext) 72 * . 73 * . 74 * . 75 * [%sp + NNN] last word of saved state 76 * (followed by previous stack contents or top of signal stack). 77 * The address of the function to call is in %g1; the old %g1 and %o0 78 * have already been saved in the sigcontext. We are running in a clean 79 * window, all previous windows now being saved to the stack. 80 * 81 * Note that [%sp + 64 + 8] == %sp + 64 + 16. The copy at %sp+64+8 82 * will eventually be removed, with a hole left in its place, if things 83 * work out. 84 */ 85#define SAVE_STATE \ 86 /* \ 87 * XXX the `save' and `restore' below are unnecessary: should \ 88 * replace with simple arithmetic on %sp \ 89 * \ 90 * Make room on the stack for 32 %f registers + %fsr. This comes \ 91 * out to 33*4 or 132 bytes, but this must be aligned to a multiple \ 92 * of 8, or 136 bytes. \ 93 */ \ 94 save %sp, -CCFSZ - 136, %sp; \ 95 mov %g2, %l2; /* save globals in %l registers */ \ 96 mov %g3, %l3; \ 97 mov %g4, %l4; \ 98 mov %g5, %l5; \ 99 mov %g6, %l6; \ 100 mov %g7, %l7; \ 101 /* \ 102 * Saving the fpu registers is expensive, so do it iff the fsr \ 103 * stored in the sigcontext shows that the fpu is enabled. \ 104 */ \ 105 ld [%fp + 64 + 16 + SC_PSR_OFFSET], %l0; \ 106 sethi %hi(PSR_EF), %l1; /* FPU enable is too high for andcc */ \ 107 andcc %l0, %l1, %l0; /* %l0 = fpu enable bit */ \ 108 be 1f; /* if not set, skip the saves */ \ 109 rd %y, %l1; /* in any case, save %y */ \ 110 /* fpu is enabled, oh well */ \ 111 st %fsr, [%sp + CCFSZ + 0]; \ 112 std %f0, [%sp + CCFSZ + 8]; \ 113 std %f2, [%sp + CCFSZ + 16]; \ 114 std %f4, [%sp + CCFSZ + 24]; \ 115 std %f6, [%sp + CCFSZ + 32]; \ 116 std %f8, [%sp + CCFSZ + 40]; \ 117 std %f10, [%sp + CCFSZ + 48]; \ 118 std %f12, [%sp + CCFSZ + 56]; \ 119 std %f14, [%sp + CCFSZ + 64]; \ 120 std %f16, [%sp + CCFSZ + 72]; \ 121 std %f18, [%sp + CCFSZ + 80]; \ 122 std %f20, [%sp + CCFSZ + 88]; \ 123 std %f22, [%sp + CCFSZ + 96]; \ 124 std %f24, [%sp + CCFSZ + 104]; \ 125 std %f26, [%sp + CCFSZ + 112]; \ 126 std %f28, [%sp + CCFSZ + 120]; \ 127 std %f30, [%sp + CCFSZ + 128]; \ 1281: 129 130#define RESTORE_STATE \ 131 /* \ 132 * Now that the handler has returned, re-establish all the state \ 133 * we just saved above, then do a sigreturn. \ 134 */ \ 135 tst %l0; /* reload fpu registers? */ \ 136 be 1f; /* if not, skip the loads */ \ 137 wr %l1, %g0, %y; /* in any case, restore %y */ \ 138 ld [%sp + CCFSZ + 0], %fsr; \ 139 ldd [%sp + CCFSZ + 8], %f0; \ 140 ldd [%sp + CCFSZ + 16], %f2; \ 141 ldd [%sp + CCFSZ + 24], %f4; \ 142 ldd [%sp + CCFSZ + 32], %f6; \ 143 ldd [%sp + CCFSZ + 40], %f8; \ 144 ldd [%sp + CCFSZ + 48], %f10; \ 145 ldd [%sp + CCFSZ + 56], %f12; \ 146 ldd [%sp + CCFSZ + 64], %f14; \ 147 ldd [%sp + CCFSZ + 72], %f16; \ 148 ldd [%sp + CCFSZ + 80], %f18; \ 149 ldd [%sp + CCFSZ + 88], %f20; \ 150 ldd [%sp + CCFSZ + 96], %f22; \ 151 ldd [%sp + CCFSZ + 104], %f24; \ 152 ldd [%sp + CCFSZ + 112], %f26; \ 153 ldd [%sp + CCFSZ + 120], %f28; \ 154 ldd [%sp + CCFSZ + 128], %f30; \ 1551: \ 156 mov %l2, %g2; \ 157 mov %l3, %g3; \ 158 mov %l4, %g4; \ 159 mov %l5, %g5; \ 160 mov %l6, %g6; \ 161 mov %l7, %g7 162