1 /* $NetBSD: psycho.c,v 1.48 2002/05/16 20:28:33 eeh Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002 Eduardo E. Horvath 5 * Copyright (c) 1999, 2000 Matthew R. Green 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The name of the author may not be used to endorse or promote products 17 * derived from this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 24 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 26 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 27 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 #include "opt_ddb.h" 33 34 /* 35 * Support for `psycho' and `psycho+' UPA to PCI bridge and 36 * UltraSPARC IIi and IIe `sabre' PCI controllers. 37 */ 38 39 #ifdef DEBUG 40 #define PDB_PROM 0x01 41 #define PDB_BUSMAP 0x02 42 #define PDB_INTR 0x04 43 int psycho_debug = 0x0; 44 #define DPRINTF(l, s) do { if (psycho_debug & l) printf s; } while (0) 45 #else 46 #define DPRINTF(l, s) 47 #endif 48 49 #include <sys/param.h> 50 #include <sys/device.h> 51 #include <sys/errno.h> 52 #include <sys/extent.h> 53 #include <sys/malloc.h> 54 #include <sys/systm.h> 55 #include <sys/time.h> 56 #include <sys/reboot.h> 57 58 #define _SPARC_BUS_DMA_PRIVATE 59 #include <machine/bus.h> 60 #include <machine/autoconf.h> 61 #include <machine/psl.h> 62 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcireg.h> 65 66 #include <sparc64/dev/iommureg.h> 67 #include <sparc64/dev/iommuvar.h> 68 #include <sparc64/dev/psychoreg.h> 69 #include <sparc64/dev/psychovar.h> 70 #include <sparc64/sparc64/cache.h> 71 72 #include "ioconf.h" 73 74 static pci_chipset_tag_t psycho_alloc_chipset __P((struct psycho_pbm *, int, 75 pci_chipset_tag_t)); 76 static void psycho_get_bus_range __P((int, int *)); 77 static void psycho_get_ranges __P((int, struct psycho_ranges **, int *)); 78 static void psycho_set_intr __P((struct psycho_softc *, int, void *, 79 u_int64_t *, u_int64_t *)); 80 81 /* Interrupt handlers */ 82 static int psycho_ue __P((void *)); 83 static int psycho_ce __P((void *)); 84 static int psycho_bus_a __P((void *)); 85 static int psycho_bus_b __P((void *)); 86 static int psycho_powerfail __P((void *)); 87 static int psycho_wakeup __P((void *)); 88 89 90 /* IOMMU support */ 91 static void psycho_iommu_init __P((struct psycho_softc *, int)); 92 93 /* 94 * bus space and bus dma support for UltraSPARC `psycho'. note that most 95 * of the bus dma support is provided by the iommu dvma controller. 96 */ 97 static paddr_t psycho_bus_mmap __P((bus_space_tag_t, bus_addr_t, off_t, 98 int, int)); 99 static int _psycho_bus_map __P((bus_space_tag_t, bus_addr_t, bus_size_t, int, 100 vaddr_t, bus_space_handle_t *)); 101 static void *psycho_intr_establish __P((bus_space_tag_t, int, int, int, 102 int (*) __P((void *)), void *)); 103 104 static int psycho_dmamap_load __P((bus_dma_tag_t, bus_dmamap_t, void *, 105 bus_size_t, struct proc *, int)); 106 static void psycho_dmamap_unload __P((bus_dma_tag_t, bus_dmamap_t)); 107 static int psycho_dmamap_load_raw __P((bus_dma_tag_t, bus_dmamap_t, 108 bus_dma_segment_t *, int, bus_size_t, int)); 109 static void psycho_dmamap_sync __P((bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 110 bus_size_t, int)); 111 int psycho_dmamem_alloc __P((bus_dma_tag_t, bus_size_t, bus_size_t, bus_size_t, 112 bus_dma_segment_t *, int, int *, int)); 113 void psycho_dmamem_free __P((bus_dma_tag_t, bus_dma_segment_t *, int)); 114 int psycho_dmamem_map __P((bus_dma_tag_t, bus_dma_segment_t *, int, size_t, 115 caddr_t *, int)); 116 void psycho_dmamem_unmap __P((bus_dma_tag_t, caddr_t, size_t)); 117 118 /* base pci_chipset */ 119 extern struct sparc_pci_chipset _sparc_pci_chipset; 120 121 /* 122 * autoconfiguration 123 */ 124 static int psycho_match __P((struct device *, struct cfdata *, void *)); 125 static void psycho_attach __P((struct device *, struct device *, void *)); 126 static int psycho_print __P((void *aux, const char *p)); 127 128 struct cfattach psycho_ca = { 129 sizeof(struct psycho_softc), psycho_match, psycho_attach 130 }; 131 132 /* 133 * "sabre" is the UltraSPARC IIi onboard UPA to PCI bridge. It manages a 134 * single PCI bus and does not have a streaming buffer. It often has an APB 135 * (advanced PCI bridge) connected to it, which was designed specifically for 136 * the IIi. The APB let's the IIi handle two independednt PCI buses, and 137 * appears as two "simba"'s underneath the sabre. 138 * 139 * "psycho" and "psycho+" is a dual UPA to PCI bridge. It sits on the UPA bus 140 * and manages two PCI buses. "psycho" has two 64-bit 33MHz buses, while 141 * "psycho+" controls both a 64-bit 33Mhz and a 64-bit 66Mhz PCI bus. You 142 * will usually find a "psycho+" since I don't think the original "psycho" 143 * ever shipped, and if it did it would be in the U30. 144 * 145 * Each "psycho" PCI bus appears as a separate OFW node, but since they are 146 * both part of the same IC, they only have a single register space. As such, 147 * they need to be configured together, even though the autoconfiguration will 148 * attach them separately. 149 * 150 * On UltraIIi machines, "sabre" itself usually takes pci0, with "simba" often 151 * as pci1 and pci2, although they have been implemented with other PCI bus 152 * numbers on some machines. 153 * 154 * On UltraII machines, there can be any number of "psycho+" ICs, each 155 * providing two PCI buses. 156 * 157 * 158 * XXXX The psycho/sabre node has an `interrupts' attribute. They contain 159 * the values of the following interrupts in this order: 160 * 161 * PCI Bus Error (30) 162 * DMA UE (2e) 163 * DMA CE (2f) 164 * Power Fail (25) 165 * 166 * We really should attach handlers for each. 167 * 168 */ 169 170 #define ROM_PCI_NAME "pci" 171 172 struct psycho_names { 173 char *p_name; 174 int p_type; 175 } psycho_names[] = { 176 { "SUNW,psycho", PSYCHO_MODE_PSYCHO }, 177 { "pci108e,8000", PSYCHO_MODE_PSYCHO }, 178 { "SUNW,sabre", PSYCHO_MODE_SABRE }, 179 { "pci108e,a000", PSYCHO_MODE_SABRE }, 180 { "pci108e,a001", PSYCHO_MODE_SABRE }, 181 { NULL, 0 } 182 }; 183 184 static int 185 psycho_match(parent, match, aux) 186 struct device *parent; 187 struct cfdata *match; 188 void *aux; 189 { 190 struct mainbus_attach_args *ma = aux; 191 char *model = PROM_getpropstring(ma->ma_node, "model"); 192 int i; 193 194 /* match on a name of "pci" and a sabre or a psycho */ 195 if (strcmp(ma->ma_name, ROM_PCI_NAME) == 0) { 196 for (i=0; psycho_names[i].p_name; i++) 197 if (strcmp(model, psycho_names[i].p_name) == 0) 198 return (1); 199 200 model = PROM_getpropstring(ma->ma_node, "compatible"); 201 for (i=0; psycho_names[i].p_name; i++) 202 if (strcmp(model, psycho_names[i].p_name) == 0) 203 return (1); 204 } 205 return (0); 206 } 207 208 /* 209 * SUNW,psycho initialisation .. 210 * - find the per-psycho registers 211 * - figure out the IGN. 212 * - find our partner psycho 213 * - configure ourselves 214 * - bus range, bus, 215 * - get interrupt-map and interrupt-map-mask 216 * - setup the chipsets. 217 * - if we're the first of the pair, initialise the IOMMU, otherwise 218 * just copy it's tags and addresses. 219 */ 220 static void 221 psycho_attach(parent, self, aux) 222 struct device *parent, *self; 223 void *aux; 224 { 225 struct psycho_softc *sc = (struct psycho_softc *)self; 226 struct psycho_softc *osc = NULL; 227 struct psycho_pbm *pp; 228 struct pcibus_attach_args pba; 229 struct mainbus_attach_args *ma = aux; 230 bus_space_handle_t bh; 231 u_int64_t csr; 232 int psycho_br[2], n, i; 233 bus_space_handle_t pci_ctl; 234 char *model = PROM_getpropstring(ma->ma_node, "model"); 235 236 printf("\n"); 237 238 sc->sc_node = ma->ma_node; 239 sc->sc_bustag = ma->ma_bustag; 240 sc->sc_dmatag = ma->ma_dmatag; 241 242 /* 243 * Identify the device. 244 */ 245 for (i=0; psycho_names[i].p_name; i++) 246 if (strcmp(model, psycho_names[i].p_name) == 0) { 247 sc->sc_mode = psycho_names[i].p_type; 248 goto found; 249 } 250 251 model = PROM_getpropstring(ma->ma_node, "compatible"); 252 for (i=0; psycho_names[i].p_name; i++) 253 if (strcmp(model, psycho_names[i].p_name) == 0) { 254 sc->sc_mode = psycho_names[i].p_type; 255 goto found; 256 } 257 258 panic("unknown psycho model %s", model); 259 found: 260 261 /* 262 * The psycho gets three register banks: 263 * (0) per-PBM configuration and status registers 264 * (1) per-PBM PCI configuration space, containing only the 265 * PBM 256-byte PCI header 266 * (2) the shared psycho configuration registers (struct psychoreg) 267 */ 268 269 /* Register layouts are different. stuupid. */ 270 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 271 sc->sc_basepaddr = (paddr_t)ma->ma_reg[2].ur_paddr; 272 273 if (ma->ma_naddress > 2) { 274 sparc_promaddr_to_handle(sc->sc_bustag, 275 ma->ma_address[2], &sc->sc_bh); 276 sparc_promaddr_to_handle(sc->sc_bustag, 277 ma->ma_address[0], &pci_ctl); 278 279 sc->sc_regs = (struct psychoreg *) 280 bus_space_vaddr(sc->sc_bustag, sc->sc_bh); 281 } else if (ma->ma_nreg > 2) { 282 283 /* We need to map this in ourselves. */ 284 if (bus_space_map(sc->sc_bustag, 285 ma->ma_reg[2].ur_paddr, 286 ma->ma_reg[2].ur_len, BUS_SPACE_MAP_LINEAR, 287 &sc->sc_bh)) 288 panic("psycho_attach: cannot map regs"); 289 sc->sc_regs = (struct psychoreg *) 290 bus_space_vaddr(sc->sc_bustag, sc->sc_bh); 291 292 if (bus_space_map(sc->sc_bustag, 293 ma->ma_reg[0].ur_paddr, 294 ma->ma_reg[0].ur_len, BUS_SPACE_MAP_LINEAR, 295 &pci_ctl)) 296 panic("psycho_attach: cannot map ctl"); 297 } else 298 panic("psycho_attach: %d not enough registers", 299 ma->ma_nreg); 300 } else { 301 sc->sc_basepaddr = (paddr_t)ma->ma_reg[0].ur_paddr; 302 303 if (ma->ma_naddress) { 304 sparc_promaddr_to_handle(sc->sc_bustag, 305 ma->ma_address[0], &sc->sc_bh); 306 sc->sc_regs = (struct psychoreg *) 307 bus_space_vaddr(sc->sc_bustag, sc->sc_bh); 308 bus_space_subregion(sc->sc_bustag, sc->sc_bh, 309 offsetof(struct psychoreg, psy_pcictl), 310 sizeof(struct pci_ctl), &pci_ctl); 311 } else if (ma->ma_nreg) { 312 313 /* We need to map this in ourselves. */ 314 if (bus_space_map(sc->sc_bustag, 315 ma->ma_reg[0].ur_paddr, 316 ma->ma_reg[0].ur_len, BUS_SPACE_MAP_LINEAR, 317 &sc->sc_bh)) 318 panic("psycho_attach: cannot map regs"); 319 sc->sc_regs = (struct psychoreg *) 320 bus_space_vaddr(sc->sc_bustag, sc->sc_bh); 321 322 bus_space_subregion(sc->sc_bustag, sc->sc_bh, 323 offsetof(struct psychoreg, psy_pcictl), 324 sizeof(struct pci_ctl), &pci_ctl); 325 } else 326 panic("psycho_attach: %d not enough registers", 327 ma->ma_nreg); 328 } 329 330 331 csr = bus_space_read_8(sc->sc_bustag, sc->sc_bh, 332 offsetof(struct psychoreg, psy_csr)); 333 sc->sc_ign = 0x7c0; /* APB IGN is always 0x7c */ 334 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) 335 sc->sc_ign = PSYCHO_GCSR_IGN(csr) << 6; 336 337 printf("%s: impl %d, version %d: ign %x ", 338 model, PSYCHO_GCSR_IMPL(csr), PSYCHO_GCSR_VERS(csr), 339 sc->sc_ign); 340 /* 341 * Match other psycho's that are already configured against 342 * the base physical address. This will be the same for a 343 * pair of devices that share register space. 344 */ 345 for (n = 0; n < psycho_cd.cd_ndevs; n++) { 346 347 struct psycho_softc *asc = 348 (struct psycho_softc *)psycho_cd.cd_devs[n]; 349 350 if (asc == NULL || asc == sc) 351 /* This entry is not there or it is me */ 352 continue; 353 354 if (asc->sc_basepaddr != sc->sc_basepaddr) 355 /* This is an unrelated psycho */ 356 continue; 357 358 /* Found partner */ 359 osc = asc; 360 break; 361 } 362 363 364 /* Oh, dear. OK, lets get started */ 365 366 /* 367 * Setup the PCI control register 368 */ 369 csr = bus_space_read_8(sc->sc_bustag, pci_ctl, 370 offsetof(struct pci_ctl, pci_csr)); 371 csr |= PCICTL_MRLM | 372 PCICTL_ARB_PARK | 373 PCICTL_ERRINTEN | 374 PCICTL_4ENABLE; 375 csr &= ~(PCICTL_SERR | 376 PCICTL_CPU_PRIO | 377 PCICTL_ARB_PRIO | 378 PCICTL_RTRYWAIT); 379 bus_space_write_8(sc->sc_bustag, pci_ctl, 380 offsetof(struct pci_ctl, pci_csr), csr); 381 382 383 /* 384 * Allocate our psycho_pbm 385 */ 386 pp = sc->sc_psycho_this = malloc(sizeof *pp, M_DEVBUF, M_NOWAIT); 387 if (pp == NULL) 388 panic("could not allocate psycho pbm"); 389 390 memset(pp, 0, sizeof *pp); 391 392 pp->pp_sc = sc; 393 394 /* grab the psycho ranges */ 395 psycho_get_ranges(sc->sc_node, &pp->pp_range, &pp->pp_nrange); 396 397 /* get the bus-range for the psycho */ 398 psycho_get_bus_range(sc->sc_node, psycho_br); 399 400 pba.pba_bus = psycho_br[0]; 401 pba.pba_bridgetag = NULL; 402 403 printf("bus range %u to %u", psycho_br[0], psycho_br[1]); 404 printf("; PCI bus %d", psycho_br[0]); 405 406 pp->pp_pcictl = pci_ctl; 407 408 /* allocate our tags */ 409 pp->pp_memt = psycho_alloc_mem_tag(pp); 410 pp->pp_iot = psycho_alloc_io_tag(pp); 411 pp->pp_dmat = psycho_alloc_dma_tag(pp); 412 pp->pp_flags = (pp->pp_memt ? PCI_FLAGS_MEM_ENABLED : 0) | 413 (pp->pp_iot ? PCI_FLAGS_IO_ENABLED : 0); 414 415 /* allocate a chipset for this */ 416 pp->pp_pc = psycho_alloc_chipset(pp, sc->sc_node, &_sparc_pci_chipset); 417 418 /* setup the rest of the psycho pbm */ 419 pba.pba_pc = psycho_alloc_chipset(pp, sc->sc_node, pp->pp_pc); 420 421 printf("\n"); 422 423 /* 424 * And finally, if we're a sabre or the first of a pair of psycho's to 425 * arrive here, start up the IOMMU and get a config space tag. 426 */ 427 if (osc == NULL) { 428 uint64_t timeo; 429 430 /* 431 * Establish handlers for interesting interrupts.... 432 * 433 * XXX We need to remember these and remove this to support 434 * hotplug on the UPA/FHC bus. 435 * 436 * XXX Not all controllers have these, but installing them 437 * is better than trying to sort through this mess. 438 */ 439 psycho_set_intr(sc, 15, psycho_ue, 440 &sc->sc_regs->ue_int_map, 441 &sc->sc_regs->ue_clr_int); 442 psycho_set_intr(sc, 1, psycho_ce, 443 &sc->sc_regs->ce_int_map, 444 &sc->sc_regs->ce_clr_int); 445 psycho_set_intr(sc, 15, psycho_bus_a, 446 &sc->sc_regs->pciaerr_int_map, 447 &sc->sc_regs->pciaerr_clr_int); 448 psycho_set_intr(sc, 15, psycho_bus_b, 449 &sc->sc_regs->pciberr_int_map, 450 &sc->sc_regs->pciberr_clr_int); 451 psycho_set_intr(sc, 15, psycho_powerfail, 452 &sc->sc_regs->power_int_map, 453 &sc->sc_regs->power_clr_int); 454 psycho_set_intr(sc, 1, psycho_wakeup, 455 &sc->sc_regs->pwrmgt_int_map, 456 &sc->sc_regs->pwrmgt_clr_int); 457 458 459 /* 460 * Apparently a number of machines with psycho and psycho+ 461 * controllers have interrupt latency issues. We'll try 462 * setting the interrupt retry timeout to 0xff which gives us 463 * a retry of 3-6 usec (which is what sysio is set to) for the 464 * moment, which seems to help alleviate this problem. 465 */ 466 timeo = sc->sc_regs->intr_retry_timer; 467 if (timeo > 0xfff) { 468 #ifdef DEBUG 469 printf("decreasing interrupt retry timeout " 470 "from %lx to 0xff\n", (long)timeo); 471 #endif 472 sc->sc_regs->intr_retry_timer = 0xff; 473 } 474 475 /* 476 * Setup IOMMU and PCI configuration if we're the first 477 * of a pair of psycho's to arrive here. 478 * 479 * We should calculate a TSB size based on amount of RAM 480 * and number of bus controllers and number an type of 481 * child devices. 482 * 483 * For the moment, 32KB should be more than enough. 484 */ 485 sc->sc_is = malloc(sizeof(struct iommu_state), 486 M_DEVBUF, M_NOWAIT); 487 if (sc->sc_is == NULL) 488 panic("psycho_attach: malloc iommu_state"); 489 sc->sc_is->is_sbvalid[0] = sc->sc_is->is_sbvalid[1] = 0; 490 491 492 if (PROM_getproplen(sc->sc_node, "no-streaming-cache") < 0) { 493 bus_space_subregion(sc->sc_bustag, sc->sc_bh, 494 offsetof(struct pci_ctl, pci_strbuf), 495 sizeof (struct iommu_strbuf), 496 &sc->sc_is->is_sb[0]); 497 sc->sc_is->is_sbvalid[0] = 1; 498 } 499 500 psycho_iommu_init(sc, 2); 501 502 sc->sc_configtag = psycho_alloc_config_tag(sc->sc_psycho_this); 503 504 /* 505 * XXX This is a really ugly hack because PCI config space 506 * is explicitly handled with unmapped accesses. 507 */ 508 i = sc->sc_bustag->type; 509 sc->sc_bustag->type = PCI_CONFIG_BUS_SPACE; 510 if (bus_space_map(sc->sc_bustag, sc->sc_basepaddr + 0x01000000, 511 0x0100000, 0, &bh)) 512 panic("could not map psycho PCI configuration space"); 513 sc->sc_bustag->type = i; 514 sc->sc_configaddr = bh; 515 } else { 516 /* Just copy IOMMU state, config tag and address */ 517 sc->sc_is = osc->sc_is; 518 sc->sc_configtag = osc->sc_configtag; 519 sc->sc_configaddr = osc->sc_configaddr; 520 521 if (PROM_getproplen(sc->sc_node, "no-streaming-cache") < 0) { 522 bus_space_subregion(sc->sc_bustag, sc->sc_bh, 523 offsetof(struct pci_ctl, pci_strbuf), 524 sizeof (struct iommu_strbuf), 525 &sc->sc_is->is_sb[1]); 526 sc->sc_is->is_sbvalid[1] = 1; 527 } 528 iommu_reset(sc->sc_is); 529 } 530 531 /* 532 * attach the pci.. note we pass PCI A tags, etc., for the sabre here. 533 */ 534 pba.pba_busname = "pci"; 535 pba.pba_flags = sc->sc_psycho_this->pp_flags; 536 pba.pba_dmat = sc->sc_psycho_this->pp_dmat; 537 pba.pba_iot = sc->sc_psycho_this->pp_iot; 538 pba.pba_memt = sc->sc_psycho_this->pp_memt; 539 540 config_found(self, &pba, psycho_print); 541 } 542 543 static int 544 psycho_print(aux, p) 545 void *aux; 546 const char *p; 547 { 548 549 if (p == NULL) 550 return (UNCONF); 551 return (QUIET); 552 } 553 554 static void 555 psycho_set_intr(sc, ipl, handler, mapper, clearer) 556 struct psycho_softc *sc; 557 int ipl; 558 void *handler; 559 u_int64_t *mapper; 560 u_int64_t *clearer; 561 { 562 struct intrhand *ih; 563 564 ih = (struct intrhand *)malloc(sizeof(struct intrhand), 565 M_DEVBUF, M_NOWAIT); 566 ih->ih_arg = sc; 567 ih->ih_map = mapper; 568 ih->ih_clr = clearer; 569 ih->ih_fun = handler; 570 ih->ih_pil = (1<<ipl); 571 ih->ih_number = INTVEC(*(ih->ih_map)); 572 intr_establish(ipl, ih); 573 *(ih->ih_map) |= INTMAP_V; 574 } 575 576 /* 577 * PCI bus support 578 */ 579 580 /* 581 * allocate a PCI chipset tag and set it's cookie. 582 */ 583 static pci_chipset_tag_t 584 psycho_alloc_chipset(pp, node, pc) 585 struct psycho_pbm *pp; 586 int node; 587 pci_chipset_tag_t pc; 588 { 589 pci_chipset_tag_t npc; 590 591 npc = malloc(sizeof *npc, M_DEVBUF, M_NOWAIT); 592 if (npc == NULL) 593 panic("could not allocate pci_chipset_tag_t"); 594 memcpy(npc, pc, sizeof *pc); 595 npc->cookie = pp; 596 npc->rootnode = node; 597 598 return (npc); 599 } 600 601 /* 602 * grovel the OBP for various psycho properties 603 */ 604 static void 605 psycho_get_bus_range(node, brp) 606 int node; 607 int *brp; 608 { 609 int n; 610 611 if (PROM_getprop(node, "bus-range", sizeof(*brp), &n, (void **)&brp)) 612 panic("could not get psycho bus-range"); 613 if (n != 2) 614 panic("broken psycho bus-range"); 615 DPRINTF(PDB_PROM, ("psycho debug: got `bus-range' for node %08x: %u - %u\n", node, brp[0], brp[1])); 616 } 617 618 static void 619 psycho_get_ranges(node, rp, np) 620 int node; 621 struct psycho_ranges **rp; 622 int *np; 623 { 624 625 if (PROM_getprop(node, "ranges", sizeof(**rp), np, (void **)rp)) 626 panic("could not get psycho ranges"); 627 DPRINTF(PDB_PROM, ("psycho debug: got `ranges' for node %08x: %d entries\n", node, *np)); 628 } 629 630 /* 631 * Interrupt handlers. 632 */ 633 634 static int 635 psycho_ue(arg) 636 void *arg; 637 { 638 struct psycho_softc *sc = (struct psycho_softc *)arg; 639 struct psychoreg *regs = sc->sc_regs; 640 long long afsr = regs->psy_ue_afsr; 641 long long afar = regs->psy_ue_afar; 642 long size = NBPG<<(sc->sc_is->is_tsbsize); 643 struct iommu_state *is = sc->sc_is; 644 char bits[128]; 645 646 /* 647 * It's uncorrectable. Dump the regs and panic. 648 */ 649 printf("%s: uncorrectable DMA error AFAR %llx pa %llx AFSR %llx:\n%s\n", 650 sc->sc_dev.dv_xname, afar, 651 (long long)iommu_extract(is, (vaddr_t)afar), afsr, 652 bitmask_snprintf(afsr, PSYCHO_UE_AFSR_BITS, 653 bits, sizeof(bits))); 654 655 /* Sometimes the AFAR points to an IOTSB entry */ 656 if (afar >= is->is_ptsb && afar < is->is_ptsb + size) { 657 printf("IOVA %llx IOTTE %llx\n", 658 (long long)((afar - is->is_ptsb) * NBPG + is->is_dvmabase), 659 (long long)ldxa(afar, ASI_PHYS_CACHED)); 660 } 661 #ifdef DDB 662 Debugger(); 663 #endif 664 regs->psy_ue_afar = 0; 665 regs->psy_ue_afsr = 0; 666 return (1); 667 } 668 static int 669 psycho_ce(arg) 670 void *arg; 671 { 672 struct psycho_softc *sc = (struct psycho_softc *)arg; 673 struct psychoreg *regs = sc->sc_regs; 674 675 /* 676 * It's correctable. Dump the regs and continue. 677 */ 678 679 printf("%s: correctable DMA error AFAR %llx AFSR %llx\n", 680 sc->sc_dev.dv_xname, 681 (long long)regs->psy_ce_afar, (long long)regs->psy_ce_afsr); 682 return (1); 683 } 684 static int 685 psycho_bus_a(arg) 686 void *arg; 687 { 688 struct psycho_softc *sc = (struct psycho_softc *)arg; 689 struct psychoreg *regs = sc->sc_regs; 690 691 /* 692 * It's uncorrectable. Dump the regs and panic. 693 */ 694 695 panic("%s: PCI bus A error AFAR %llx AFSR %llx\n", 696 sc->sc_dev.dv_xname, 697 (long long)regs->psy_pcictl[0].pci_afar, 698 (long long)regs->psy_pcictl[0].pci_afsr); 699 return (1); 700 } 701 static int 702 psycho_bus_b(arg) 703 void *arg; 704 { 705 struct psycho_softc *sc = (struct psycho_softc *)arg; 706 struct psychoreg *regs = sc->sc_regs; 707 708 /* 709 * It's uncorrectable. Dump the regs and panic. 710 */ 711 712 panic("%s: PCI bus B error AFAR %llx AFSR %llx\n", 713 sc->sc_dev.dv_xname, 714 (long long)regs->psy_pcictl[0].pci_afar, 715 (long long)regs->psy_pcictl[0].pci_afsr); 716 return (1); 717 } 718 static int 719 psycho_powerfail(arg) 720 void *arg; 721 { 722 723 /* 724 * We lost power. Try to shut down NOW. 725 */ 726 printf("Power Failure Detected: Shutting down NOW.\n"); 727 cpu_reboot(RB_POWERDOWN|RB_HALT, NULL); 728 return (1); 729 } 730 static 731 int psycho_wakeup(arg) 732 void *arg; 733 { 734 struct psycho_softc *sc = (struct psycho_softc *)arg; 735 736 /* 737 * Gee, we don't really have a framework to deal with this 738 * properly. 739 */ 740 printf("%s: power management wakeup\n", sc->sc_dev.dv_xname); 741 return (1); 742 } 743 744 745 746 /* 747 * initialise the IOMMU.. 748 */ 749 void 750 psycho_iommu_init(sc, tsbsize) 751 struct psycho_softc *sc; 752 int tsbsize; 753 { 754 char *name; 755 struct iommu_state *is = sc->sc_is; 756 u_int32_t iobase = -1; 757 int *vdma = NULL; 758 int nitem; 759 760 /* punch in our copies */ 761 is->is_bustag = sc->sc_bustag; 762 bus_space_subregion(sc->sc_bustag, sc->sc_bh, 763 offsetof(struct psychoreg, psy_iommu), 764 sizeof (struct iommureg), 765 &is->is_iommu); 766 767 /* 768 * Separate the men from the boys. Get the `virtual-dma' 769 * property for sabre and use that to make sure the damn 770 * iommu works. 771 * 772 * We could query the `#virtual-dma-size-cells' and 773 * `#virtual-dma-addr-cells' and DTRT, but I'm lazy. 774 */ 775 if (!PROM_getprop(sc->sc_node, "virtual-dma", sizeof(vdma), &nitem, 776 (void **)&vdma)) { 777 /* Damn. Gotta use these values. */ 778 iobase = vdma[0]; 779 #define TSBCASE(x) case 1<<((x)+23): tsbsize = (x); break 780 switch (vdma[1]) { 781 TSBCASE(1); TSBCASE(2); TSBCASE(3); 782 TSBCASE(4); TSBCASE(5); TSBCASE(6); 783 default: 784 printf("bogus tsb size %x, using 7\n", vdma[1]); 785 TSBCASE(7); 786 } 787 #undef TSBCASE 788 } 789 790 /* give us a nice name.. */ 791 name = (char *)malloc(32, M_DEVBUF, M_NOWAIT); 792 if (name == 0) 793 panic("couldn't malloc iommu name"); 794 snprintf(name, 32, "%s dvma", sc->sc_dev.dv_xname); 795 796 iommu_init(name, is, tsbsize, iobase); 797 } 798 799 /* 800 * below here is bus space and bus dma support 801 */ 802 bus_space_tag_t 803 psycho_alloc_bus_tag(pp, type) 804 struct psycho_pbm *pp; 805 int type; 806 { 807 struct psycho_softc *sc = pp->pp_sc; 808 bus_space_tag_t bt; 809 810 bt = (bus_space_tag_t) 811 malloc(sizeof(struct sparc_bus_space_tag), M_DEVBUF, M_NOWAIT); 812 if (bt == NULL) 813 panic("could not allocate psycho bus tag"); 814 815 bzero(bt, sizeof *bt); 816 bt->cookie = pp; 817 bt->parent = sc->sc_bustag; 818 bt->type = type; 819 bt->sparc_bus_map = _psycho_bus_map; 820 bt->sparc_bus_mmap = psycho_bus_mmap; 821 bt->sparc_intr_establish = psycho_intr_establish; 822 return (bt); 823 } 824 825 bus_dma_tag_t 826 psycho_alloc_dma_tag(pp) 827 struct psycho_pbm *pp; 828 { 829 struct psycho_softc *sc = pp->pp_sc; 830 bus_dma_tag_t dt, pdt = sc->sc_dmatag; 831 832 dt = (bus_dma_tag_t) 833 malloc(sizeof(struct sparc_bus_dma_tag), M_DEVBUF, M_NOWAIT); 834 if (dt == NULL) 835 panic("could not allocate psycho dma tag"); 836 837 bzero(dt, sizeof *dt); 838 dt->_cookie = pp; 839 dt->_parent = pdt; 840 #define PCOPY(x) dt->x = pdt->x 841 PCOPY(_dmamap_create); 842 PCOPY(_dmamap_destroy); 843 dt->_dmamap_load = psycho_dmamap_load; 844 PCOPY(_dmamap_load_mbuf); 845 PCOPY(_dmamap_load_uio); 846 dt->_dmamap_load_raw = psycho_dmamap_load_raw; 847 dt->_dmamap_unload = psycho_dmamap_unload; 848 dt->_dmamap_sync = psycho_dmamap_sync; 849 dt->_dmamem_alloc = psycho_dmamem_alloc; 850 dt->_dmamem_free = psycho_dmamem_free; 851 dt->_dmamem_map = psycho_dmamem_map; 852 dt->_dmamem_unmap = psycho_dmamem_unmap; 853 PCOPY(_dmamem_mmap); 854 #undef PCOPY 855 return (dt); 856 } 857 858 /* 859 * bus space support. <sparc64/dev/psychoreg.h> has a discussion about 860 * PCI physical addresses. 861 */ 862 863 static int get_childspace __P((int)); 864 865 static int 866 get_childspace(type) 867 int type; 868 { 869 int ss; 870 871 switch (type) { 872 case PCI_CONFIG_BUS_SPACE: 873 ss = 0x00; 874 break; 875 case PCI_IO_BUS_SPACE: 876 ss = 0x01; 877 break; 878 case PCI_MEMORY_BUS_SPACE: 879 ss = 0x02; 880 break; 881 #if 0 882 /* we don't do 64 bit memory space */ 883 case PCI_MEMORY64_BUS_SPACE: 884 ss = 0x03; 885 break; 886 #endif 887 default: 888 panic("get_childspace: unknown bus type"); 889 } 890 891 return (ss); 892 } 893 894 static int 895 _psycho_bus_map(t, offset, size, flags, unused, hp) 896 bus_space_tag_t t; 897 bus_addr_t offset; 898 bus_size_t size; 899 int flags; 900 vaddr_t unused; 901 bus_space_handle_t *hp; 902 { 903 struct psycho_pbm *pp = t->cookie; 904 struct psycho_softc *sc = pp->pp_sc; 905 int i, ss; 906 907 DPRINTF(PDB_BUSMAP, 908 ("_psycho_bus_map: type %d off %qx sz %qx flags %d", 909 t->type, (unsigned long long)offset, 910 (unsigned long long)size, flags)); 911 912 ss = get_childspace(t->type); 913 DPRINTF(PDB_BUSMAP, (" cspace %d", ss)); 914 915 for (i = 0; i < pp->pp_nrange; i++) { 916 bus_addr_t paddr; 917 918 if (((pp->pp_range[i].cspace >> 24) & 0x03) != ss) 919 continue; 920 921 paddr = pp->pp_range[i].phys_lo + offset; 922 paddr |= ((bus_addr_t)pp->pp_range[i].phys_hi<<32); 923 DPRINTF(PDB_BUSMAP, ("\n_psycho_bus_map: mapping paddr space %lx offset %lx paddr %qx\n", 924 (long)ss, (long)offset, 925 (unsigned long long)paddr)); 926 return ((*sc->sc_bustag->sparc_bus_map)(t, paddr, size, 927 flags, 0, hp)); 928 } 929 DPRINTF(PDB_BUSMAP, (" FAILED\n")); 930 return (EINVAL); 931 } 932 933 static paddr_t 934 psycho_bus_mmap(t, paddr, off, prot, flags) 935 bus_space_tag_t t; 936 bus_addr_t paddr; 937 off_t off; 938 int prot; 939 int flags; 940 { 941 bus_addr_t offset = paddr; 942 struct psycho_pbm *pp = t->cookie; 943 struct psycho_softc *sc = pp->pp_sc; 944 int i, ss; 945 946 ss = get_childspace(t->type); 947 948 DPRINTF(PDB_BUSMAP, ("_psycho_bus_mmap: prot %x flags %d pa %qx\n", 949 prot, flags, (unsigned long long)paddr)); 950 951 for (i = 0; i < pp->pp_nrange; i++) { 952 bus_addr_t paddr; 953 954 if (((pp->pp_range[i].cspace >> 24) & 0x03) != ss) 955 continue; 956 957 paddr = pp->pp_range[i].phys_lo + offset; 958 paddr |= ((bus_addr_t)pp->pp_range[i].phys_hi<<32); 959 DPRINTF(PDB_BUSMAP, ("\n_psycho_bus_mmap: mapping paddr " 960 "space %lx offset %lx paddr %qx\n", 961 (long)ss, (long)offset, 962 (unsigned long long)paddr)); 963 return (bus_space_mmap(sc->sc_bustag, paddr, off, 964 prot, flags)); 965 } 966 967 return (-1); 968 } 969 970 971 /* 972 * install an interrupt handler for a PCI device 973 */ 974 void * 975 psycho_intr_establish(t, ihandle, level, flags, handler, arg) 976 bus_space_tag_t t; 977 int ihandle; 978 int level; 979 int flags; 980 int (*handler) __P((void *)); 981 void *arg; 982 { 983 struct psycho_pbm *pp = t->cookie; 984 struct psycho_softc *sc = pp->pp_sc; 985 struct intrhand *ih; 986 volatile u_int64_t *intrmapptr = NULL, *intrclrptr = NULL; 987 int64_t intrmap = 0; 988 int ino; 989 long vec = INTVEC(ihandle); 990 991 ih = (struct intrhand *) 992 malloc(sizeof(struct intrhand), M_DEVBUF, M_NOWAIT); 993 if (ih == NULL) 994 return (NULL); 995 996 /* 997 * Hunt through all the interrupt mapping regs to look for our 998 * interrupt vector. 999 * 1000 * XXX We only compare INOs rather than IGNs since the firmware may 1001 * not provide the IGN and the IGN is constant for all device on that 1002 * PCI controller. This could cause problems for the FFB/external 1003 * interrupt which has a full vector that can be set arbitrarily. 1004 */ 1005 1006 1007 DPRINTF(PDB_INTR, ("\npsycho_intr_establish: ihandle %x vec %lx", ihandle, vec)); 1008 ino = INTINO(vec); 1009 DPRINTF(PDB_INTR, (" ino %x", ino)); 1010 1011 /* If the device didn't ask for an IPL, use the one encoded. */ 1012 if (level == IPL_NONE) level = INTLEV(vec); 1013 /* If it still has no level, print a warning and assign IPL 2 */ 1014 if (level == IPL_NONE) { 1015 printf("ERROR: no IPL, setting IPL 2.\n"); 1016 level = 2; 1017 } 1018 1019 if ((flags & BUS_INTR_ESTABLISH_SOFTINTR) == 0) { 1020 1021 DPRINTF(PDB_INTR, ("\npsycho: intr %lx: %p\nHunting for IRQ...\n", 1022 (long)ino, intrlev[ino])); 1023 1024 /* Hunt thru obio first */ 1025 for (intrmapptr = &sc->sc_regs->scsi_int_map, 1026 intrclrptr = &sc->sc_regs->scsi_clr_int; 1027 intrmapptr <= &sc->sc_regs->ffb1_int_map; 1028 intrmapptr++, intrclrptr++) { 1029 if (INTINO(*intrmapptr) == ino) 1030 goto found; 1031 } 1032 1033 /* Now do PCI interrupts */ 1034 for (intrmapptr = &sc->sc_regs->pcia_slot0_int, 1035 intrclrptr = &sc->sc_regs->pcia0_clr_int[0]; 1036 intrmapptr <= &sc->sc_regs->pcib_slot3_int; 1037 intrmapptr++, intrclrptr += 4) { 1038 if (((*intrmapptr ^ vec) & 0x3c) == 0) { 1039 intrclrptr += vec & 0x3; 1040 goto found; 1041 } 1042 } 1043 printf("Cannot find interrupt vector %lx\n", vec); 1044 return (NULL); 1045 1046 found: 1047 /* Register the map and clear intr registers */ 1048 ih->ih_map = intrmapptr; 1049 ih->ih_clr = intrclrptr; 1050 } 1051 #ifdef NOT_DEBUG 1052 if (psycho_debug & PDB_INTR) { 1053 long i; 1054 1055 for (i = 0; i < 500000000; i++) 1056 continue; 1057 } 1058 #endif 1059 1060 ih->ih_fun = handler; 1061 ih->ih_arg = arg; 1062 ih->ih_pil = level; 1063 ih->ih_number = ino | sc->sc_ign; 1064 1065 DPRINTF(PDB_INTR, ( 1066 "; installing handler %p arg %p with ino %u pil %u\n", 1067 handler, arg, (u_int)ino, (u_int)ih->ih_pil)); 1068 1069 intr_establish(ih->ih_pil, ih); 1070 1071 /* 1072 * Enable the interrupt now we have the handler installed. 1073 * Read the current value as we can't change it besides the 1074 * valid bit so so make sure only this bit is changed. 1075 * 1076 * XXXX --- we really should use bus_space for this. 1077 */ 1078 if (intrmapptr) { 1079 intrmap = *intrmapptr; 1080 DPRINTF(PDB_INTR, ("; read intrmap = %016qx", 1081 (unsigned long long)intrmap)); 1082 1083 /* Enable the interrupt */ 1084 intrmap |= INTMAP_V; 1085 DPRINTF(PDB_INTR, ("; addr of intrmapptr = %p", intrmapptr)); 1086 DPRINTF(PDB_INTR, ("; writing intrmap = %016qx\n", 1087 (unsigned long long)intrmap)); 1088 *intrmapptr = intrmap; 1089 DPRINTF(PDB_INTR, ("; reread intrmap = %016qx", 1090 (unsigned long long)(intrmap = *intrmapptr))); 1091 } 1092 return (ih); 1093 } 1094 1095 /* 1096 * hooks into the iommu dvma calls. 1097 */ 1098 int 1099 psycho_dmamap_load(t, map, buf, buflen, p, flags) 1100 bus_dma_tag_t t; 1101 bus_dmamap_t map; 1102 void *buf; 1103 bus_size_t buflen; 1104 struct proc *p; 1105 int flags; 1106 { 1107 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1108 struct psycho_softc *sc = pp->pp_sc; 1109 1110 return (iommu_dvmamap_load(t, sc->sc_is, map, buf, buflen, p, flags)); 1111 } 1112 1113 void 1114 psycho_dmamap_unload(t, map) 1115 bus_dma_tag_t t; 1116 bus_dmamap_t map; 1117 { 1118 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1119 struct psycho_softc *sc = pp->pp_sc; 1120 1121 iommu_dvmamap_unload(t, sc->sc_is, map); 1122 } 1123 1124 int 1125 psycho_dmamap_load_raw(t, map, segs, nsegs, size, flags) 1126 bus_dma_tag_t t; 1127 bus_dmamap_t map; 1128 bus_dma_segment_t *segs; 1129 int nsegs; 1130 bus_size_t size; 1131 int flags; 1132 { 1133 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1134 struct psycho_softc *sc = pp->pp_sc; 1135 1136 return (iommu_dvmamap_load_raw(t, sc->sc_is, map, segs, nsegs, flags, size)); 1137 } 1138 1139 void 1140 psycho_dmamap_sync(t, map, offset, len, ops) 1141 bus_dma_tag_t t; 1142 bus_dmamap_t map; 1143 bus_addr_t offset; 1144 bus_size_t len; 1145 int ops; 1146 { 1147 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1148 struct psycho_softc *sc = pp->pp_sc; 1149 1150 if (ops & (BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE)) { 1151 /* Flush the CPU then the IOMMU */ 1152 bus_dmamap_sync(t->_parent, map, offset, len, ops); 1153 iommu_dvmamap_sync(t, sc->sc_is, map, offset, len, ops); 1154 } 1155 if (ops & (BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE)) { 1156 /* Flush the IOMMU then the CPU */ 1157 iommu_dvmamap_sync(t, sc->sc_is, map, offset, len, ops); 1158 bus_dmamap_sync(t->_parent, map, offset, len, ops); 1159 } 1160 1161 } 1162 1163 int 1164 psycho_dmamem_alloc(t, size, alignment, boundary, segs, nsegs, rsegs, flags) 1165 bus_dma_tag_t t; 1166 bus_size_t size; 1167 bus_size_t alignment; 1168 bus_size_t boundary; 1169 bus_dma_segment_t *segs; 1170 int nsegs; 1171 int *rsegs; 1172 int flags; 1173 { 1174 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1175 struct psycho_softc *sc = pp->pp_sc; 1176 1177 return (iommu_dvmamem_alloc(t, sc->sc_is, size, alignment, boundary, 1178 segs, nsegs, rsegs, flags)); 1179 } 1180 1181 void 1182 psycho_dmamem_free(t, segs, nsegs) 1183 bus_dma_tag_t t; 1184 bus_dma_segment_t *segs; 1185 int nsegs; 1186 { 1187 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1188 struct psycho_softc *sc = pp->pp_sc; 1189 1190 iommu_dvmamem_free(t, sc->sc_is, segs, nsegs); 1191 } 1192 1193 int 1194 psycho_dmamem_map(t, segs, nsegs, size, kvap, flags) 1195 bus_dma_tag_t t; 1196 bus_dma_segment_t *segs; 1197 int nsegs; 1198 size_t size; 1199 caddr_t *kvap; 1200 int flags; 1201 { 1202 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1203 struct psycho_softc *sc = pp->pp_sc; 1204 1205 return (iommu_dvmamem_map(t, sc->sc_is, segs, nsegs, size, kvap, flags)); 1206 } 1207 1208 void 1209 psycho_dmamem_unmap(t, kva, size) 1210 bus_dma_tag_t t; 1211 caddr_t kva; 1212 size_t size; 1213 { 1214 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1215 struct psycho_softc *sc = pp->pp_sc; 1216 1217 iommu_dvmamem_unmap(t, sc->sc_is, kva, size); 1218 } 1219