1 /* $NetBSD: psycho.c,v 1.55 2002/10/02 16:02:19 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002 Eduardo E. Horvath 5 * Copyright (c) 1999, 2000 Matthew R. Green 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The name of the author may not be used to endorse or promote products 17 * derived from this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 24 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 26 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 27 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 #include "opt_ddb.h" 33 34 /* 35 * Support for `psycho' and `psycho+' UPA to PCI bridge and 36 * UltraSPARC IIi and IIe `sabre' PCI controllers. 37 */ 38 39 #ifdef DEBUG 40 #define PDB_PROM 0x01 41 #define PDB_BUSMAP 0x02 42 #define PDB_INTR 0x04 43 int psycho_debug = 0x0; 44 #define DPRINTF(l, s) do { if (psycho_debug & l) printf s; } while (0) 45 #else 46 #define DPRINTF(l, s) 47 #endif 48 49 #include <sys/param.h> 50 #include <sys/device.h> 51 #include <sys/errno.h> 52 #include <sys/extent.h> 53 #include <sys/malloc.h> 54 #include <sys/systm.h> 55 #include <sys/time.h> 56 #include <sys/reboot.h> 57 58 #define _SPARC_BUS_DMA_PRIVATE 59 #include <machine/bus.h> 60 #include <machine/autoconf.h> 61 #include <machine/psl.h> 62 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcireg.h> 65 66 #include <sparc64/dev/iommureg.h> 67 #include <sparc64/dev/iommuvar.h> 68 #include <sparc64/dev/psychoreg.h> 69 #include <sparc64/dev/psychovar.h> 70 #include <sparc64/sparc64/cache.h> 71 72 #include "ioconf.h" 73 74 static pci_chipset_tag_t psycho_alloc_chipset __P((struct psycho_pbm *, int, 75 pci_chipset_tag_t)); 76 static void psycho_get_bus_range __P((int, int *)); 77 static void psycho_get_ranges __P((int, struct psycho_ranges **, int *)); 78 static void psycho_set_intr __P((struct psycho_softc *, int, void *, 79 u_int64_t *, u_int64_t *)); 80 81 /* Interrupt handlers */ 82 static int psycho_ue __P((void *)); 83 static int psycho_ce __P((void *)); 84 static int psycho_bus_a __P((void *)); 85 static int psycho_bus_b __P((void *)); 86 static int psycho_powerfail __P((void *)); 87 static int psycho_wakeup __P((void *)); 88 89 90 /* IOMMU support */ 91 static void psycho_iommu_init __P((struct psycho_softc *, int)); 92 93 /* 94 * bus space and bus dma support for UltraSPARC `psycho'. note that most 95 * of the bus dma support is provided by the iommu dvma controller. 96 */ 97 static paddr_t psycho_bus_mmap __P((bus_space_tag_t, bus_addr_t, off_t, 98 int, int)); 99 static int _psycho_bus_map __P((bus_space_tag_t, bus_addr_t, bus_size_t, int, 100 vaddr_t, bus_space_handle_t *)); 101 static void *psycho_intr_establish __P((bus_space_tag_t, int, int, int, 102 int (*) __P((void *)), void *)); 103 104 static int psycho_dmamap_load __P((bus_dma_tag_t, bus_dmamap_t, void *, 105 bus_size_t, struct proc *, int)); 106 static void psycho_dmamap_unload __P((bus_dma_tag_t, bus_dmamap_t)); 107 static int psycho_dmamap_load_raw __P((bus_dma_tag_t, bus_dmamap_t, 108 bus_dma_segment_t *, int, bus_size_t, int)); 109 static void psycho_dmamap_sync __P((bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 110 bus_size_t, int)); 111 int psycho_dmamem_alloc __P((bus_dma_tag_t, bus_size_t, bus_size_t, bus_size_t, 112 bus_dma_segment_t *, int, int *, int)); 113 void psycho_dmamem_free __P((bus_dma_tag_t, bus_dma_segment_t *, int)); 114 int psycho_dmamem_map __P((bus_dma_tag_t, bus_dma_segment_t *, int, size_t, 115 caddr_t *, int)); 116 void psycho_dmamem_unmap __P((bus_dma_tag_t, caddr_t, size_t)); 117 118 /* base pci_chipset */ 119 extern struct sparc_pci_chipset _sparc_pci_chipset; 120 121 /* 122 * autoconfiguration 123 */ 124 static int psycho_match __P((struct device *, struct cfdata *, void *)); 125 static void psycho_attach __P((struct device *, struct device *, void *)); 126 static int psycho_print __P((void *aux, const char *p)); 127 128 CFATTACH_DECL(psycho, sizeof(struct psycho_softc), 129 psycho_match, psycho_attach, NULL, NULL); 130 131 /* 132 * "sabre" is the UltraSPARC IIi onboard UPA to PCI bridge. It manages a 133 * single PCI bus and does not have a streaming buffer. It often has an APB 134 * (advanced PCI bridge) connected to it, which was designed specifically for 135 * the IIi. The APB let's the IIi handle two independednt PCI buses, and 136 * appears as two "simba"'s underneath the sabre. 137 * 138 * "psycho" and "psycho+" is a dual UPA to PCI bridge. It sits on the UPA bus 139 * and manages two PCI buses. "psycho" has two 64-bit 33MHz buses, while 140 * "psycho+" controls both a 64-bit 33Mhz and a 64-bit 66Mhz PCI bus. You 141 * will usually find a "psycho+" since I don't think the original "psycho" 142 * ever shipped, and if it did it would be in the U30. 143 * 144 * Each "psycho" PCI bus appears as a separate OFW node, but since they are 145 * both part of the same IC, they only have a single register space. As such, 146 * they need to be configured together, even though the autoconfiguration will 147 * attach them separately. 148 * 149 * On UltraIIi machines, "sabre" itself usually takes pci0, with "simba" often 150 * as pci1 and pci2, although they have been implemented with other PCI bus 151 * numbers on some machines. 152 * 153 * On UltraII machines, there can be any number of "psycho+" ICs, each 154 * providing two PCI buses. 155 * 156 * 157 * XXXX The psycho/sabre node has an `interrupts' attribute. They contain 158 * the values of the following interrupts in this order: 159 * 160 * PCI Bus Error (30) 161 * DMA UE (2e) 162 * DMA CE (2f) 163 * Power Fail (25) 164 * 165 * We really should attach handlers for each. 166 * 167 */ 168 169 #define ROM_PCI_NAME "pci" 170 171 struct psycho_names { 172 char *p_name; 173 int p_type; 174 } psycho_names[] = { 175 { "SUNW,psycho", PSYCHO_MODE_PSYCHO }, 176 { "pci108e,8000", PSYCHO_MODE_PSYCHO }, 177 { "SUNW,sabre", PSYCHO_MODE_SABRE }, 178 { "pci108e,a000", PSYCHO_MODE_SABRE }, 179 { "pci108e,a001", PSYCHO_MODE_SABRE }, 180 { NULL, 0 } 181 }; 182 183 static int 184 psycho_match(parent, match, aux) 185 struct device *parent; 186 struct cfdata *match; 187 void *aux; 188 { 189 struct mainbus_attach_args *ma = aux; 190 char *model = PROM_getpropstring(ma->ma_node, "model"); 191 int i; 192 193 /* match on a name of "pci" and a sabre or a psycho */ 194 if (strcmp(ma->ma_name, ROM_PCI_NAME) == 0) { 195 for (i=0; psycho_names[i].p_name; i++) 196 if (strcmp(model, psycho_names[i].p_name) == 0) 197 return (1); 198 199 model = PROM_getpropstring(ma->ma_node, "compatible"); 200 for (i=0; psycho_names[i].p_name; i++) 201 if (strcmp(model, psycho_names[i].p_name) == 0) 202 return (1); 203 } 204 return (0); 205 } 206 207 /* 208 * SUNW,psycho initialisation .. 209 * - find the per-psycho registers 210 * - figure out the IGN. 211 * - find our partner psycho 212 * - configure ourselves 213 * - bus range, bus, 214 * - get interrupt-map and interrupt-map-mask 215 * - setup the chipsets. 216 * - if we're the first of the pair, initialise the IOMMU, otherwise 217 * just copy it's tags and addresses. 218 */ 219 static void 220 psycho_attach(parent, self, aux) 221 struct device *parent, *self; 222 void *aux; 223 { 224 struct psycho_softc *sc = (struct psycho_softc *)self; 225 struct psycho_softc *osc = NULL; 226 struct psycho_pbm *pp; 227 struct pcibus_attach_args pba; 228 struct mainbus_attach_args *ma = aux; 229 bus_space_handle_t bh; 230 u_int64_t csr; 231 int psycho_br[2], n, i; 232 bus_space_handle_t pci_ctl; 233 char *model = PROM_getpropstring(ma->ma_node, "model"); 234 235 printf("\n"); 236 237 sc->sc_node = ma->ma_node; 238 sc->sc_bustag = ma->ma_bustag; 239 sc->sc_dmatag = ma->ma_dmatag; 240 241 /* 242 * Identify the device. 243 */ 244 for (i=0; psycho_names[i].p_name; i++) 245 if (strcmp(model, psycho_names[i].p_name) == 0) { 246 sc->sc_mode = psycho_names[i].p_type; 247 goto found; 248 } 249 250 model = PROM_getpropstring(ma->ma_node, "compatible"); 251 for (i=0; psycho_names[i].p_name; i++) 252 if (strcmp(model, psycho_names[i].p_name) == 0) { 253 sc->sc_mode = psycho_names[i].p_type; 254 goto found; 255 } 256 257 panic("unknown psycho model %s", model); 258 found: 259 260 /* 261 * The psycho gets three register banks: 262 * (0) per-PBM configuration and status registers 263 * (1) per-PBM PCI configuration space, containing only the 264 * PBM 256-byte PCI header 265 * (2) the shared psycho configuration registers (struct psychoreg) 266 */ 267 268 /* Register layouts are different. stuupid. */ 269 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 270 sc->sc_basepaddr = (paddr_t)ma->ma_reg[2].ur_paddr; 271 272 if (ma->ma_naddress > 2) { 273 sparc_promaddr_to_handle(sc->sc_bustag, 274 ma->ma_address[2], &sc->sc_bh); 275 sparc_promaddr_to_handle(sc->sc_bustag, 276 ma->ma_address[0], &pci_ctl); 277 278 sc->sc_regs = (struct psychoreg *) 279 bus_space_vaddr(sc->sc_bustag, sc->sc_bh); 280 } else if (ma->ma_nreg > 2) { 281 282 /* We need to map this in ourselves. */ 283 if (bus_space_map(sc->sc_bustag, 284 ma->ma_reg[2].ur_paddr, 285 ma->ma_reg[2].ur_len, BUS_SPACE_MAP_LINEAR, 286 &sc->sc_bh)) 287 panic("psycho_attach: cannot map regs"); 288 sc->sc_regs = (struct psychoreg *) 289 bus_space_vaddr(sc->sc_bustag, sc->sc_bh); 290 291 if (bus_space_map(sc->sc_bustag, 292 ma->ma_reg[0].ur_paddr, 293 ma->ma_reg[0].ur_len, BUS_SPACE_MAP_LINEAR, 294 &pci_ctl)) 295 panic("psycho_attach: cannot map ctl"); 296 } else 297 panic("psycho_attach: %d not enough registers", 298 ma->ma_nreg); 299 } else { 300 sc->sc_basepaddr = (paddr_t)ma->ma_reg[0].ur_paddr; 301 302 if (ma->ma_naddress) { 303 sparc_promaddr_to_handle(sc->sc_bustag, 304 ma->ma_address[0], &sc->sc_bh); 305 sc->sc_regs = (struct psychoreg *) 306 bus_space_vaddr(sc->sc_bustag, sc->sc_bh); 307 bus_space_subregion(sc->sc_bustag, sc->sc_bh, 308 offsetof(struct psychoreg, psy_pcictl), 309 sizeof(struct pci_ctl), &pci_ctl); 310 } else if (ma->ma_nreg) { 311 312 /* We need to map this in ourselves. */ 313 if (bus_space_map(sc->sc_bustag, 314 ma->ma_reg[0].ur_paddr, 315 ma->ma_reg[0].ur_len, BUS_SPACE_MAP_LINEAR, 316 &sc->sc_bh)) 317 panic("psycho_attach: cannot map regs"); 318 sc->sc_regs = (struct psychoreg *) 319 bus_space_vaddr(sc->sc_bustag, sc->sc_bh); 320 321 bus_space_subregion(sc->sc_bustag, sc->sc_bh, 322 offsetof(struct psychoreg, psy_pcictl), 323 sizeof(struct pci_ctl), &pci_ctl); 324 } else 325 panic("psycho_attach: %d not enough registers", 326 ma->ma_nreg); 327 } 328 329 330 csr = bus_space_read_8(sc->sc_bustag, sc->sc_bh, 331 offsetof(struct psychoreg, psy_csr)); 332 sc->sc_ign = 0x7c0; /* APB IGN is always 0x7c */ 333 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) 334 sc->sc_ign = PSYCHO_GCSR_IGN(csr) << 6; 335 336 printf("%s: impl %d, version %d: ign %x ", 337 model, PSYCHO_GCSR_IMPL(csr), PSYCHO_GCSR_VERS(csr), 338 sc->sc_ign); 339 /* 340 * Match other psycho's that are already configured against 341 * the base physical address. This will be the same for a 342 * pair of devices that share register space. 343 */ 344 for (n = 0; n < psycho_cd.cd_ndevs; n++) { 345 346 struct psycho_softc *asc = 347 (struct psycho_softc *)psycho_cd.cd_devs[n]; 348 349 if (asc == NULL || asc == sc) 350 /* This entry is not there or it is me */ 351 continue; 352 353 if (asc->sc_basepaddr != sc->sc_basepaddr) 354 /* This is an unrelated psycho */ 355 continue; 356 357 /* Found partner */ 358 osc = asc; 359 break; 360 } 361 362 363 /* Oh, dear. OK, lets get started */ 364 365 /* 366 * Setup the PCI control register 367 */ 368 csr = bus_space_read_8(sc->sc_bustag, pci_ctl, 369 offsetof(struct pci_ctl, pci_csr)); 370 csr |= PCICTL_MRLM | 371 PCICTL_ARB_PARK | 372 PCICTL_ERRINTEN | 373 PCICTL_4ENABLE; 374 csr &= ~(PCICTL_SERR | 375 PCICTL_CPU_PRIO | 376 PCICTL_ARB_PRIO | 377 PCICTL_RTRYWAIT); 378 bus_space_write_8(sc->sc_bustag, pci_ctl, 379 offsetof(struct pci_ctl, pci_csr), csr); 380 381 382 /* 383 * Allocate our psycho_pbm 384 */ 385 pp = sc->sc_psycho_this = malloc(sizeof *pp, M_DEVBUF, M_NOWAIT); 386 if (pp == NULL) 387 panic("could not allocate psycho pbm"); 388 389 memset(pp, 0, sizeof *pp); 390 391 pp->pp_sc = sc; 392 393 /* grab the psycho ranges */ 394 psycho_get_ranges(sc->sc_node, &pp->pp_range, &pp->pp_nrange); 395 396 /* get the bus-range for the psycho */ 397 psycho_get_bus_range(sc->sc_node, psycho_br); 398 399 pba.pba_bus = psycho_br[0]; 400 pba.pba_bridgetag = NULL; 401 402 printf("bus range %u to %u", psycho_br[0], psycho_br[1]); 403 printf("; PCI bus %d", psycho_br[0]); 404 405 pp->pp_pcictl = pci_ctl; 406 407 /* allocate our tags */ 408 pp->pp_memt = psycho_alloc_mem_tag(pp); 409 pp->pp_iot = psycho_alloc_io_tag(pp); 410 pp->pp_dmat = psycho_alloc_dma_tag(pp); 411 pp->pp_flags = (pp->pp_memt ? PCI_FLAGS_MEM_ENABLED : 0) | 412 (pp->pp_iot ? PCI_FLAGS_IO_ENABLED : 0); 413 414 /* allocate a chipset for this */ 415 pp->pp_pc = psycho_alloc_chipset(pp, sc->sc_node, &_sparc_pci_chipset); 416 417 /* setup the rest of the psycho pbm */ 418 pba.pba_pc = psycho_alloc_chipset(pp, sc->sc_node, pp->pp_pc); 419 420 printf("\n"); 421 422 /* 423 * And finally, if we're a sabre or the first of a pair of psycho's to 424 * arrive here, start up the IOMMU and get a config space tag. 425 */ 426 if (osc == NULL) { 427 uint64_t timeo; 428 429 /* 430 * Establish handlers for interesting interrupts.... 431 * 432 * XXX We need to remember these and remove this to support 433 * hotplug on the UPA/FHC bus. 434 * 435 * XXX Not all controllers have these, but installing them 436 * is better than trying to sort through this mess. 437 */ 438 psycho_set_intr(sc, 15, psycho_ue, 439 &sc->sc_regs->ue_int_map, 440 &sc->sc_regs->ue_clr_int); 441 psycho_set_intr(sc, 1, psycho_ce, 442 &sc->sc_regs->ce_int_map, 443 &sc->sc_regs->ce_clr_int); 444 psycho_set_intr(sc, 15, psycho_bus_a, 445 &sc->sc_regs->pciaerr_int_map, 446 &sc->sc_regs->pciaerr_clr_int); 447 psycho_set_intr(sc, 15, psycho_bus_b, 448 &sc->sc_regs->pciberr_int_map, 449 &sc->sc_regs->pciberr_clr_int); 450 psycho_set_intr(sc, 15, psycho_powerfail, 451 &sc->sc_regs->power_int_map, 452 &sc->sc_regs->power_clr_int); 453 psycho_set_intr(sc, 1, psycho_wakeup, 454 &sc->sc_regs->pwrmgt_int_map, 455 &sc->sc_regs->pwrmgt_clr_int); 456 457 458 /* 459 * Apparently a number of machines with psycho and psycho+ 460 * controllers have interrupt latency issues. We'll try 461 * setting the interrupt retry timeout to 0xff which gives us 462 * a retry of 3-6 usec (which is what sysio is set to) for the 463 * moment, which seems to help alleviate this problem. 464 */ 465 timeo = sc->sc_regs->intr_retry_timer; 466 if (timeo > 0xfff) { 467 #ifdef DEBUG 468 printf("decreasing interrupt retry timeout " 469 "from %lx to 0xff\n", (long)timeo); 470 #endif 471 sc->sc_regs->intr_retry_timer = 0xff; 472 } 473 474 /* 475 * Setup IOMMU and PCI configuration if we're the first 476 * of a pair of psycho's to arrive here. 477 * 478 * We should calculate a TSB size based on amount of RAM 479 * and number of bus controllers and number an type of 480 * child devices. 481 * 482 * For the moment, 32KB should be more than enough. 483 */ 484 sc->sc_is = malloc(sizeof(struct iommu_state), 485 M_DEVBUF, M_NOWAIT); 486 if (sc->sc_is == NULL) 487 panic("psycho_attach: malloc iommu_state"); 488 489 /* Point the strbuf_ctl at the iommu_state */ 490 pp->pp_sb.sb_is = sc->sc_is; 491 492 sc->sc_is->is_sb[0] = sc->sc_is->is_sb[1] = NULL; 493 if (PROM_getproplen(sc->sc_node, "no-streaming-cache") < 0) { 494 struct strbuf_ctl *sb = &pp->pp_sb; 495 vaddr_t va = (vaddr_t)&pp->pp_flush[0x40]; 496 497 /* 498 * Initialize the strbuf_ctl. 499 * 500 * The flush sync buffer must be 64-byte aligned. 501 */ 502 sb->sb_flush = (void *)(va & ~0x3f); 503 504 bus_space_subregion(sc->sc_bustag, pci_ctl, 505 offsetof(struct pci_ctl, pci_strbuf), 506 sizeof (struct iommu_strbuf), &sb->sb_sb); 507 508 /* Point our iommu at the strbuf_ctl */ 509 sc->sc_is->is_sb[0] = sb; 510 } 511 512 psycho_iommu_init(sc, 2); 513 514 sc->sc_configtag = psycho_alloc_config_tag(sc->sc_psycho_this); 515 516 /* 517 * XXX This is a really ugly hack because PCI config space 518 * is explicitly handled with unmapped accesses. 519 */ 520 i = sc->sc_bustag->type; 521 sc->sc_bustag->type = PCI_CONFIG_BUS_SPACE; 522 if (bus_space_map(sc->sc_bustag, sc->sc_basepaddr + 0x01000000, 523 0x0100000, 0, &bh)) 524 panic("could not map psycho PCI configuration space"); 525 sc->sc_bustag->type = i; 526 sc->sc_configaddr = bh; 527 } else { 528 /* Just copy IOMMU state, config tag and address */ 529 sc->sc_is = osc->sc_is; 530 sc->sc_configtag = osc->sc_configtag; 531 sc->sc_configaddr = osc->sc_configaddr; 532 533 /* Point the strbuf_ctl at the iommu_state */ 534 pp->pp_sb.sb_is = sc->sc_is; 535 536 if (PROM_getproplen(sc->sc_node, "no-streaming-cache") < 0) { 537 struct strbuf_ctl *sb = &pp->pp_sb; 538 vaddr_t va = (vaddr_t)&pp->pp_flush[0x40]; 539 540 /* 541 * Initialize the strbuf_ctl. 542 * 543 * The flush sync buffer must be 64-byte aligned. 544 */ 545 sb->sb_flush = (void *)(va & ~0x3f); 546 547 bus_space_subregion(sc->sc_bustag, pci_ctl, 548 offsetof(struct pci_ctl, pci_strbuf), 549 sizeof (struct iommu_strbuf), &sb->sb_sb); 550 551 /* Point our iommu at the strbuf_ctl */ 552 sc->sc_is->is_sb[1] = sb; 553 } 554 iommu_reset(sc->sc_is); 555 } 556 557 /* 558 * attach the pci.. note we pass PCI A tags, etc., for the sabre here. 559 */ 560 pba.pba_busname = "pci"; 561 pba.pba_flags = sc->sc_psycho_this->pp_flags; 562 pba.pba_dmat = sc->sc_psycho_this->pp_dmat; 563 pba.pba_iot = sc->sc_psycho_this->pp_iot; 564 pba.pba_memt = sc->sc_psycho_this->pp_memt; 565 566 config_found(self, &pba, psycho_print); 567 } 568 569 static int 570 psycho_print(aux, p) 571 void *aux; 572 const char *p; 573 { 574 575 if (p == NULL) 576 return (UNCONF); 577 return (QUIET); 578 } 579 580 static void 581 psycho_set_intr(sc, ipl, handler, mapper, clearer) 582 struct psycho_softc *sc; 583 int ipl; 584 void *handler; 585 u_int64_t *mapper; 586 u_int64_t *clearer; 587 { 588 struct intrhand *ih; 589 590 ih = (struct intrhand *)malloc(sizeof(struct intrhand), 591 M_DEVBUF, M_NOWAIT); 592 ih->ih_arg = sc; 593 ih->ih_map = mapper; 594 ih->ih_clr = clearer; 595 ih->ih_fun = handler; 596 ih->ih_pil = (1<<ipl); 597 ih->ih_number = INTVEC(*(ih->ih_map)); 598 intr_establish(ipl, ih); 599 *(ih->ih_map) |= INTMAP_V; 600 } 601 602 /* 603 * PCI bus support 604 */ 605 606 /* 607 * allocate a PCI chipset tag and set it's cookie. 608 */ 609 static pci_chipset_tag_t 610 psycho_alloc_chipset(pp, node, pc) 611 struct psycho_pbm *pp; 612 int node; 613 pci_chipset_tag_t pc; 614 { 615 pci_chipset_tag_t npc; 616 617 npc = malloc(sizeof *npc, M_DEVBUF, M_NOWAIT); 618 if (npc == NULL) 619 panic("could not allocate pci_chipset_tag_t"); 620 memcpy(npc, pc, sizeof *pc); 621 npc->cookie = pp; 622 npc->rootnode = node; 623 624 return (npc); 625 } 626 627 /* 628 * grovel the OBP for various psycho properties 629 */ 630 static void 631 psycho_get_bus_range(node, brp) 632 int node; 633 int *brp; 634 { 635 int n; 636 637 if (PROM_getprop(node, "bus-range", sizeof(*brp), &n, (void **)&brp)) 638 panic("could not get psycho bus-range"); 639 if (n != 2) 640 panic("broken psycho bus-range"); 641 DPRINTF(PDB_PROM, ("psycho debug: got `bus-range' for node %08x: %u - %u\n", node, brp[0], brp[1])); 642 } 643 644 static void 645 psycho_get_ranges(node, rp, np) 646 int node; 647 struct psycho_ranges **rp; 648 int *np; 649 { 650 651 if (PROM_getprop(node, "ranges", sizeof(**rp), np, (void **)rp)) 652 panic("could not get psycho ranges"); 653 DPRINTF(PDB_PROM, ("psycho debug: got `ranges' for node %08x: %d entries\n", node, *np)); 654 } 655 656 /* 657 * Interrupt handlers. 658 */ 659 660 static int 661 psycho_ue(arg) 662 void *arg; 663 { 664 struct psycho_softc *sc = (struct psycho_softc *)arg; 665 struct psychoreg *regs = sc->sc_regs; 666 long long afsr = regs->psy_ue_afsr; 667 long long afar = regs->psy_ue_afar; 668 long size = NBPG<<(sc->sc_is->is_tsbsize); 669 struct iommu_state *is = sc->sc_is; 670 char bits[128]; 671 672 /* 673 * It's uncorrectable. Dump the regs and panic. 674 */ 675 printf("%s: uncorrectable DMA error AFAR %llx pa %llx AFSR %llx:\n%s\n", 676 sc->sc_dev.dv_xname, afar, 677 (long long)iommu_extract(is, (vaddr_t)afar), afsr, 678 bitmask_snprintf(afsr, PSYCHO_UE_AFSR_BITS, 679 bits, sizeof(bits))); 680 681 /* Sometimes the AFAR points to an IOTSB entry */ 682 if (afar >= is->is_ptsb && afar < is->is_ptsb + size) { 683 printf("IOVA %llx IOTTE %llx\n", 684 (long long)((afar - is->is_ptsb) * NBPG + is->is_dvmabase), 685 (long long)ldxa(afar, ASI_PHYS_CACHED)); 686 } 687 #ifdef DDB 688 Debugger(); 689 #endif 690 regs->psy_ue_afar = 0; 691 regs->psy_ue_afsr = 0; 692 return (1); 693 } 694 static int 695 psycho_ce(arg) 696 void *arg; 697 { 698 struct psycho_softc *sc = (struct psycho_softc *)arg; 699 struct psychoreg *regs = sc->sc_regs; 700 701 /* 702 * It's correctable. Dump the regs and continue. 703 */ 704 705 printf("%s: correctable DMA error AFAR %llx AFSR %llx\n", 706 sc->sc_dev.dv_xname, 707 (long long)regs->psy_ce_afar, (long long)regs->psy_ce_afsr); 708 return (1); 709 } 710 static int 711 psycho_bus_a(arg) 712 void *arg; 713 { 714 struct psycho_softc *sc = (struct psycho_softc *)arg; 715 struct psychoreg *regs = sc->sc_regs; 716 717 /* 718 * It's uncorrectable. Dump the regs and panic. 719 */ 720 721 panic("%s: PCI bus A error AFAR %llx AFSR %llx", 722 sc->sc_dev.dv_xname, 723 (long long)regs->psy_pcictl[0].pci_afar, 724 (long long)regs->psy_pcictl[0].pci_afsr); 725 return (1); 726 } 727 static int 728 psycho_bus_b(arg) 729 void *arg; 730 { 731 struct psycho_softc *sc = (struct psycho_softc *)arg; 732 struct psychoreg *regs = sc->sc_regs; 733 734 /* 735 * It's uncorrectable. Dump the regs and panic. 736 */ 737 738 panic("%s: PCI bus B error AFAR %llx AFSR %llx", 739 sc->sc_dev.dv_xname, 740 (long long)regs->psy_pcictl[0].pci_afar, 741 (long long)regs->psy_pcictl[0].pci_afsr); 742 return (1); 743 } 744 static int 745 psycho_powerfail(arg) 746 void *arg; 747 { 748 749 /* 750 * We lost power. Try to shut down NOW. 751 */ 752 printf("Power Failure Detected: Shutting down NOW.\n"); 753 cpu_reboot(RB_POWERDOWN|RB_HALT, NULL); 754 return (1); 755 } 756 static 757 int psycho_wakeup(arg) 758 void *arg; 759 { 760 struct psycho_softc *sc = (struct psycho_softc *)arg; 761 762 /* 763 * Gee, we don't really have a framework to deal with this 764 * properly. 765 */ 766 printf("%s: power management wakeup\n", sc->sc_dev.dv_xname); 767 return (1); 768 } 769 770 771 772 /* 773 * initialise the IOMMU.. 774 */ 775 void 776 psycho_iommu_init(sc, tsbsize) 777 struct psycho_softc *sc; 778 int tsbsize; 779 { 780 char *name; 781 struct iommu_state *is = sc->sc_is; 782 u_int32_t iobase = -1; 783 int *vdma = NULL; 784 int nitem; 785 786 /* punch in our copies */ 787 is->is_bustag = sc->sc_bustag; 788 bus_space_subregion(sc->sc_bustag, sc->sc_bh, 789 offsetof(struct psychoreg, psy_iommu), 790 sizeof (struct iommureg), 791 &is->is_iommu); 792 793 /* 794 * Separate the men from the boys. Get the `virtual-dma' 795 * property for sabre and use that to make sure the damn 796 * iommu works. 797 * 798 * We could query the `#virtual-dma-size-cells' and 799 * `#virtual-dma-addr-cells' and DTRT, but I'm lazy. 800 */ 801 if (!PROM_getprop(sc->sc_node, "virtual-dma", sizeof(vdma), &nitem, 802 (void **)&vdma)) { 803 /* Damn. Gotta use these values. */ 804 iobase = vdma[0]; 805 #define TSBCASE(x) case 1<<((x)+23): tsbsize = (x); break 806 switch (vdma[1]) { 807 TSBCASE(1); TSBCASE(2); TSBCASE(3); 808 TSBCASE(4); TSBCASE(5); TSBCASE(6); 809 default: 810 printf("bogus tsb size %x, using 7\n", vdma[1]); 811 TSBCASE(7); 812 } 813 #undef TSBCASE 814 } 815 816 /* give us a nice name.. */ 817 name = (char *)malloc(32, M_DEVBUF, M_NOWAIT); 818 if (name == 0) 819 panic("couldn't malloc iommu name"); 820 snprintf(name, 32, "%s dvma", sc->sc_dev.dv_xname); 821 822 iommu_init(name, is, tsbsize, iobase); 823 } 824 825 /* 826 * below here is bus space and bus dma support 827 */ 828 bus_space_tag_t 829 psycho_alloc_bus_tag(pp, type) 830 struct psycho_pbm *pp; 831 int type; 832 { 833 struct psycho_softc *sc = pp->pp_sc; 834 bus_space_tag_t bt; 835 836 bt = (bus_space_tag_t) 837 malloc(sizeof(struct sparc_bus_space_tag), M_DEVBUF, M_NOWAIT); 838 if (bt == NULL) 839 panic("could not allocate psycho bus tag"); 840 841 bzero(bt, sizeof *bt); 842 bt->cookie = pp; 843 bt->parent = sc->sc_bustag; 844 bt->type = type; 845 bt->sparc_bus_map = _psycho_bus_map; 846 bt->sparc_bus_mmap = psycho_bus_mmap; 847 bt->sparc_intr_establish = psycho_intr_establish; 848 return (bt); 849 } 850 851 bus_dma_tag_t 852 psycho_alloc_dma_tag(pp) 853 struct psycho_pbm *pp; 854 { 855 struct psycho_softc *sc = pp->pp_sc; 856 bus_dma_tag_t dt, pdt = sc->sc_dmatag; 857 858 dt = (bus_dma_tag_t) 859 malloc(sizeof(struct sparc_bus_dma_tag), M_DEVBUF, M_NOWAIT); 860 if (dt == NULL) 861 panic("could not allocate psycho dma tag"); 862 863 bzero(dt, sizeof *dt); 864 dt->_cookie = pp; 865 dt->_parent = pdt; 866 #define PCOPY(x) dt->x = pdt->x 867 PCOPY(_dmamap_create); 868 PCOPY(_dmamap_destroy); 869 dt->_dmamap_load = psycho_dmamap_load; 870 PCOPY(_dmamap_load_mbuf); 871 PCOPY(_dmamap_load_uio); 872 dt->_dmamap_load_raw = psycho_dmamap_load_raw; 873 dt->_dmamap_unload = psycho_dmamap_unload; 874 dt->_dmamap_sync = psycho_dmamap_sync; 875 dt->_dmamem_alloc = psycho_dmamem_alloc; 876 dt->_dmamem_free = psycho_dmamem_free; 877 dt->_dmamem_map = psycho_dmamem_map; 878 dt->_dmamem_unmap = psycho_dmamem_unmap; 879 PCOPY(_dmamem_mmap); 880 #undef PCOPY 881 return (dt); 882 } 883 884 /* 885 * bus space support. <sparc64/dev/psychoreg.h> has a discussion about 886 * PCI physical addresses. 887 */ 888 889 static int get_childspace __P((int)); 890 891 static int 892 get_childspace(type) 893 int type; 894 { 895 int ss; 896 897 switch (type) { 898 case PCI_CONFIG_BUS_SPACE: 899 ss = 0x00; 900 break; 901 case PCI_IO_BUS_SPACE: 902 ss = 0x01; 903 break; 904 case PCI_MEMORY_BUS_SPACE: 905 ss = 0x02; 906 break; 907 #if 0 908 /* we don't do 64 bit memory space */ 909 case PCI_MEMORY64_BUS_SPACE: 910 ss = 0x03; 911 break; 912 #endif 913 default: 914 panic("get_childspace: unknown bus type"); 915 } 916 917 return (ss); 918 } 919 920 static int 921 _psycho_bus_map(t, offset, size, flags, unused, hp) 922 bus_space_tag_t t; 923 bus_addr_t offset; 924 bus_size_t size; 925 int flags; 926 vaddr_t unused; 927 bus_space_handle_t *hp; 928 { 929 struct psycho_pbm *pp = t->cookie; 930 struct psycho_softc *sc = pp->pp_sc; 931 int i, ss; 932 933 DPRINTF(PDB_BUSMAP, 934 ("_psycho_bus_map: type %d off %qx sz %qx flags %d", 935 t->type, (unsigned long long)offset, 936 (unsigned long long)size, flags)); 937 938 ss = get_childspace(t->type); 939 DPRINTF(PDB_BUSMAP, (" cspace %d", ss)); 940 941 for (i = 0; i < pp->pp_nrange; i++) { 942 bus_addr_t paddr; 943 944 if (((pp->pp_range[i].cspace >> 24) & 0x03) != ss) 945 continue; 946 947 paddr = pp->pp_range[i].phys_lo + offset; 948 paddr |= ((bus_addr_t)pp->pp_range[i].phys_hi<<32); 949 DPRINTF(PDB_BUSMAP, ("\n_psycho_bus_map: mapping paddr space %lx offset %lx paddr %qx\n", 950 (long)ss, (long)offset, 951 (unsigned long long)paddr)); 952 return ((*sc->sc_bustag->sparc_bus_map)(t, paddr, size, 953 flags, 0, hp)); 954 } 955 DPRINTF(PDB_BUSMAP, (" FAILED\n")); 956 return (EINVAL); 957 } 958 959 static paddr_t 960 psycho_bus_mmap(t, paddr, off, prot, flags) 961 bus_space_tag_t t; 962 bus_addr_t paddr; 963 off_t off; 964 int prot; 965 int flags; 966 { 967 bus_addr_t offset = paddr; 968 struct psycho_pbm *pp = t->cookie; 969 struct psycho_softc *sc = pp->pp_sc; 970 int i, ss; 971 972 ss = get_childspace(t->type); 973 974 DPRINTF(PDB_BUSMAP, ("_psycho_bus_mmap: prot %x flags %d pa %qx\n", 975 prot, flags, (unsigned long long)paddr)); 976 977 for (i = 0; i < pp->pp_nrange; i++) { 978 bus_addr_t paddr; 979 980 if (((pp->pp_range[i].cspace >> 24) & 0x03) != ss) 981 continue; 982 983 paddr = pp->pp_range[i].phys_lo + offset; 984 paddr |= ((bus_addr_t)pp->pp_range[i].phys_hi<<32); 985 DPRINTF(PDB_BUSMAP, ("\n_psycho_bus_mmap: mapping paddr " 986 "space %lx offset %lx paddr %qx\n", 987 (long)ss, (long)offset, 988 (unsigned long long)paddr)); 989 return (bus_space_mmap(sc->sc_bustag, paddr, off, 990 prot, flags)); 991 } 992 993 return (-1); 994 } 995 996 997 /* 998 * install an interrupt handler for a PCI device 999 */ 1000 void * 1001 psycho_intr_establish(t, ihandle, level, flags, handler, arg) 1002 bus_space_tag_t t; 1003 int ihandle; 1004 int level; 1005 int flags; 1006 int (*handler) __P((void *)); 1007 void *arg; 1008 { 1009 struct psycho_pbm *pp = t->cookie; 1010 struct psycho_softc *sc = pp->pp_sc; 1011 struct intrhand *ih; 1012 volatile u_int64_t *intrmapptr = NULL, *intrclrptr = NULL; 1013 int64_t intrmap = 0; 1014 int ino; 1015 long vec = INTVEC(ihandle); 1016 1017 ih = (struct intrhand *) 1018 malloc(sizeof(struct intrhand), M_DEVBUF, M_NOWAIT); 1019 if (ih == NULL) 1020 return (NULL); 1021 1022 /* 1023 * Hunt through all the interrupt mapping regs to look for our 1024 * interrupt vector. 1025 * 1026 * XXX We only compare INOs rather than IGNs since the firmware may 1027 * not provide the IGN and the IGN is constant for all device on that 1028 * PCI controller. This could cause problems for the FFB/external 1029 * interrupt which has a full vector that can be set arbitrarily. 1030 */ 1031 1032 1033 DPRINTF(PDB_INTR, ("\npsycho_intr_establish: ihandle %x vec %lx", ihandle, vec)); 1034 ino = INTINO(vec); 1035 DPRINTF(PDB_INTR, (" ino %x", ino)); 1036 1037 /* If the device didn't ask for an IPL, use the one encoded. */ 1038 if (level == IPL_NONE) level = INTLEV(vec); 1039 /* If it still has no level, print a warning and assign IPL 2 */ 1040 if (level == IPL_NONE) { 1041 printf("ERROR: no IPL, setting IPL 2.\n"); 1042 level = 2; 1043 } 1044 1045 if ((flags & BUS_INTR_ESTABLISH_SOFTINTR) == 0) { 1046 1047 DPRINTF(PDB_INTR, ("\npsycho: intr %lx: %p\nHunting for IRQ...\n", 1048 (long)ino, intrlev[ino])); 1049 1050 /* Hunt thru obio first */ 1051 for (intrmapptr = &sc->sc_regs->scsi_int_map, 1052 intrclrptr = &sc->sc_regs->scsi_clr_int; 1053 intrmapptr < &sc->sc_regs->ffb0_int_map; 1054 intrmapptr++, intrclrptr++) { 1055 if (INTINO(*intrmapptr) == ino) 1056 goto found; 1057 } 1058 1059 /* Now do PCI interrupts */ 1060 for (intrmapptr = &sc->sc_regs->pcia_slot0_int, 1061 intrclrptr = &sc->sc_regs->pcia0_clr_int[0]; 1062 intrmapptr <= &sc->sc_regs->pcib_slot3_int; 1063 intrmapptr++, intrclrptr += 4) { 1064 if (((*intrmapptr ^ vec) & 0x3c) == 0) { 1065 intrclrptr += vec & 0x3; 1066 goto found; 1067 } 1068 } 1069 1070 /* Finally check the two FFB slots */ 1071 intrclrptr = NULL; /* XXX? */ 1072 for (intrmapptr = &sc->sc_regs->ffb0_int_map; 1073 intrmapptr <= &sc->sc_regs->ffb1_int_map; 1074 intrmapptr++) { 1075 if (INTVEC(*intrmapptr) == ino) 1076 goto found; 1077 } 1078 1079 printf("Cannot find interrupt vector %lx\n", vec); 1080 return (NULL); 1081 1082 found: 1083 /* Register the map and clear intr registers */ 1084 ih->ih_map = intrmapptr; 1085 ih->ih_clr = intrclrptr; 1086 } 1087 #ifdef NOT_DEBUG 1088 if (psycho_debug & PDB_INTR) { 1089 long i; 1090 1091 for (i = 0; i < 500000000; i++) 1092 continue; 1093 } 1094 #endif 1095 1096 ih->ih_fun = handler; 1097 ih->ih_arg = arg; 1098 ih->ih_pil = level; 1099 ih->ih_number = ino | sc->sc_ign; 1100 1101 DPRINTF(PDB_INTR, ( 1102 "; installing handler %p arg %p with ino %u pil %u\n", 1103 handler, arg, (u_int)ino, (u_int)ih->ih_pil)); 1104 1105 intr_establish(ih->ih_pil, ih); 1106 1107 /* 1108 * Enable the interrupt now we have the handler installed. 1109 * Read the current value as we can't change it besides the 1110 * valid bit so so make sure only this bit is changed. 1111 * 1112 * XXXX --- we really should use bus_space for this. 1113 */ 1114 if (intrmapptr) { 1115 intrmap = *intrmapptr; 1116 DPRINTF(PDB_INTR, ("; read intrmap = %016qx", 1117 (unsigned long long)intrmap)); 1118 1119 /* Enable the interrupt */ 1120 intrmap |= INTMAP_V; 1121 DPRINTF(PDB_INTR, ("; addr of intrmapptr = %p", intrmapptr)); 1122 DPRINTF(PDB_INTR, ("; writing intrmap = %016qx\n", 1123 (unsigned long long)intrmap)); 1124 *intrmapptr = intrmap; 1125 DPRINTF(PDB_INTR, ("; reread intrmap = %016qx", 1126 (unsigned long long)(intrmap = *intrmapptr))); 1127 } 1128 return (ih); 1129 } 1130 1131 /* 1132 * hooks into the iommu dvma calls. 1133 */ 1134 int 1135 psycho_dmamap_load(t, map, buf, buflen, p, flags) 1136 bus_dma_tag_t t; 1137 bus_dmamap_t map; 1138 void *buf; 1139 bus_size_t buflen; 1140 struct proc *p; 1141 int flags; 1142 { 1143 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1144 1145 return (iommu_dvmamap_load(t, &pp->pp_sb, map, buf, buflen, p, flags)); 1146 } 1147 1148 void 1149 psycho_dmamap_unload(t, map) 1150 bus_dma_tag_t t; 1151 bus_dmamap_t map; 1152 { 1153 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1154 1155 iommu_dvmamap_unload(t, &pp->pp_sb, map); 1156 } 1157 1158 int 1159 psycho_dmamap_load_raw(t, map, segs, nsegs, size, flags) 1160 bus_dma_tag_t t; 1161 bus_dmamap_t map; 1162 bus_dma_segment_t *segs; 1163 int nsegs; 1164 bus_size_t size; 1165 int flags; 1166 { 1167 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1168 1169 return (iommu_dvmamap_load_raw(t, &pp->pp_sb, map, segs, nsegs, flags, size)); 1170 } 1171 1172 void 1173 psycho_dmamap_sync(t, map, offset, len, ops) 1174 bus_dma_tag_t t; 1175 bus_dmamap_t map; 1176 bus_addr_t offset; 1177 bus_size_t len; 1178 int ops; 1179 { 1180 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1181 1182 if (ops & (BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE)) { 1183 /* Flush the CPU then the IOMMU */ 1184 bus_dmamap_sync(t->_parent, map, offset, len, ops); 1185 iommu_dvmamap_sync(t, &pp->pp_sb, map, offset, len, ops); 1186 } 1187 if (ops & (BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE)) { 1188 /* Flush the IOMMU then the CPU */ 1189 iommu_dvmamap_sync(t, &pp->pp_sb, map, offset, len, ops); 1190 bus_dmamap_sync(t->_parent, map, offset, len, ops); 1191 } 1192 1193 } 1194 1195 int 1196 psycho_dmamem_alloc(t, size, alignment, boundary, segs, nsegs, rsegs, flags) 1197 bus_dma_tag_t t; 1198 bus_size_t size; 1199 bus_size_t alignment; 1200 bus_size_t boundary; 1201 bus_dma_segment_t *segs; 1202 int nsegs; 1203 int *rsegs; 1204 int flags; 1205 { 1206 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1207 1208 return (iommu_dvmamem_alloc(t, &pp->pp_sb, size, alignment, boundary, 1209 segs, nsegs, rsegs, flags)); 1210 } 1211 1212 void 1213 psycho_dmamem_free(t, segs, nsegs) 1214 bus_dma_tag_t t; 1215 bus_dma_segment_t *segs; 1216 int nsegs; 1217 { 1218 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1219 1220 iommu_dvmamem_free(t, &pp->pp_sb, segs, nsegs); 1221 } 1222 1223 int 1224 psycho_dmamem_map(t, segs, nsegs, size, kvap, flags) 1225 bus_dma_tag_t t; 1226 bus_dma_segment_t *segs; 1227 int nsegs; 1228 size_t size; 1229 caddr_t *kvap; 1230 int flags; 1231 { 1232 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1233 1234 return (iommu_dvmamem_map(t, &pp->pp_sb, segs, nsegs, size, kvap, flags)); 1235 } 1236 1237 void 1238 psycho_dmamem_unmap(t, kva, size) 1239 bus_dma_tag_t t; 1240 caddr_t kva; 1241 size_t size; 1242 { 1243 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1244 1245 iommu_dvmamem_unmap(t, &pp->pp_sb, kva, size); 1246 } 1247