1 /* $NetBSD: pte.h,v 1.10 2002/03/20 18:41:53 eeh Exp $ */ 2 3 /* 4 * Copyright (c) 1996-1999 Eduardo Horvath 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 12 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 13 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 14 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 15 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 16 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 17 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 18 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 19 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 20 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 21 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 22 * SUCH DAMAGE. 23 * 24 */ 25 26 #if defined(_KERNEL_OPT) 27 #include "opt_sparc_arch.h" 28 #endif 29 30 /* 31 * Address translation works as follows: 32 * 33 ** 34 * For sun4u: 35 * 36 * Take your pick; it's all S/W anyway. We'll start by emulating a sun4. 37 * Oh, here's the sun4u TTE for reference: 38 * 39 * struct sun4u_tte { 40 * u_int64 tag_g:1, (global flag) 41 * tag_ctxt:15, (context for mapping) 42 * tag_unassigned:6, 43 * tag_va:42; (virtual address bits<64:22>) 44 * u_int64 data_v:1, (valid bit) 45 * data_size:2, (page size [8K*8**<SIZE>]) 46 * data_nfo:1, (no-fault only) 47 * data_ie:1, (invert endianness [inefficient]) 48 * data_soft2:2, (reserved for S/W) 49 * data_pa:36, (physical address) 50 * data_soft:6, (reserved for S/W) 51 * data_lock:1, (lock into TLB) 52 * data_cacheable:2, (cacheability control) 53 * data_e:1, (explicit accesses only) 54 * data_priv:1, (privileged page) 55 * data_w:1, (writeable) 56 * data_g:1; (same as tag_g) 57 * }; 58 */ 59 60 /* virtual address to virtual page number */ 61 #define VA_SUN4_VPG(va) (((int)(va) >> 13) & 31) 62 #define VA_SUN4C_VPG(va) (((int)(va) >> 12) & 63) 63 #define VA_SUN4U_VPG(va) (((int)(va) >> 13) & 31) 64 65 /* virtual address to offset within page */ 66 #define VA_SUN4_OFF(va) (((int)(va)) & 0x1FFF) 67 #define VA_SUN4C_OFF(va) (((int)(va)) & 0xFFF) 68 #define VA_SUN4U_OFF(va) (((int)(va)) & 0x1FFF) 69 70 /* When we go to 64-bit VAs we need to handle the hole */ 71 #define VA_VPG(va) VA_SUN4U_VPG(va) 72 #define VA_OFF(va) VA_SUN4U_OFF(va) 73 74 #define PG_SHIFT4U 13 75 #define MMU_PAGE_ALIGN 8192 76 77 /* If you know where a tte is in the tsb, how do you find its va? */ 78 #define TSBVA(i) ((tsb[(i)].tag.f.tag_va<<22)|(((i)<<13)&0x3ff000)) 79 80 #ifndef _LOCORE 81 /* 82 * This is the spitfire TTE. 83 * 84 * We could use bitmasks and shifts to construct this if 85 * we had a 64-bit compiler w/64-bit longs. Otherwise it's 86 * a real pain to do this in C. 87 */ 88 #if 0 89 /* We don't use bitfeilds anyway. */ 90 struct sun4u_tag_fields { 91 u_int64_t tag_g:1, /* global flag */ 92 tag_ctxt:15, /* context for mapping */ 93 tag_unassigned:6, 94 tag_va:42; /* virtual address bits<64:22> */ 95 }; 96 union sun4u_tag { struct sun4u_tag_fields f; int64_t tag; }; 97 struct sun4u_data_fields { 98 u_int64_t data_v:1, /* valid bit */ 99 data_size:2, /* page size [8K*8**<SIZE>] */ 100 data_nfo:1, /* no-fault only */ 101 data_ie:1, /* invert endianness [inefficient] */ 102 data_soft2:2, /* reserved for S/W */ 103 data_pa:36, /* physical address */ 104 data_accessed:1,/* S/W accessed bit */ 105 data_modified:1,/* S/W modified bit */ 106 data_realw:1, /* S/W real writable bit (to manage modified) */ 107 data_tsblock:1, /* S/W TSB locked entry */ 108 data_exec:1, /* S/W Executable */ 109 data_onlyexec:1,/* S/W Executable only */ 110 data_lock:1, /* lock into TLB */ 111 data_cacheable:2, /* cacheability control */ 112 data_e:1, /* explicit accesses only */ 113 data_priv:1, /* privileged page */ 114 data_w:1, /* writeable */ 115 data_g:1; /* same as tag_g */ 116 }; 117 union sun4u_data { struct sun4u_data_fields f; int64_t data; }; 118 struct sun4u_tte { 119 union sun4u_tag tag; 120 union sun4u_data data; 121 }; 122 #else 123 struct sun4u_tte { 124 int64_t tag; 125 int64_t data; 126 }; 127 #endif 128 typedef struct sun4u_tte pte_t; 129 130 /* Assembly routine to flush a mapping */ 131 extern void tlb_flush_pte __P((vaddr_t addr, int ctx)); 132 extern void tlb_flush_ctx __P((int ctx)); 133 134 #endif /* _LOCORE */ 135 136 /* TSB tag masks */ 137 #define CTX_MASK ((1<<13)-1) 138 #define TSB_TAG_CTX_SHIFT 48 139 #define TSB_TAG_VA_SHIFT 22 140 #define TSB_TAG_G 0x8000000000000000LL 141 142 #define TSB_TAG_CTX(t) ((((int64_t)(t))>>TSB_TAG_CTX_SHIFT)&CTX_MASK) 143 #define TSB_TAG_VA(t) ((((int64_t)(t))<<TSB_TAG_VA_SHIFT)) 144 #define TSB_TAG(g,ctx,va) ((((u_int64_t)((g)!=0))<<63)|(((u_int64_t)(ctx)&CTX_MASK)<<TSB_TAG_CTX_SHIFT)|(((u_int64_t)va)>>TSB_TAG_VA_SHIFT)) 145 146 /* Page sizes */ 147 #define PGSZ_8K 0 148 #define PGSZ_64K 1 149 #define PGSZ_512K 2 150 #define PGSZ_4M 3 151 152 #define PGSZ_SHIFT 61 153 154 /* 155 * Why couldn't Sun pick better page sizes? 156 * 157 * Page sizes are 2**(12+(3*sz)), except for 8K which 158 * is 2**12+1 instead of 2**12. 159 */ 160 #define PG_SZ(s) (1<<(12+(s?(3*s):1))) 161 #define TLB_SZ(s) (((uint64_t)(s))<<PGSZ_SHIFT) 162 163 /* TLB data masks */ 164 #define TLB_V 0x8000000000000000LL 165 #define TLB_8K TLB_SZ(PGSZ_8K) 166 #define TLB_64K TLB_SZ(PGSZ_64K) 167 #define TLB_512K TLB_SZ(PGSZ_512K) 168 #define TLB_4M TLB_SZ(PGSZ_4M) 169 #define TLB_SZ_MASK 0x6000000000000000LL 170 #define TLB_NFO 0x1000000000000000LL 171 #define TLB_IE 0x0800000000000000LL 172 #define TLB_SOFT2_MASK 0x07fe000000000000LL 173 #define TLB_DIAG_MASK 0x0001fe0000000000LL 174 #define TLB_PA_MASK 0x000001ffffffe000LL 175 #define TLB_SOFT_MASK 0x0000000000001f80LL 176 /* S/W bits */ 177 /* Access & TSB locked bits are swapped so I can set access w/one insn */ 178 /* #define TLB_ACCESS 0x0000000000001000LL */ 179 #define TLB_ACCESS 0x0000000000000200LL 180 #define TLB_MODIFY 0x0000000000000800LL 181 #define TLB_REAL_W 0x0000000000000400LL 182 /* #define TLB_TSB_LOCK 0x0000000000000200LL */ 183 #define TLB_TSB_LOCK 0x0000000000001000LL 184 #define TLB_EXEC 0x0000000000000100LL 185 #define TLB_EXEC_ONLY 0x0000000000000080LL 186 /* H/W bits */ 187 #define TLB_L 0x0000000000000040LL 188 #define TLB_CACHE_MASK 0x0000000000000030LL 189 #define TLB_CP 0x0000000000000020LL 190 #define TLB_CV 0x0000000000000010LL 191 #define TLB_E 0x0000000000000008LL 192 #define TLB_P 0x0000000000000004LL 193 #define TLB_W 0x0000000000000002LL 194 #define TLB_G 0x0000000000000001LL 195 196 /* Use a bit in the SOFT2 area to indicate a locked mapping. */ 197 #define TLB_WIRED 0x0010000000000000LL 198 199 /* 200 * The following bits are used by locore so they should 201 * be duplicates of the above w/o the "long long" 202 */ 203 /* S/W bits */ 204 /* #define TTE_ACCESS 0x0000000000001000 */ 205 #define TTE_ACCESS 0x0000000000000200 206 #define TTE_MODIFY 0x0000000000000800 207 #define TTE_REAL_W 0x0000000000000400 208 /* #define TTE_TSB_LOCK 0x0000000000000200 */ 209 #define TTE_TSB_LOCK 0x0000000000001000 210 #define TTE_EXEC 0x0000000000000100 211 #define TTE_EXEC_ONLY 0x0000000000000080 212 /* H/W bits */ 213 #define TTE_L 0x0000000000000040 214 #define TTE_CACHE_MASK 0x0000000000000030 215 #define TTE_CP 0x0000000000000020 216 #define TTE_CV 0x0000000000000010 217 #define TTE_E 0x0000000000000008 218 #define TTE_P 0x0000000000000004 219 #define TTE_W 0x0000000000000002 220 #define TTE_G 0x0000000000000001 221 222 #define TTE_DATA_BITS "\177\20" \ 223 "b\77V\0" "f\75\2SIZE\0" "b\77V\0" "f\75\2SIZE\0" \ 224 "=\0008K\0" "=\00164K\0" "=\002512K\0" "=\0034M\0" \ 225 "b\74NFO\0" "b\73IE\0" "f\62\10SOFT2\0" \ 226 "f\51\10DIAG\0" "f\15\33PA<40:13>\0" "f\7\5SOFT\0" \ 227 "b\6L\0" "b\5CP\0" "b\4CV\0" \ 228 "b\3E\0" "b\2P\0" "b\1W\0" "b\0G\0" 229 230 #define TSB_DATA(g,sz,pa,priv,write,cache,aliased,valid,ie) \ 231 (((valid)?TLB_V:0LL)|TLB_SZ(sz)|(((u_int64_t)(pa))&TLB_PA_MASK)|\ 232 ((cache)?((aliased)?TLB_CP:TLB_CACHE_MASK):TLB_E)|\ 233 ((priv)?TLB_P:0LL)|((write)?TLB_W:0LL)|((g)?TLB_G:0LL)|((ie)?TLB_IE:0LL)) 234 235 #define MMU_CACHE_VIRT 0x3 236 #define MMU_CACHE_PHYS 0x2 237 #define MMU_CACHE_NONE 0x0 238 239 /* This needs to be updated for sun4u IOMMUs */ 240 /* 241 * IOMMU PTE bits. 242 */ 243 #define IOPTE_PPN_MASK 0x07ffff00 244 #define IOPTE_PPN_SHIFT 8 245 #define IOPTE_RSVD 0x000000f1 246 #define IOPTE_WRITE 0x00000004 247 #define IOPTE_VALID 0x00000002 248 249 /* 250 * This is purely for compatibility with the old SPARC machines. 251 */ 252 #define NBPRG (1 << 24) /* bytes per region */ 253 #define RGSHIFT 24 /* log2(NBPRG) */ 254 #define NSEGRG (NBPRG / NBPSG) /* segments per region */ 255 256 #define NBPSG (1 << 18) /* bytes per segment */ 257 #define SGSHIFT 18 /* log2(NBPSG) */ 258 259 /* there is no `struct pte'; we just use `int'; this is for non-4M only */ 260 #define PG_V 0x80000000 261 #define PG_PFNUM 0x0007ffff /* n.b.: only 16 bits on sun4c */ 262 263 /* virtual address to virtual region number */ 264 #define VA_VREG(va) (((unsigned int)(va) >> RGSHIFT) & 255) 265 266 /* virtual address to virtual segment number */ 267 #define VA_VSEG(va) (((unsigned int)(va) >> SGSHIFT) & 63) 268 269 #ifndef _LOCORE 270 typedef u_short pmeg_t; /* 10 bits needed per Sun-4 segmap entry */ 271 #endif 272 273 /* 274 * Here are the bit definitions for 4M/SRMMU pte's 275 */ 276 /* MMU TABLE ENTRIES */ 277 #define SRMMU_TETYPE 0x3 /* mask for table entry type */ 278 #define SRMMU_TEPTE 0x2 /* Page Table Entry */ 279 /* PTE FIELDS */ 280 #define SRMMU_PPNMASK 0xFFFFFF00 281 #define SRMMU_PPNPASHIFT 0x4 /* shift to put ppn into PAddr */ 282