xref: /netbsd/sys/arch/sparc64/sparc64/cache.c (revision bf9ec67e)
1 /*	$NetBSD: cache.c,v 1.5 2000/12/06 01:47:50 mrg Exp $ */
2 
3 /*
4  * Copyright (c) 1996
5  *	The President and Fellows of Harvard College. All rights reserved.
6  * Copyright (c) 1992, 1993
7  *	The Regents of the University of California.  All rights reserved.
8  *
9  * This software was developed by the Computer Systems Engineering group
10  * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
11  * contributed to Berkeley.
12  *
13  * All advertising materials mentioning features or use of this software
14  * must display the following acknowledgement:
15  *	This product includes software developed by Harvard University.
16  *	This product includes software developed by the University of
17  *	California, Lawrence Berkeley Laboratory.
18  *
19  * Redistribution and use in source and binary forms, with or without
20  * modification, are permitted provided that the following conditions
21  * are met:
22  *
23  * 1. Redistributions of source code must retain the above copyright
24  *    notice, this list of conditions and the following disclaimer.
25  * 2. Redistributions in binary form must reproduce the above copyright
26  *    notice, this list of conditions and the following disclaimer in the
27  *    documentation and/or other materials provided with the distribution.
28  * 3. All advertising materials mentioning features or use of this software
29  *    must display the following acknowledgement:
30  *	This product includes software developed by Aaron Brown and
31  *	Harvard University.
32  *	This product includes software developed by the University of
33  *	California, Berkeley and its contributors.
34  * 4. Neither the name of the University nor the names of its contributors
35  *    may be used to endorse or promote products derived from this software
36  *    without specific prior written permission.
37  *
38  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
39  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
40  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
41  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
42  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
43  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
44  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
45  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
46  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
47  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
48  * SUCH DAMAGE.
49  *
50  *	@(#)cache.c	8.2 (Berkeley) 10/30/93
51  *
52  */
53 
54 /*
55  * Cache routines.
56  *
57  * UltraSPARC has VIPT D$ and PIPT I$.
58  *
59  * TODO:
60  *	- rework range flush
61  */
62 
63 #include <sys/param.h>
64 #include <sys/systm.h>
65 
66 #include <machine/ctlreg.h>
67 #include <machine/pte.h>
68 
69 #include <sparc64/sparc64/cache.h>
70 
71 enum vactype vactype;
72 struct cachestats cachestats;
73 int cachedebug = 0;
74 
75 /*
76  * Enable the cache.
77  * The prom does this for us.
78  */
79 void
80 cache_enable()
81 {
82 	/*
83 	 * No point in implementing this unless we have a cache_disable().
84 	 * Anyway, sun4u ECC is generated in the E$, so we can't disable that
85 	 * and expect to use any RAM.
86 	 */
87 	cacheinfo.c_enabled = 1; /* enable cache flusing */
88 }
89 
90 /*
91  * Flush the given virtual page from the cache.
92  * (va is the actual address, and must be aligned on a page boundary.)
93  * To get the E$ we read to each cache line.
94  */
95 int
96 cache_flush_page(pa)
97 	paddr_t pa;
98 {
99 	register int i, j, ls;
100 	register char *p;
101 	register int *kp;
102 
103 #ifdef DEBUG
104 	if (cachedebug)
105 		printf("cache_flush_page %llx\n", (unsigned long long)pa);
106 	if (pa & PGOFSET)
107 		panic("cache_flush_page: asked to flush misaligned pa %llx", (unsigned long long)pa);
108 #endif
109 
110 	/* Don't flush if not enabled or not probed. */
111 	if (!cacheinfo.c_enabled) return 0;
112 
113 	cachestats.cs_npgflush++;
114 	p = (char *)(u_long)pa;
115 	ls = cacheinfo.c_linesize;
116 	i = NBPG >> cacheinfo.dc_l2linesize;
117 	/* Assume E$ takes care of itself*/
118 	kp = (int *)(u_long)((pa & (cacheinfo.ec_totalsize - 1)) + KERNBASE);
119 	j = 0; /* defeat optimizer? */
120 	for (; --i >= 0; p += ls) {
121 		flush(p);	/* Take care of I$. */
122 		j += kp[i];	/* Take care of E$. */
123 	}
124 	return j;
125 }
126 
127 /*
128  * Flush a range of virtual addresses (in the current context).
129  * The first byte is at (base&~PGOFSET) and the last one is just
130  * before byte (base+len).
131  *
132  * We may need to get more complex if we need to flush E$ because
133  * the virtual color may not match the physical color.  Assume cache
134  * coherence is handled by H/W.
135  */
136 
137 #define CACHE_FLUSH_MAGIC	(cacheinfo.ec_totalsize / NBPG)
138 
139 int
140 cache_flush(base, len)
141 	vaddr_t base;
142 	size_t len;
143 {
144 	int i, j, ls;
145 	vaddr_t baseoff;
146 	char *p;
147 	int *kp;
148 
149 #ifdef DEBUG
150 	if (cachedebug)
151 		printf("cache_flush %p %x\n", (void *)(u_long)base, (u_int)len);
152 #endif
153 
154 	/* Don't flush if not enabled or not probed. */
155 	if (!cacheinfo.c_enabled) return 0;
156 
157 	baseoff = (vaddr_t)base & PGOFSET;
158 	i = (baseoff + len + PGOFSET) >> PGSHIFT;
159 
160 	cachestats.cs_nraflush++;
161 
162 	i = min(i,CACHE_FLUSH_MAGIC);
163 
164 	p = (char *)((vaddr_t)base & ~baseoff);
165 	ls = cacheinfo.dc_linesize;
166 	i >>= cacheinfo.dc_l2linesize;
167 	/* Pick right physical color for E$ */
168 	kp = (int *)(((vaddr_t)p & (cacheinfo.ec_totalsize - 1)) + KERNBASE);
169 	j = 0; /* defeat optimizer? */
170 	for (; --i >= 0; p += ls) {
171 		flush(p);	/* Take care of I$. */
172 		j += kp[i];	/* Take care of E$. */
173 	}
174 	return j;
175 }
176