1 /* $NetBSD: cache.h,v 1.4 2002/04/16 23:13:13 eeh Exp $ */ 2 3 /* 4 * Copyright (c) 1996 5 * The President and Fellows of Harvard College. All rights reserved. 6 * Copyright (c) 1992, 1993 7 * The Regents of the University of California. All rights reserved. 8 * 9 * This software was developed by the Computer Systems Engineering group 10 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 11 * contributed to Berkeley. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 3. All advertising materials mentioning features or use of this software 22 * must display the following acknowledgement: 23 * This product includes software developed by Aaron Brown and 24 * Harvard University. 25 * This product includes software developed by the University of 26 * California, Berkeley and its contributors. 27 * 4. Neither the name of the University nor the names of its contributors 28 * may be used to endorse or promote products derived from this software 29 * without specific prior written permission. 30 * 31 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 32 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 33 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 34 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 35 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 39 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 40 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 41 * SUCH DAMAGE. 42 * 43 * @(#)cache.h 8.1 (Berkeley) 6/11/93 44 */ 45 46 enum vactype { VAC_NONE, VAC_WRITETHROUGH, VAC_WRITEBACK }; 47 48 extern enum vactype vactype; /* XXX move into cacheinfo struct */ 49 50 /* 51 * Cache tags can be written in control space, and must be set to 0 52 * (or invalid anyway) before turning on the cache. The tags are 53 * addressed as an array of 32-bit structures of the form: 54 * 55 * struct cache_tag { 56 * u_int :7, (unused; must be zero) 57 * ct_cid:3, (context ID) 58 * ct_w:1, (write flag from PTE) 59 * ct_s:1, (supervisor flag from PTE) 60 * ct_v:1, (set => cache entry is valid) 61 * :3, (unused; must be zero) 62 * ct_tid:14, (cache tag ID) 63 * :2; (unused; must be zero) 64 * }; 65 * 66 * The SPARCstation 1 cache sees virtual addresses as: 67 * 68 * struct cache_va { 69 * u_int :2, (unused; probably copies of va_tid<13>) 70 * cva_tid:14, (tag ID) 71 * cva_line:12, (cache line number) 72 * cva_byte:4; (byte in cache line) 73 * }; 74 * 75 * (The SS2 cache is similar but has half as many lines, each twice as long.) 76 * 77 * Note that, because the 12-bit line ID is `wider' than the page offset, 78 * it is possible to have one page map to two different cache lines. 79 * This can happen whenever two different physical pages have the same bits 80 * in the part of the virtual address that overlaps the cache line ID, i.e., 81 * bits <15:12>. In order to prevent cache duplication, we have to 82 * make sure that no one page has more than one virtual address where 83 * (va1 & 0xf000) != (va2 & 0xf000). (The cache hardware turns off ct_v 84 * when a cache miss occurs on a write, i.e., if va1 is in the cache and 85 * va2 is not, and you write to va2, va1 goes out of the cache. If va1 86 * is in the cache and va2 is not, reading va2 also causes va1 to become 87 * uncached, and the [same] data is then read from main memory into the 88 * cache.) 89 * 90 * The other alternative, of course, is to disable caching of aliased 91 * pages. (In a few cases this might be faster anyway, but we do it 92 * only when forced.) 93 * 94 * The Sun4, since it has an 8K pagesize instead of 4K, needs to check 95 * bits that are one position higher. 96 */ 97 98 /* 99 * The spitfire has a 16K two-way set associative level-1 I$ and a separate 100 * 16K level-1 D$. The I$ can be invalidated using the FLUSH instructions, 101 * so we don't really need to worry about it much. The D$ is 16K write-through 102 * direct mapped virtually addressed cache with two 16-byte sub-blocks per line. 103 * The E$ is a 512KB-4MB direct mapped physically indexed physically tagged cache. 104 * Since the level-1 caches are write-through, they don't need flushing and can be 105 * invalidated directly. 106 * 107 * The spitfire sees virtual addresses as: 108 * 109 * struct cache_va { 110 * u_int64_t :22, (unused; we only have 40-bit addresses) 111 * cva_tag:28, (tag ID) 112 * cva_line:9, (cache line number) 113 * cva_byte:5; (byte within line) 114 * }; 115 * 116 * Since there is one bit of overlap between the page offset and the line index, 117 * all we need to do is make sure that bit 14 of the va remains constant and we have 118 * no aliasing problems. 119 * 120 * Let me try again. Page size is 8K, cache size is 16K so if (va1&0x3fff != va2&0x3fff) 121 * we have a problem. Bit 14 *must* be the same for all mappings of a page to be cacheable 122 * in the D$. (The I$ is 16K 2-way associative--each bank is 8K. No conflict there.) 123 */ 124 125 /* Some more well-known values: */ 126 #define CACHE_ALIAS_MASK 0x7fff 127 #define CACHE_ALIAS_BITS 0x4000 128 129 /* 130 * True iff a1 and a2 are `bad' aliases (will cause cache duplication). 131 */ 132 #define BADALIAS(a1, a2) (((int)(a1) ^ (int)(a2)) & CACHE_ALIAS_BITS) 133 134 /* 135 * Routines for dealing with the cache. 136 */ 137 void cache_enable __P((void)); /* turn it on */ 138 int cache_flush_page __P((paddr_t)); /* flush page from E$ */ 139 int cache_flush __P((vaddr_t, vsize_t)); /* flush region */ 140 141 /* The following two are for I$ and D$ flushes and are in locore.s */ 142 void dcache_flush_page __P((paddr_t)); /* flush page from D$ */ 143 void icache_flush_page __P((paddr_t)); /* flush page from I$ */ 144 void blast_vcache __P((void)); /* Clear entire contents of I$ and D$ */ 145 146 /* The following flush a range from the D$ and I$ but not E$. */ 147 void cache_flush_virt __P((vaddr_t, vsize_t)); 148 void cache_flush_phys __P((paddr_t, psize_t, int)); 149 150 /* 151 * Cache control information. 152 */ 153 struct cacheinfo { 154 int c_totalsize; /* total size, in bytes */ 155 /* if split, MAX(icache,dcache) */ 156 int c_enabled; /* true => cache is enabled */ 157 int c_hwflush; /* true => have hardware flush */ 158 int c_linesize; /* line size, in bytes */ 159 int c_l2linesize; /* log2(linesize) */ 160 int c_physical; /* true => cache is physical */ 161 int c_split; /* true => cache is split */ 162 int ic_totalsize; /* instruction cache */ 163 int ic_enabled; 164 int ic_linesize; 165 int ic_l2linesize; 166 int dc_totalsize; /* data cache */ 167 int dc_enabled; 168 int dc_linesize; 169 int dc_l2linesize; 170 int ec_totalsize; /* external cache info */ 171 int ec_enabled; 172 int ec_linesize; 173 int ec_l2linesize; 174 }; 175 extern struct cacheinfo cacheinfo; 176 177 /* 178 * Cache control statistics. 179 */ 180 struct cachestats { 181 int cs_npgflush; /* # page flushes */ 182 int cs_nraflush; /* # range flushes */ 183 #ifdef notyet 184 int cs_ra[65]; /* pages/range */ 185 #endif 186 }; 187