1 /* $NetBSD: cpu.c,v 1.98 2010/11/06 11:46:03 uebayasi Exp $ */ 2 3 /* 4 * Copyright (c) 1996 5 * The President and Fellows of Harvard College. All rights reserved. 6 * Copyright (c) 1992, 1993 7 * The Regents of the University of California. All rights reserved. 8 * 9 * This software was developed by the Computer Systems Engineering group 10 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 11 * contributed to Berkeley. 12 * 13 * All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Harvard University. 16 * This product includes software developed by the University of 17 * California, Lawrence Berkeley Laboratory. 18 * 19 * Redistribution and use in source and binary forms, with or without 20 * modification, are permitted provided that the following conditions 21 * are met: 22 * 23 * 1. Redistributions of source code must retain the above copyright 24 * notice, this list of conditions and the following disclaimer. 25 * 2. Redistributions in binary form must reproduce the above copyright 26 * notice, this list of conditions and the following disclaimer in the 27 * documentation and/or other materials provided with the distribution. 28 * 3. All advertising materials mentioning features or use of this software 29 * must display the following acknowledgement: 30 * This product includes software developed by Aaron Brown and 31 * Harvard University. 32 * This product includes software developed by the University of 33 * California, Berkeley and its contributors. 34 * 4. Neither the name of the University nor the names of its contributors 35 * may be used to endorse or promote products derived from this software 36 * without specific prior written permission. 37 * 38 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 39 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 40 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 41 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 42 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 43 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 44 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 45 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 46 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 47 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 48 * SUCH DAMAGE. 49 * 50 * @(#)cpu.c 8.5 (Berkeley) 11/23/93 51 * 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.98 2010/11/06 11:46:03 uebayasi Exp $"); 56 57 #include "opt_multiprocessor.h" 58 59 #include <sys/param.h> 60 #include <sys/systm.h> 61 #include <sys/device.h> 62 #include <sys/kernel.h> 63 #include <sys/reboot.h> 64 65 #include <uvm/uvm.h> 66 67 #include <machine/autoconf.h> 68 #include <machine/cpu.h> 69 #include <machine/reg.h> 70 #include <machine/trap.h> 71 #include <machine/pmap.h> 72 #include <machine/sparc64.h> 73 #include <machine/openfirm.h> 74 75 #include <sparc64/sparc64/cache.h> 76 77 int ecache_min_line_size; 78 79 /* Linked list of all CPUs in system. */ 80 #if defined(MULTIPROCESSOR) 81 int sparc_ncpus = 0; 82 #endif 83 struct cpu_info *cpus = NULL; 84 85 volatile sparc64_cpuset_t cpus_active;/* set of active cpus */ 86 struct cpu_bootargs *cpu_args; /* allocated very early in pmap_bootstrap. */ 87 struct pool_cache *fpstate_cache; 88 89 static struct cpu_info *alloc_cpuinfo(u_int); 90 91 /* The following are used externally (sysctl_hw). */ 92 char machine[] = MACHINE; /* from <machine/param.h> */ 93 char machine_arch[] = MACHINE_ARCH; /* from <machine/param.h> */ 94 char cpu_model[100]; /* machine model (primary CPU) */ 95 extern char machine_model[]; 96 97 /* These are used in locore.s, and are maximums */ 98 int dcache_line_size; 99 int dcache_size; 100 int icache_line_size; 101 int icache_size; 102 103 #ifdef MULTIPROCESSOR 104 static const char *ipi_evcnt_names[IPI_EVCNT_NUM] = IPI_EVCNT_NAMES; 105 #endif 106 107 static void cpu_reset_fpustate(void); 108 109 volatile int sync_tick = 0; 110 111 /* The CPU configuration driver. */ 112 void cpu_attach(struct device *, struct device *, void *); 113 int cpu_match(struct device *, struct cfdata *, void *); 114 115 CFATTACH_DECL_NEW(cpu, 0, cpu_match, cpu_attach, NULL, NULL); 116 117 static int 118 upaid_from_node(u_int cpu_node) 119 { 120 int portid; 121 122 if (OF_getprop(cpu_node, "upa-portid", &portid, sizeof(portid)) <= 0 && 123 OF_getprop(cpu_node, "portid", &portid, sizeof(portid)) <= 0) 124 panic("cpu node w/o upa-portid"); 125 126 return portid; 127 } 128 129 struct cpu_info * 130 alloc_cpuinfo(u_int cpu_node) 131 { 132 paddr_t pa0, pa; 133 vaddr_t va, va0; 134 vsize_t sz = 8 * PAGE_SIZE; 135 int portid; 136 struct cpu_info *cpi, *ci; 137 extern paddr_t cpu0paddr; 138 139 /* 140 * Check for UPAID in the cpus list. 141 */ 142 portid = upaid_from_node(cpu_node); 143 144 for (cpi = cpus; cpi != NULL; cpi = cpi->ci_next) 145 if (cpi->ci_cpuid == portid) 146 return cpi; 147 148 /* Allocate the aligned VA and determine the size. */ 149 va = uvm_km_alloc(kernel_map, sz, 8 * PAGE_SIZE, UVM_KMF_VAONLY); 150 if (!va) 151 panic("alloc_cpuinfo: no virtual space"); 152 va0 = va; 153 154 pa0 = cpu0paddr; 155 cpu0paddr += sz; 156 157 for (pa = pa0; pa < cpu0paddr; pa += PAGE_SIZE, va += PAGE_SIZE) 158 pmap_kenter_pa(va, pa, VM_PROT_READ | VM_PROT_WRITE, 0); 159 160 pmap_update(pmap_kernel()); 161 162 cpi = (struct cpu_info *)(va0 + CPUINFO_VA - INTSTACK); 163 164 memset((void *)va0, 0, sz); 165 166 /* 167 * Initialize cpuinfo structure. 168 * 169 * Arrange pcb, idle stack and interrupt stack in the same 170 * way as is done for the boot CPU in pmap.c. 171 */ 172 cpi->ci_next = NULL; 173 cpi->ci_curlwp = NULL; 174 cpi->ci_cpuid = portid; 175 cpi->ci_fplwp = NULL; 176 cpi->ci_spinup = NULL; 177 cpi->ci_paddr = pa0; 178 cpi->ci_self = cpi; 179 cpi->ci_node = cpu_node; 180 cpi->ci_idepth = -1; 181 memset(cpi->ci_intrpending, -1, sizeof(cpi->ci_intrpending)); 182 183 /* 184 * Finally, add itself to the list of active cpus. 185 */ 186 for (ci = cpus; ci->ci_next != NULL; ci = ci->ci_next) 187 ; 188 #ifdef MULTIPROCESSOR 189 ci->ci_next = cpi; 190 #endif 191 return (cpi); 192 } 193 194 int 195 cpu_match(struct device *parent, struct cfdata *cf, void *aux) 196 { 197 struct mainbus_attach_args *ma = aux; 198 199 if (strcmp(cf->cf_name, ma->ma_name) != 0) 200 return 0; 201 202 /* 203 * If we are going to only attach a single cpu, make sure 204 * to pick the one we are running on right now. 205 */ 206 if (upaid_from_node(ma->ma_node) != CPU_UPAID) { 207 #ifdef MULTIPROCESSOR 208 if (boothowto & RB_MD1) 209 #endif 210 return 0; 211 } 212 213 return 1; 214 } 215 216 static void 217 cpu_reset_fpustate(void) 218 { 219 struct fpstate64 *fpstate; 220 struct fpstate64 fps[2]; 221 222 /* This needs to be 64-byte aligned */ 223 fpstate = ALIGNFPSTATE(&fps[1]); 224 225 /* 226 * Get the FSR and clear any exceptions. If we do not unload 227 * the queue here and it is left over from a previous crash, we 228 * will panic in the first loadfpstate(), due to a sequence error, 229 * so we need to dump the whole state anyway. 230 */ 231 fpstate->fs_fsr = 7 << FSR_VER_SHIFT; /* 7 is reserved for "none" */ 232 savefpstate(fpstate); 233 } 234 235 /* 236 * Attach the CPU. 237 * Discover interesting goop about the virtual address cache 238 * (slightly funny place to do it, but this is where it is to be found). 239 */ 240 void 241 cpu_attach(struct device *parent, struct device *dev, void *aux) 242 { 243 int node; 244 long clk; 245 struct mainbus_attach_args *ma = aux; 246 struct cpu_info *ci; 247 const char *sep; 248 register int i, l; 249 int bigcache, cachesize; 250 char buf[100]; 251 int totalsize = 0; 252 int linesize, dcachesize, icachesize; 253 254 /* tell them what we have */ 255 node = ma->ma_node; 256 257 /* 258 * Allocate cpu_info structure if needed. 259 */ 260 ci = alloc_cpuinfo((u_int)node); 261 262 /* 263 * Only do this on the boot cpu. Other cpu's call 264 * cpu_reset_fpustate() from cpu_hatch() before they 265 * call into the idle loop. 266 * For other cpus, we need to call mi_cpu_attach() 267 * and complete setting up cpcb. 268 */ 269 if (ci->ci_flags & CPUF_PRIMARY) { 270 fpstate_cache = pool_cache_init(sizeof(struct fpstate64), 271 BLOCK_SIZE, 0, 0, "fpstate", NULL, 272 IPL_NONE, NULL, NULL, NULL); 273 cpu_reset_fpustate(); 274 } 275 #ifdef MULTIPROCESSOR 276 else { 277 mi_cpu_attach(ci); 278 ci->ci_cpcb = lwp_getpcb(ci->ci_data.cpu_idlelwp); 279 } 280 for (i = 0; i < IPI_EVCNT_NUM; ++i) 281 evcnt_attach_dynamic(&ci->ci_ipi_evcnt[i], EVCNT_TYPE_INTR, 282 NULL, device_xname(dev), ipi_evcnt_names[i]); 283 #endif 284 evcnt_attach_dynamic(&ci->ci_tick_evcnt, EVCNT_TYPE_INTR, NULL, 285 device_xname(dev), "timer"); 286 mutex_init(&ci->ci_ctx_lock, MUTEX_SPIN, IPL_VM); 287 288 clk = prom_getpropint(node, "clock-frequency", 0); 289 if (clk == 0) { 290 /* 291 * Try to find it in the OpenPROM root... 292 */ 293 clk = prom_getpropint(findroot(), "clock-frequency", 0); 294 } 295 if (clk) { 296 /* Tell OS what frequency we run on */ 297 ci->ci_cpu_clockrate[0] = clk; 298 ci->ci_cpu_clockrate[1] = clk / 1000000; 299 } 300 301 snprintf(buf, sizeof buf, "%s @ %s MHz", 302 prom_getpropstring(node, "name"), clockfreq(clk)); 303 snprintf(cpu_model, sizeof cpu_model, "%s (%s)", machine_model, buf); 304 305 aprint_normal(": %s, UPA id %d\n", buf, ci->ci_cpuid); 306 aprint_naive("\n"); 307 aprint_normal_dev(dev, ""); 308 309 bigcache = 0; 310 311 icachesize = prom_getpropint(node, "icache-size", 0); 312 if (icachesize > icache_size) 313 icache_size = icachesize; 314 linesize = l = prom_getpropint(node, "icache-line-size", 0); 315 if (linesize > icache_line_size) 316 icache_line_size = linesize; 317 318 for (i = 0; (1 << i) < l && l; i++) 319 /* void */; 320 if ((1 << i) != l && l) 321 panic("bad icache line size %d", l); 322 totalsize = icachesize; 323 if (totalsize == 0) 324 totalsize = l * 325 prom_getpropint(node, "icache-nlines", 64) * 326 prom_getpropint(node, "icache-associativity", 1); 327 328 cachesize = totalsize / 329 prom_getpropint(node, "icache-associativity", 1); 330 bigcache = cachesize; 331 332 sep = ""; 333 if (totalsize > 0) { 334 aprint_normal("%s%ldK instruction (%ld b/l)", sep, 335 (long)totalsize/1024, 336 (long)linesize); 337 sep = ", "; 338 } 339 340 dcachesize = prom_getpropint(node, "dcache-size", 0); 341 if (dcachesize > dcache_size) 342 dcache_size = dcachesize; 343 linesize = l = prom_getpropint(node, "dcache-line-size", 0); 344 if (linesize > dcache_line_size) 345 dcache_line_size = linesize; 346 347 for (i = 0; (1 << i) < l && l; i++) 348 /* void */; 349 if ((1 << i) != l && l) 350 panic("bad dcache line size %d", l); 351 totalsize = dcachesize; 352 if (totalsize == 0) 353 totalsize = l * 354 prom_getpropint(node, "dcache-nlines", 128) * 355 prom_getpropint(node, "dcache-associativity", 1); 356 357 cachesize = totalsize / 358 prom_getpropint(node, "dcache-associativity", 1); 359 if (cachesize > bigcache) 360 bigcache = cachesize; 361 362 if (totalsize > 0) { 363 aprint_normal("%s%ldK data (%ld b/l)", sep, 364 (long)totalsize/1024, 365 (long)linesize); 366 sep = ", "; 367 } 368 369 linesize = l = 370 prom_getpropint(node, "ecache-line-size", 0); 371 for (i = 0; (1 << i) < l && l; i++) 372 /* void */; 373 if ((1 << i) != l && l) 374 panic("bad ecache line size %d", l); 375 totalsize = prom_getpropint(node, "ecache-size", 0); 376 if (totalsize == 0) 377 totalsize = l * 378 prom_getpropint(node, "ecache-nlines", 32768) * 379 prom_getpropint(node, "ecache-associativity", 1); 380 381 cachesize = totalsize / 382 prom_getpropint(node, "ecache-associativity", 1); 383 if (cachesize > bigcache) 384 bigcache = cachesize; 385 386 if (totalsize > 0) { 387 aprint_normal("%s%ldK external (%ld b/l)", sep, 388 (long)totalsize/1024, 389 (long)linesize); 390 } 391 aprint_normal("\n"); 392 393 if (ecache_min_line_size == 0 || 394 linesize < ecache_min_line_size) 395 ecache_min_line_size = linesize; 396 397 /* 398 * Now that we know the size of the largest cache on this CPU, 399 * re-color our pages. 400 */ 401 uvm_page_recolor(atop(bigcache)); /* XXX */ 402 403 } 404 405 #if defined(MULTIPROCESSOR) 406 vaddr_t cpu_spinup_trampoline; 407 408 /* 409 * Start secondary processors in motion. 410 */ 411 void 412 cpu_boot_secondary_processors(void) 413 { 414 int i, pstate; 415 struct cpu_info *ci; 416 417 sync_tick = 0; 418 419 sparc64_ipi_init(); 420 421 if (boothowto & RB_MD1) { 422 cpus[0].ci_next = NULL; 423 sparc_ncpus = ncpu = ncpuonline = 1; 424 return; 425 } 426 427 for (ci = cpus; ci != NULL; ci = ci->ci_next) { 428 if (ci->ci_cpuid == CPU_UPAID) 429 continue; 430 431 cpu_pmap_prepare(ci, false); 432 cpu_args->cb_node = ci->ci_node; 433 cpu_args->cb_cpuinfo = ci->ci_paddr; 434 membar_sync(); 435 436 /* Disable interrupts and start another CPU. */ 437 pstate = getpstate(); 438 setpstate(PSTATE_KERN); 439 440 prom_startcpu(ci->ci_node, (void *)cpu_spinup_trampoline, 0); 441 442 for (i = 0; i < 2000; i++) { 443 membar_sync(); 444 if (CPUSET_HAS(cpus_active, ci->ci_index)) 445 break; 446 delay(10000); 447 } 448 449 /* synchronize %tick ( to some degree at least ) */ 450 delay(1000); 451 sync_tick = 1; 452 membar_sync(); 453 settick(0); 454 455 setpstate(pstate); 456 457 if (!CPUSET_HAS(cpus_active, ci->ci_index)) 458 printf("cpu%d: startup failed\n", ci->ci_cpuid); 459 } 460 } 461 462 void 463 cpu_hatch(void) 464 { 465 char *v = (char*)CPUINFO_VA; 466 int i; 467 468 for (i = 0; i < 4*PAGE_SIZE; i += sizeof(long)) 469 flush(v + i); 470 471 cpu_pmap_init(curcpu()); 472 CPUSET_ADD(cpus_active, cpu_number()); 473 cpu_reset_fpustate(); 474 curlwp = curcpu()->ci_data.cpu_idlelwp; 475 membar_sync(); 476 477 /* wait for the boot CPU to flip the switch */ 478 while (sync_tick == 0) { 479 /* we do nothing here */ 480 } 481 settick(0); 482 483 tickintr_establish(PIL_CLOCK, tickintr); 484 spl0(); 485 } 486 #endif /* MULTIPROCESSOR */ 487