1 /* $NetBSD: timerreg.h,v 1.5 2005/12/11 12:19:15 christos Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. Neither the name of the University nor the names of its contributors 25 * may be used to endorse or promote products derived from this software 26 * without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 * 40 * @(#)timerreg.h 8.1 (Berkeley) 6/11/93 41 */ 42 43 /* 44 * Sun-4c counter/timer registers. The timers are implemented within 45 * the cache chip (!). The counter and limit fields below could be 46 * defined as: 47 * 48 * struct { 49 * u_int t_limit:1, // limit reached 50 * t_usec:21, // counter value in microseconds 51 * t_mbz:10; // always zero 52 * }; 53 * 54 * but this is more trouble than it is worth. 55 * 56 * These timers work in a rather peculiar fashion. Most clock counters 57 * run to 0 (as, e.g., on the VAX, where the ICR counts up to 0 from a 58 * large unsigned number). On the Sun-4c, it counts up to a limit. But 59 * for some reason, when it reaches the limit, it resets to 1, not 0. 60 * Thus, if the limit is set to 4, the counter counts like this: 61 * 62 * 1, 2, 3, 1, 2, 3, ... 63 * 64 * and if we want to divide by N we must set the limit register to N+1. 65 * 66 * Sun-4m counters/timer registers are similar, with these exceptions: 67 * 68 * - the limit and counter registers have changed positions.. 69 * - both limit and counter registers are 22 bits wide, but 70 * they count in 500ns increments (bit 9 being the least 71 * significant bit). 72 * 73 * Note that we still use the `sun4c' masks and shifts to compute 74 * the bit pattern, given the tick period in microseconds, resulting 75 * in a limit value that is 1 too high. This means that (with HZ=100) 76 * the clock will err on the slow side by 500ns/10ms (or 0.00005 %). 77 * We dont bother. 78 * 79 * Sun-4u counters/timer are similar but: 80 * 81 * - the registers have been shuffled around once again. We need 82 * to use offsets from the 3 addresses the ROM provides us. 83 * - The counters are 28 bits wide with 1us accuracy. 84 * - You can make them do funky things with the limit register 85 * - They have standard 64-bit SBUS control registers. 86 * 87 * There is a problem on the Ultra5 and Ultra10. As the PCI controller 88 * doesn't include the timer, there are no `counter-timer' nodes here 89 * and so we must use %tick. 90 */ 91 #ifndef _LOCORE 92 struct timer_4 { 93 volatile int t_counter; /* counter reg */ 94 volatile int t_limit; /* limit reg */ 95 }; 96 97 struct timerreg_4 { 98 struct timer_4 t_c10; /* counter that interrupts at ipl 10 */ 99 struct timer_4 t_c14; /* counter that interrupts at ipl 14 */ 100 }; 101 102 struct timer_4m { /* counter that interrupts at ipl 10 */ 103 volatile int t_limit; /* limit register */ 104 volatile int t_counter; /* counter register */ 105 volatile int t_limit_nr; /* limit reg, non-resetting */ 106 volatile int t_reserved; 107 volatile int t_cfg; /* a configuration register */ 108 /* 109 * Note: The SparcClassic manual only defines this one bit 110 * I suspect there are more in multi-processor machines. 111 */ 112 #define TMR_CFG_USER 1 113 }; 114 115 struct timer_4u { 116 volatile int64_t t_count; /* counter reg */ 117 volatile int64_t t_limit; /* limit reg */ 118 119 #define TMR_LIM_IEN 0x80000000 /* interrupt enable bit */ 120 #define TMR_LIM_RELOAD 0x40000000 /* reload counter to 0 */ 121 #define TMR_LIM_PERIODIC 0x20000000 /* reset when limit is reached */ 122 #define TMR_LIM_MASK 0x1fffffff 123 }; 124 125 struct timerreg_4u { 126 struct timer_4u* t_timer; /* There are two of them */ 127 volatile int64_t* t_clrintr; /* There are two of these, too. */ 128 volatile int64_t* t_mapintr; /* Same here. */ 129 }; 130 131 struct counter_4m { /* counter that interrupts at ipl 14 */ 132 volatile int t_limit; /* limit register */ 133 volatile int t_counter; /* counter register */ 134 volatile int t_limit_nr; /* limit reg, non-resetting */ 135 volatile int t_ss; /* Start/Stop register */ 136 #define TMR_USER_RUN 1 137 }; 138 139 #endif /* _LOCORE */ 140 141 #define TMR_LIMIT 0x80000000 /* counter reached its limit */ 142 #define TMR_SHIFT 10 /* shift to obtain microseconds */ 143 #define TMR_MASK 0x1fffff /* 21 bits */ 144 145 /* Compute a limit that causes the timer to fire every n microseconds. */ 146 /* #define tmr_ustolim(n) (((n) + 1) << TMR_SHIFT) */ 147 #define tmr_ustolim(n) ((n)) 148 149 /*efine TMR_SHIFT4M 9 -* shift to obtain microseconds */ 150 /*efine tmr_ustolim(n) (((2*(n)) + 1) << TMR_SHIFT4M)*/ 151 152 153 154