1 /* $NetBSD: timerreg.h,v 1.3 1999/06/05 05:10:01 mrg Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. All advertising materials mentioning features or use of this software 25 * must display the following acknowledgement: 26 * This product includes software developed by the University of 27 * California, Berkeley and its contributors. 28 * 4. Neither the name of the University nor the names of its contributors 29 * may be used to endorse or promote products derived from this software 30 * without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 35 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 38 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 39 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 40 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 41 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 42 * SUCH DAMAGE. 43 * 44 * @(#)timerreg.h 8.1 (Berkeley) 6/11/93 45 */ 46 47 /* 48 * Sun-4c counter/timer registers. The timers are implemented within 49 * the cache chip (!). The counter and limit fields below could be 50 * defined as: 51 * 52 * struct { 53 * u_int t_limit:1, // limit reached 54 * t_usec:21, // counter value in microseconds 55 * t_mbz:10; // always zero 56 * }; 57 * 58 * but this is more trouble than it is worth. 59 * 60 * These timers work in a rather peculiar fashion. Most clock counters 61 * run to 0 (as, e.g., on the VAX, where the ICR counts up to 0 from a 62 * large unsigned number). On the Sun-4c, it counts up to a limit. But 63 * for some reason, when it reaches the limit, it resets to 1, not 0. 64 * Thus, if the limit is set to 4, the counter counts like this: 65 * 66 * 1, 2, 3, 1, 2, 3, ... 67 * 68 * and if we want to divide by N we must set the limit register to N+1. 69 * 70 * Sun-4m counters/timer registers are similar, with these exceptions: 71 * 72 * - the limit and counter registers have changed positions.. 73 * - both limit and counter registers are 22 bits wide, but 74 * they count in 500ns increments (bit 9 being the least 75 * significant bit). 76 * 77 * Note that we still use the `sun4c' masks and shifts to compute 78 * the bit pattern, given the tick period in microseconds, resulting 79 * in a limit value that is 1 too high. This means that (with HZ=100) 80 * the clock will err on the slow side by 500ns/10ms (or 0.00005 %). 81 * We dont bother. 82 * 83 * Sun-4u counters/timer are similar but: 84 * 85 * - the registers have been shuffled around once again. We need 86 * to use offsets from the 3 addresses the ROM provides us. 87 * - The counters are 28 bits wide with 1us accuracy. 88 * - You can make them do funky things with the limit register 89 * - They have standard 64-bit SBUS control registers. 90 * 91 * There is a problem on the Ultra5 and Ultra10. As the PCI controller 92 * doesn't include the timer, there are no `counter-timer' nodes here 93 * and so we must use %tick. 94 */ 95 #ifndef _LOCORE 96 struct timer_4 { 97 volatile int t_counter; /* counter reg */ 98 volatile int t_limit; /* limit reg */ 99 }; 100 101 struct timerreg_4 { 102 struct timer_4 t_c10; /* counter that interrupts at ipl 10 */ 103 struct timer_4 t_c14; /* counter that interrupts at ipl 14 */ 104 }; 105 106 struct timer_4m { /* counter that interrupts at ipl 10 */ 107 volatile int t_limit; /* limit register */ 108 volatile int t_counter; /* counter register */ 109 volatile int t_limit_nr; /* limit reg, non-resetting */ 110 volatile int t_reserved; 111 volatile int t_cfg; /* a configuration register */ 112 /* 113 * Note: The SparcClassic manual only defines this one bit 114 * I suspect there are more in multi-processor machines. 115 */ 116 #define TMR_CFG_USER 1 117 }; 118 119 struct timer_4u { 120 volatile int64_t t_count; /* counter reg */ 121 volatile int64_t t_limit; /* limit reg */ 122 123 #define TMR_LIM_IEN 0x80000000 /* interrupt enable bit */ 124 #define TMR_LIM_RELOAD 0x40000000 /* reload counter to 0 */ 125 #define TMR_LIM_PERIODIC 0x20000000 /* reset when limit is reached */ 126 #define TMR_LIM_MASK 0x1fffffff 127 }; 128 129 struct timerreg_4u { 130 struct timer_4u* t_timer; /* There are two of them */ 131 volatile int64_t* t_clrintr; /* There are two of these, too. */ 132 volatile int64_t* t_mapintr; /* Same here. */ 133 }; 134 135 struct counter_4m { /* counter that interrupts at ipl 14 */ 136 volatile int t_limit; /* limit register */ 137 volatile int t_counter; /* counter register */ 138 volatile int t_limit_nr; /* limit reg, non-resetting */ 139 volatile int t_ss; /* Start/Stop register */ 140 #define TMR_USER_RUN 1 141 }; 142 143 #endif /* _LOCORE */ 144 145 #define TMR_LIMIT 0x80000000 /* counter reached its limit */ 146 #define TMR_SHIFT 10 /* shift to obtain microseconds */ 147 #define TMR_MASK 0x1fffff /* 21 bits */ 148 149 /* Compute a limit that causes the timer to fire every n microseconds. */ 150 /* #define tmr_ustolim(n) (((n) + 1) << TMR_SHIFT) */ 151 #define tmr_ustolim(n) ((n)) 152 153 /*efine TMR_SHIFT4M 9 -* shift to obtain microseconds */ 154 /*efine tmr_ustolim(n) (((2*(n)) + 1) << TMR_SHIFT4M)*/ 155 156 157 158