1 /* $NetBSD: if_ie_mbmem.c,v 1.3 2001/06/27 17:32:44 fredette Exp $ */ 2 3 /*- 4 * Copyright (c) 1995 Charles D. Cranor 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Charles D. Cranor. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Converted to SUN ie driver by Charles D. Cranor, 35 * October 1994, January 1995. 36 */ 37 38 /* 39 * The i82586 is a very painful chip, found in sun2's, sun3's, sun-4/100's 40 * sun-4/200's, and VME based suns. The byte order is all wrong for a 41 * SUN, making life difficult. Programming this chip is mostly the same, 42 * but certain details differ from system to system. This driver is 43 * written so that different "ie" interfaces can be controled by the same 44 * driver. 45 */ 46 47 /* 48 * programming notes: 49 * 50 * the ie chip operates in a 24 bit address space. 51 * 52 * most ie interfaces appear to be divided into two parts: 53 * - generic 586 stuff 54 * - board specific 55 * 56 * generic: 57 * the generic stuff of the ie chip is all done with data structures 58 * that live in the chip's memory address space. the chip expects 59 * its main data structure (the sys conf ptr -- SCP) to be at a fixed 60 * address in its 24 bit space: 0xfffff4 61 * 62 * the SCP points to another structure called the ISCP. 63 * the ISCP points to another structure called the SCB. 64 * the SCB has a status field, a linked list of "commands", and 65 * a linked list of "receive buffers". these are data structures that 66 * live in memory, not registers. 67 * 68 * board: 69 * to get the chip to do anything, you first put a command in the 70 * command data structure list. then you have to signal "attention" 71 * to the chip to get it to look at the command. how you 72 * signal attention depends on what board you have... on PC's 73 * there is an i/o port number to do this, on sun's there is a 74 * register bit you toggle. 75 * 76 * to get data from the chip you program it to interrupt... 77 * 78 * 79 * sun issues: 80 * 81 * there are 3 kinds of sun "ie" interfaces: 82 * 1 - a VME/multibus card 83 * 2 - an on-board interface (sun3's, sun-4/100's, and sun-4/200's) 84 * 3 - another VME board called the 3E 85 * 86 * the VME boards lives in vme16 space. only 16 and 8 bit accesses 87 * are allowed, so functions that copy data must be aware of this. 88 * 89 * the chip is an intel chip. this means that the byte order 90 * on all the "short"s in the chip's data structures is wrong. 91 * so, constants described in the intel docs are swapped for the sun. 92 * that means that any buffer pointers you give the chip must be 93 * swapped to intel format. yuck. 94 * 95 * VME/multibus interface: 96 * for the multibus interface the board ignores the top 4 bits 97 * of the chip address. the multibus interface has its own 98 * MMU like page map (without protections or valid bits, etc). 99 * there are 256 pages of physical memory on the board (each page 100 * is 1024 bytes). There are 1024 slots in the page map. so, 101 * a 1024 byte page takes up 10 bits of address for the offset, 102 * and if there are 1024 slots in the page that is another 10 bits 103 * of the address. That makes a 20 bit address, and as stated 104 * earlier the board ignores the top 4 bits, so that accounts 105 * for all 24 bits of address. 106 * 107 * Note that the last entry of the page map maps the top of the 108 * 24 bit address space and that the SCP is supposed to be at 109 * 0xfffff4 (taking into account allignment). so, 110 * for multibus, that entry in the page map has to be used for the SCP. 111 * 112 * The page map effects BOTH how the ie chip sees the 113 * memory, and how the host sees it. 114 * 115 * The page map is part of the "register" area of the board 116 * 117 * The page map to control where ram appears in the address space. 118 * We choose to have RAM start at 0 in the 24 bit address space. 119 * 120 * to get the phyiscal address of the board's RAM you must take the 121 * top 12 bits of the physical address of the register address and 122 * or in the 4 bits from the status word as bits 17-20 (remember that 123 * the board ignores the chip's top 4 address lines). For example: 124 * if the register is @ 0xffe88000, then the top 12 bits are 0xffe00000. 125 * to get the 4 bits from the status word just do status & IEMBMEM_HADDR. 126 * suppose the value is "4". Then just shift it left 16 bits to get 127 * it into bits 17-20 (e.g. 0x40000). Then or it to get the 128 * address of RAM (in our example: 0xffe40000). see the attach routine! 129 * 130 * 131 * on-board interface: 132 * 133 * on the onboard ie interface the 24 bit address space is hardwired 134 * to be 0xff000000 -> 0xffffffff of KVA. this means that sc_iobase 135 * will be 0xff000000. sc_maddr will be where ever we allocate RAM 136 * in KVA. note that since the SCP is at a fixed address it means 137 * that we have to allocate a fixed KVA for the SCP. 138 * <fill in useful info later> 139 * 140 * 141 * VME3E interface: 142 * 143 * <fill in useful info later> 144 * 145 */ 146 147 #include <sys/param.h> 148 #include <sys/systm.h> 149 #include <sys/errno.h> 150 #include <sys/device.h> 151 #include <sys/protosw.h> 152 #include <sys/socket.h> 153 154 #include <net/if.h> 155 #include <net/if_types.h> 156 #include <net/if_dl.h> 157 #include <net/if_media.h> 158 #include <net/if_ether.h> 159 160 #include <machine/autoconf.h> 161 #include <machine/idprom.h> 162 #include <machine/bus.h> 163 #include <machine/intr.h> 164 #include <machine/cpu.h> 165 166 #include <dev/ic/i82586reg.h> 167 #include <dev/ic/i82586var.h> 168 169 #include "locators.h" 170 171 /* 172 * VME/multibus definitions 173 */ 174 #define IEMBMEM_PAGESIZE 1024 /* bytes */ 175 #define IEMBMEM_PAGSHIFT 10 /* bits */ 176 #define IEMBMEM_NPAGES 256 /* number of pages on chip */ 177 #define IEMBMEM_MAPSZ 1024 /* number of entries in the map */ 178 179 /* 180 * PTE for the page map 181 */ 182 #define IEMBMEM_SBORDR 0x8000 /* sun byte order */ 183 #define IEMBMEM_IBORDR 0x0000 /* intel byte ordr */ 184 185 #define IEMBMEM_P2MEM 0x2000 /* memory is on P2 */ 186 #define IEMBMEM_OBMEM 0x0000 /* memory is on board */ 187 188 #define IEMBMEM_PGMASK 0x0fff /* gives the physical page frame number */ 189 190 struct iembmem { 191 u_int16_t pgmap[IEMBMEM_MAPSZ]; 192 u_int16_t xxx[32]; /* prom */ 193 u_int16_t status; /* see below for bits */ 194 u_int16_t xxx2; /* filler */ 195 u_int16_t pectrl; /* parity control (see below) */ 196 u_int16_t peaddr; /* low 16 bits of address */ 197 }; 198 199 /* 200 * status bits 201 */ 202 #define IEMBMEM_RESET 0x8000 /* reset board */ 203 #define IEMBMEM_ONAIR 0x4000 /* go out of loopback 'on-air' */ 204 #define IEMBMEM_ATTEN 0x2000 /* attention */ 205 #define IEMBMEM_IENAB 0x1000 /* interrupt enable */ 206 #define IEMBMEM_PEINT 0x0800 /* parity error interrupt enable */ 207 #define IEMBMEM_PERR 0x0200 /* parity error flag */ 208 #define IEMBMEM_INT 0x0100 /* interrupt flag */ 209 #define IEMBMEM_P2EN 0x0020 /* enable p2 bus */ 210 #define IEMBMEM_256K 0x0010 /* 256kb rams */ 211 #define IEMBMEM_HADDR 0x000f /* mask for bits 17-20 of address */ 212 213 /* 214 * parity control 215 */ 216 #define IEMBMEM_PARACK 0x0100 /* parity error ack */ 217 #define IEMBMEM_PARSRC 0x0080 /* parity error source */ 218 #define IEMBMEM_PAREND 0x0040 /* which end of the data got the error */ 219 #define IEMBMEM_PARADR 0x000f /* mask to get bits 17-20 of parity address */ 220 221 /* Supported media */ 222 static int media[] = { 223 IFM_ETHER | IFM_10_2, 224 }; 225 #define NMEDIA (sizeof(media) / sizeof(media[0])) 226 227 /* 228 * the 3E board not supported (yet?) 229 */ 230 231 232 static void ie_mbmemreset __P((struct ie_softc *, int)); 233 static void ie_mbmemattend __P((struct ie_softc *, int)); 234 static void ie_mbmemrun __P((struct ie_softc *)); 235 static int ie_mbmemintr __P((struct ie_softc *, int)); 236 237 int ie_mbmem_match __P((struct device *, struct cfdata *, void *)); 238 void ie_mbmem_attach __P((struct device *, struct device *, void *)); 239 240 struct ie_mbmem_softc { 241 struct ie_softc ie; 242 bus_space_tag_t ievt; 243 bus_space_handle_t ievh; 244 }; 245 246 struct cfattach ie_mbmem_ca = { 247 sizeof(struct ie_mbmem_softc), ie_mbmem_match, ie_mbmem_attach 248 }; 249 250 #define read_iev(sc, reg) \ 251 bus_space_read_2(sc->ievt, sc->ievh, offsetof(struct iembmem, reg)) 252 #define write_iev(sc, reg, val) \ 253 bus_space_write_2(sc->ievt, sc->ievh, offsetof(struct iembmem, reg), val) 254 255 /* 256 * MULTIBUS support routines 257 */ 258 void 259 ie_mbmemreset(sc, what) 260 struct ie_softc *sc; 261 int what; 262 { 263 struct ie_mbmem_softc *vsc = (struct ie_mbmem_softc *)sc; 264 write_iev(vsc, status, IEMBMEM_RESET); 265 delay(100); /* XXX could be shorter? */ 266 write_iev(vsc, status, 0); 267 } 268 269 void 270 ie_mbmemattend(sc, why) 271 struct ie_softc *sc; 272 int why; 273 { 274 struct ie_mbmem_softc *vsc = (struct ie_mbmem_softc *)sc; 275 276 /* flag! */ 277 write_iev(vsc, status, read_iev(vsc, status) | IEMBMEM_ATTEN); 278 /* down. */ 279 write_iev(vsc, status, read_iev(vsc, status) & ~IEMBMEM_ATTEN); 280 } 281 282 void 283 ie_mbmemrun(sc) 284 struct ie_softc *sc; 285 { 286 struct ie_mbmem_softc *vsc = (struct ie_mbmem_softc *)sc; 287 288 write_iev(vsc, status, read_iev(vsc, status) 289 | IEMBMEM_ONAIR | IEMBMEM_IENAB | IEMBMEM_PEINT); 290 } 291 292 int 293 ie_mbmemintr(sc, where) 294 struct ie_softc *sc; 295 int where; 296 { 297 struct ie_mbmem_softc *vsc = (struct ie_mbmem_softc *)sc; 298 299 if (where != INTR_ENTER) 300 return (0); 301 302 /* 303 * check for parity error 304 */ 305 if (read_iev(vsc, status) & IEMBMEM_PERR) { 306 printf("%s: parity error (ctrl 0x%x @ 0x%02x%04x)\n", 307 sc->sc_dev.dv_xname, read_iev(vsc, pectrl), 308 read_iev(vsc, pectrl) & IEMBMEM_HADDR, 309 read_iev(vsc, peaddr)); 310 write_iev(vsc, pectrl, read_iev(vsc, pectrl) | IEMBMEM_PARACK); 311 } 312 return (0); 313 } 314 315 void ie_mbmemcopyin __P((struct ie_softc *, void *, int, size_t)); 316 void ie_mbmemcopyout __P((struct ie_softc *, const void *, int, size_t)); 317 318 /* 319 * Copy board memory to kernel. 320 */ 321 void 322 ie_mbmemcopyin(sc, p, offset, size) 323 struct ie_softc *sc; 324 void *p; 325 int offset; 326 size_t size; 327 { 328 bus_space_copyin(sc->bt, sc->bh, offset, p, size); 329 } 330 331 /* 332 * Copy from kernel space to board memory. 333 */ 334 void 335 ie_mbmemcopyout(sc, p, offset, size) 336 struct ie_softc *sc; 337 const void *p; 338 int offset; 339 size_t size; 340 { 341 bus_space_copyout(sc->bt, sc->bh, offset, p, size); 342 } 343 344 /* read a 16-bit value at BH offset */ 345 u_int16_t ie_mbmem_read16 __P((struct ie_softc *, int offset)); 346 /* write a 16-bit value at BH offset */ 347 void ie_mbmem_write16 __P((struct ie_softc *, int offset, u_int16_t value)); 348 void ie_mbmem_write24 __P((struct ie_softc *, int offset, int addr)); 349 350 u_int16_t 351 ie_mbmem_read16(sc, offset) 352 struct ie_softc *sc; 353 int offset; 354 { 355 u_int16_t v; 356 357 bus_space_barrier(sc->bt, sc->bh, offset, 2, BUS_SPACE_BARRIER_READ); 358 v = bus_space_read_2(sc->bt, sc->bh, offset); 359 return (((v&0xff)<<8) | ((v>>8)&0xff)); 360 } 361 362 void 363 ie_mbmem_write16(sc, offset, v) 364 struct ie_softc *sc; 365 int offset; 366 u_int16_t v; 367 { 368 int v0 = ((((v)&0xff)<<8) | (((v)>>8)&0xff)); 369 bus_space_write_2(sc->bt, sc->bh, offset, v0); 370 bus_space_barrier(sc->bt, sc->bh, offset, 2, BUS_SPACE_BARRIER_WRITE); 371 } 372 373 void 374 ie_mbmem_write24(sc, offset, addr) 375 struct ie_softc *sc; 376 int offset; 377 int addr; 378 { 379 u_char *f = (u_char *)&addr; 380 u_int16_t v0, v1; 381 u_char *t; 382 383 t = (u_char *)&v0; 384 t[0] = f[3]; t[1] = f[2]; 385 bus_space_write_2(sc->bt, sc->bh, offset, v0); 386 387 t = (u_char *)&v1; 388 t[0] = f[1]; t[1] = 0; 389 bus_space_write_2(sc->bt, sc->bh, offset+2, v1); 390 391 bus_space_barrier(sc->bt, sc->bh, offset, 4, BUS_SPACE_BARRIER_WRITE); 392 } 393 394 int 395 ie_mbmem_match(parent, cf, aux) 396 struct device *parent; 397 struct cfdata *cf; 398 void *aux; 399 { 400 struct mbmem_attach_args *mbma = aux; 401 bus_space_handle_t bh; 402 int matched; 403 404 /* No default Multibus address. */ 405 if (mbma->mbma_paddr == -1) 406 return(0); 407 408 /* Make sure there is something there... */ 409 if (bus_space_map(mbma->mbma_bustag, mbma->mbma_paddr, sizeof(struct iembmem), 410 0, &bh)) 411 return (0); 412 matched = (bus_space_peek_2(mbma->mbma_bustag, bh, 0, NULL) == 0); 413 bus_space_unmap(mbma->mbma_bustag, bh, sizeof(struct iembmem)); 414 if (!matched) 415 return (0); 416 417 /* Default interrupt priority. */ 418 if (mbma->mbma_pri == -1) 419 mbma->mbma_pri = 3; 420 421 return (1); 422 } 423 424 void 425 ie_mbmem_attach(parent, self, aux) 426 struct device *parent; 427 struct device *self; 428 void *aux; 429 { 430 u_int8_t myaddr[ETHER_ADDR_LEN]; 431 struct ie_mbmem_softc *vsc = (void *) self; 432 struct mbmem_attach_args *mbma = aux; 433 struct ie_softc *sc; 434 bus_size_t memsize; 435 bus_addr_t rampaddr; 436 int lcv; 437 438 sc = &vsc->ie; 439 440 sc->hwreset = ie_mbmemreset; 441 sc->hwinit = ie_mbmemrun; 442 sc->chan_attn = ie_mbmemattend; 443 sc->intrhook = ie_mbmemintr; 444 sc->memcopyout = ie_mbmemcopyout; 445 sc->memcopyin = ie_mbmemcopyin; 446 447 sc->ie_bus_barrier = NULL; 448 sc->ie_bus_read16 = ie_mbmem_read16; 449 sc->ie_bus_write16 = ie_mbmem_write16; 450 sc->ie_bus_write24 = ie_mbmem_write24; 451 452 /* 453 * There is 64K of memory on the Multibus board. 454 * (determined by hardware - NOT configurable!) 455 */ 456 memsize = 0x10000; /* MEMSIZE 64K */ 457 458 /* Map in the board control regs. */ 459 vsc->ievt = mbma->mbma_bustag; 460 if (bus_space_map(mbma->mbma_bustag, mbma->mbma_paddr, sizeof(struct iembmem), 461 0, &vsc->ievh)) 462 panic("ie_mbmem_attach: can't map regs"); 463 464 /* 465 * Find and map in the board memory. 466 */ 467 /* top 12 bits */ 468 rampaddr = mbma->mbma_paddr & 0xfff00000; 469 /* 4 more */ 470 rampaddr = rampaddr | ((read_iev(vsc, status) & IEMBMEM_HADDR) << 16); 471 sc->bt = mbma->mbma_bustag; 472 if (bus_space_map(mbma->mbma_bustag, rampaddr, memsize, 0, &sc->bh)) 473 panic("ie_mbmem_attach: can't map mem"); 474 475 write_iev(vsc, pectrl, read_iev(vsc, pectrl) | IEMBMEM_PARACK); 476 477 /* 478 * Set up mappings, direct map except for last page 479 * which is mapped at zero and at high address (for scp) 480 */ 481 for (lcv = 0; lcv < IEMBMEM_MAPSZ - 1; lcv++) 482 write_iev(vsc, pgmap[lcv], IEMBMEM_SBORDR | IEMBMEM_OBMEM | lcv); 483 write_iev(vsc, pgmap[IEMBMEM_MAPSZ - 1], IEMBMEM_SBORDR | IEMBMEM_OBMEM | 0); 484 485 /* Clear all ram */ 486 bus_space_set_region_2(sc->bt, sc->bh, 0, 0, memsize/2); 487 488 /* 489 * We use the first page to set up SCP, ICSP and SCB data 490 * structures. The remaining pages become the buffer area 491 * (managed in i82586.c). 492 * SCP is in double-mapped page, so the 586 can see it at 493 * the mandatory magic address (IE_SCP_ADDR). 494 */ 495 sc->scp = (IE_SCP_ADDR & (IEMBMEM_PAGESIZE - 1)); 496 497 /* iscp at location zero */ 498 sc->iscp = 0; 499 500 /* scb follows iscp */ 501 sc->scb = IE_ISCP_SZ; 502 503 ie_mbmem_write16(sc, IE_ISCP_SCB((long)sc->iscp), sc->scb); 504 ie_mbmem_write16(sc, IE_ISCP_BASE((u_long)sc->iscp), 0); 505 ie_mbmem_write24(sc, IE_SCP_ISCP((u_long)sc->scp), 0); 506 507 if (i82586_proberam(sc) == 0) { 508 printf(": memory probe failed\n"); 509 return; 510 } 511 512 /* 513 * Rest of first page is unused; rest of ram for buffers. 514 */ 515 sc->buf_area = IEMBMEM_PAGESIZE; 516 sc->buf_area_sz = memsize - IEMBMEM_PAGESIZE; 517 518 sc->do_xmitnopchain = 0; 519 520 printf("\n%s:", self->dv_xname); 521 522 /* Set the ethernet address. */ 523 idprom_etheraddr(myaddr); 524 525 i82586_attach(sc, "multibus", myaddr, media, NMEDIA, media[0]); 526 527 bus_intr_establish(mbma->mbma_bustag, mbma->mbma_pri, IPL_NET, 0, 528 i82586_intr, sc); 529 } 530