1 /* $NetBSD: cg4.c,v 1.29 2002/10/23 09:12:25 jdolecek Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. All advertising materials mentioning features or use of this software 25 * must display the following acknowledgement: 26 * This product includes software developed by the University of 27 * California, Berkeley and its contributors. 28 * 4. Neither the name of the University nor the names of its contributors 29 * may be used to endorse or promote products derived from this software 30 * without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 35 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 38 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 39 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 40 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 41 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 42 * SUCH DAMAGE. 43 * 44 * from: @(#)cgthree.c 8.2 (Berkeley) 10/30/93 45 */ 46 47 /* 48 * color display (cg4) driver. 49 * 50 * Credits, history: 51 * Gordon Ross created this driver based on the cg3 driver from 52 * the sparc port as distributed in BSD 4.4 Lite, but included 53 * support for only the "type B" adapter (Brooktree DACs). 54 * Ezra Story added support for the "type A" (AMD DACs). 55 * 56 * Todo: 57 * Make this driver handle video interrupts. 58 * Defer colormap updates to vertical retrace interrupts. 59 */ 60 61 #include <sys/param.h> 62 #include <sys/systm.h> 63 #include <sys/conf.h> 64 #include <sys/device.h> 65 #include <sys/ioctl.h> 66 #include <sys/malloc.h> 67 #include <sys/mman.h> 68 #include <sys/proc.h> 69 #include <sys/tty.h> 70 71 #include <uvm/uvm_extern.h> 72 73 #include <machine/autoconf.h> 74 #include <machine/cpu.h> 75 #include <dev/sun/fbio.h> 76 #include <machine/idprom.h> 77 #include <machine/pmap.h> 78 79 #include <sun3/dev/fbvar.h> 80 #include <sun3/dev/btreg.h> 81 #include <sun3/dev/cg4reg.h> 82 #include <sun3/dev/p4reg.h> 83 84 union bt_cmap_u { 85 u_char btcm_char[256 * 3]; /* raw data */ 86 u_char btcm_rgb[256][3]; /* 256 R/G/B entries */ 87 u_int btcm_int[256 * 3 / 4]; /* the way the chip gets loaded */ 88 }; 89 90 #define CG4_TYPE_A 0 /* AMD DACs */ 91 #define CG4_TYPE_B 1 /* Brooktree DACs */ 92 93 #define CG4_MMAP_SIZE (CG4_OVERLAY_SIZE + CG4_ENABLE_SIZE + CG4_PIXMAP_SIZE) 94 95 #define CMAP_SIZE 256 96 struct soft_cmap { 97 u_char r[CMAP_SIZE]; 98 u_char g[CMAP_SIZE]; 99 u_char b[CMAP_SIZE]; 100 }; 101 102 /* per-display variables */ 103 struct cg4_softc { 104 struct device sc_dev; /* base device */ 105 struct fbdevice sc_fb; /* frame buffer device */ 106 int sc_cg4type; /* A or B */ 107 int sc_pa_overlay; /* phys. addr. of overlay plane */ 108 int sc_pa_enable; /* phys. addr. of enable plane */ 109 int sc_pa_pixmap; /* phys. addr. of color plane */ 110 int sc_video_on; /* zero if blanked */ 111 void *sc_va_cmap; /* Colormap h/w (mapped KVA) */ 112 void *sc_btcm; /* Soft cmap, Brooktree format */ 113 void (*sc_ldcmap) __P((struct cg4_softc *)); 114 struct soft_cmap sc_cmap; /* Soft cmap, user format */ 115 }; 116 117 /* autoconfiguration driver */ 118 static void cg4attach __P((struct device *, struct device *, void *)); 119 static int cg4match __P((struct device *, struct cfdata *, void *)); 120 121 CFATTACH_DECL(cgfour, sizeof(struct cg4_softc), 122 cg4match, cg4attach, NULL, NULL); 123 124 extern struct cfdriver cgfour_cd; 125 126 dev_type_open(cg4open); 127 dev_type_ioctl(cg4ioctl); 128 dev_type_mmap(cg4mmap); 129 130 const struct cdevsw cgfour_cdevsw = { 131 cg4open, nullclose, noread, nowrite, cg4ioctl, 132 nostop, notty, nopoll, cg4mmap, nokqfilter, 133 }; 134 135 static int cg4gattr __P((struct fbdevice *, void *)); 136 static int cg4gvideo __P((struct fbdevice *, void *)); 137 static int cg4svideo __P((struct fbdevice *, void *)); 138 static int cg4getcmap __P((struct fbdevice *, void *)); 139 static int cg4putcmap __P((struct fbdevice *, void *)); 140 141 #ifdef _SUN3_ 142 static void cg4a_init __P((struct cg4_softc *)); 143 static void cg4a_ldcmap __P((struct cg4_softc *)); 144 #endif /* SUN3 */ 145 146 static void cg4b_init __P((struct cg4_softc *)); 147 static void cg4b_ldcmap __P((struct cg4_softc *)); 148 149 static struct fbdriver cg4_fbdriver = { 150 cg4open, nullclose, cg4mmap, nokqfilter, cg4gattr, 151 cg4gvideo, cg4svideo, 152 cg4getcmap, cg4putcmap }; 153 154 /* 155 * Match a cg4. 156 */ 157 static int 158 cg4match(parent, cf, args) 159 struct device *parent; 160 struct cfdata *cf; 161 void *args; 162 { 163 struct confargs *ca = args; 164 int mid, p4id, peekval, tmp; 165 void *p4reg; 166 167 /* No default address support. */ 168 if (ca->ca_paddr == -1) 169 return (0); 170 171 /* 172 * Slight hack here: The low four bits of the 173 * config flags, if set, restrict the match to 174 * that machine "implementation" only. 175 */ 176 mid = cf->cf_flags & IDM_IMPL_MASK; 177 if (mid && (mid != (cpu_machine_id & IDM_IMPL_MASK))) 178 return (0); 179 180 /* 181 * The config flag 0x10 if set means we are 182 * looking for a Type A board (3/110). 183 */ 184 if (cf->cf_flags & 0x10) { 185 #ifdef _SUN3_ 186 /* Type A: Check for AMD RAMDACs in control space. */ 187 if (bus_peek(BUS_OBIO, CG4A_OBIO_CMAP, 1) == -1) 188 return (0); 189 /* Check for the overlay plane. */ 190 tmp = ca->ca_paddr + CG4A_OFF_OVERLAY; 191 if (bus_peek(ca->ca_bustype, tmp, 1) == -1) 192 return (0); 193 /* OK, it looks like a Type A. */ 194 return (1); 195 #else /* SUN3 */ 196 /* Only the Sun3/110 ever has a type A. */ 197 return (0); 198 #endif /* SUN3 */ 199 } 200 201 /* 202 * From here on, it is a type B or nothing. 203 * The config flag 0x20 if set means there 204 * is no P4 register. (bus error) 205 */ 206 if ((cf->cf_flags & 0x20) == 0) { 207 p4reg = bus_tmapin(ca->ca_bustype, ca->ca_paddr); 208 peekval = peek_long(p4reg); 209 p4id = (peekval == -1) ? 210 P4_NOTFOUND : fb_pfour_id(p4reg); 211 bus_tmapout(p4reg); 212 if (peekval == -1) 213 return (0); 214 if (p4id != P4_ID_COLOR8P1) { 215 #ifdef DEBUG 216 printf("cgfour at 0x%x match p4id=0x%x fails\n", 217 ca->ca_paddr, p4id & 0xFF); 218 #endif 219 return (0); 220 } 221 } 222 223 /* 224 * Check for CMAP hardware and overlay plane. 225 */ 226 tmp = ca->ca_paddr + CG4B_OFF_CMAP; 227 if (bus_peek(ca->ca_bustype, tmp, 4) == -1) 228 return (0); 229 tmp = ca->ca_paddr + CG4B_OFF_OVERLAY; 230 if (bus_peek(ca->ca_bustype, tmp, 1) == -1) 231 return (0); 232 233 return (1); 234 } 235 236 /* 237 * Attach a display. We need to notice if it is the console, too. 238 */ 239 static void 240 cg4attach(parent, self, args) 241 struct device *parent, *self; 242 void *args; 243 { 244 struct cg4_softc *sc = (struct cg4_softc *)self; 245 struct fbdevice *fb = &sc->sc_fb; 246 struct confargs *ca = args; 247 struct fbtype *fbt; 248 int tmp; 249 250 fbt = &fb->fb_fbtype; 251 fbt->fb_type = FBTYPE_SUN4COLOR; 252 fbt->fb_width = 1152; /* default - see below */ 253 fbt->fb_height = 900; /* default - see below */ 254 fbt->fb_depth = 8; 255 fbt->fb_cmsize = 256; 256 fbt->fb_size = CG4_MMAP_SIZE; 257 fb->fb_driver = &cg4_fbdriver; 258 fb->fb_private = sc; 259 fb->fb_name = sc->sc_dev.dv_xname; 260 fb->fb_flags = sc->sc_dev.dv_cfdata->cf_flags; 261 262 /* 263 * The config flag 0x10 if set means we are 264 * attaching a Type A (3/110) which has the 265 * AMD RAMDACs in control space, and no P4. 266 */ 267 if (fb->fb_flags & 0x10) { 268 #ifdef _SUN3_ 269 sc->sc_cg4type = CG4_TYPE_A; 270 sc->sc_ldcmap = cg4a_ldcmap; 271 sc->sc_pa_overlay = ca->ca_paddr + CG4A_OFF_OVERLAY; 272 sc->sc_pa_enable = ca->ca_paddr + CG4A_OFF_ENABLE; 273 sc->sc_pa_pixmap = ca->ca_paddr + CG4A_OFF_PIXMAP; 274 sc->sc_va_cmap = bus_mapin(BUS_OBIO, CG4A_OBIO_CMAP, 275 sizeof(struct amd_regs)); 276 cg4a_init(sc); 277 #else /* SUN3 */ 278 panic("cgfour flags 0x10"); 279 #endif /* SUN3 */ 280 } else { 281 sc->sc_cg4type = CG4_TYPE_B; 282 sc->sc_ldcmap = cg4b_ldcmap; 283 sc->sc_pa_overlay = ca->ca_paddr + CG4B_OFF_OVERLAY; 284 sc->sc_pa_enable = ca->ca_paddr + CG4B_OFF_ENABLE; 285 sc->sc_pa_pixmap = ca->ca_paddr + CG4B_OFF_PIXMAP; 286 tmp = ca->ca_paddr + CG4B_OFF_CMAP; 287 sc->sc_va_cmap = bus_mapin(ca->ca_bustype, tmp, 288 sizeof(struct bt_regs)); 289 cg4b_init(sc); 290 } 291 292 if ((fb->fb_flags & 0x20) == 0) { 293 /* It is supposed to have a P4 register. */ 294 fb->fb_pfour = bus_mapin(ca->ca_bustype, ca->ca_paddr, 4); 295 } 296 297 /* 298 * Determine width and height as follows: 299 * If it has a P4 register, use that; 300 * else if unit==0, use the EEPROM size, 301 * else make our best guess. 302 */ 303 if (fb->fb_pfour) 304 fb_pfour_setsize(fb); 305 else if (sc->sc_dev.dv_unit == 0) 306 fb_eeprom_setsize(fb); 307 else { 308 /* Guess based on machine ID. */ 309 switch (cpu_machine_id) { 310 default: 311 /* Leave the defaults set above. */ 312 break; 313 } 314 } 315 printf(" (%dx%d)\n", fbt->fb_width, fbt->fb_height); 316 317 /* 318 * Make sure video is on. This driver uses a 319 * black colormap to blank the screen, so if 320 * there is any global enable, set it here. 321 */ 322 tmp = 1; 323 cg4svideo(fb, &tmp); 324 if (fb->fb_pfour) 325 fb_pfour_set_video(fb, 1); 326 else 327 enable_video(1); 328 329 /* Let /dev/fb know we are here. */ 330 fb_attach(fb, 4); 331 } 332 333 int 334 cg4open(dev, flags, mode, p) 335 dev_t dev; 336 int flags, mode; 337 struct proc *p; 338 { 339 int unit = minor(dev); 340 341 if (unit >= cgfour_cd.cd_ndevs || cgfour_cd.cd_devs[unit] == NULL) 342 return (ENXIO); 343 return (0); 344 } 345 346 int 347 cg4ioctl(dev, cmd, data, flags, p) 348 dev_t dev; 349 u_long cmd; 350 caddr_t data; 351 int flags; 352 struct proc *p; 353 { 354 struct cg4_softc *sc = cgfour_cd.cd_devs[minor(dev)]; 355 356 return (fbioctlfb(&sc->sc_fb, cmd, data)); 357 } 358 359 /* 360 * Return the address that would map the given device at the given 361 * offset, allowing for the given protection, or return -1 for error. 362 * 363 * X11 expects its mmap'd region to look like this: 364 * 128k overlay data memory 365 * 128k overlay enable bitmap 366 * 1024k color memory 367 * 368 * The hardware looks completely different. 369 */ 370 paddr_t 371 cg4mmap(dev, off, prot) 372 dev_t dev; 373 off_t off; 374 int prot; 375 { 376 struct cg4_softc *sc = cgfour_cd.cd_devs[minor(dev)]; 377 int physbase; 378 379 if (off & PGOFSET) 380 panic("cg4mmap"); 381 382 if ((off < 0) || (off >= CG4_MMAP_SIZE)) 383 return (-1); 384 385 if (off < 0x40000) { 386 if (off < 0x20000) { 387 physbase = sc->sc_pa_overlay; 388 } else { 389 /* enable plane */ 390 off -= 0x20000; 391 physbase = sc->sc_pa_enable; 392 } 393 } else { 394 /* pixel map */ 395 off -= 0x40000; 396 physbase = sc->sc_pa_pixmap; 397 } 398 399 /* 400 * I turned on PMAP_NC here to disable the cache as I was 401 * getting horribly broken behaviour without it. 402 */ 403 return ((physbase + off) | PMAP_NC); 404 } 405 406 /* 407 * Internal ioctl functions. 408 */ 409 410 /* FBIOGATTR: */ 411 static int cg4gattr(fb, data) 412 struct fbdevice *fb; 413 void *data; 414 { 415 struct fbgattr *fba = data; 416 417 fba->real_type = fb->fb_fbtype.fb_type; 418 fba->owner = 0; /* XXX - TIOCCONS stuff? */ 419 fba->fbtype = fb->fb_fbtype; 420 fba->sattr.flags = 0; 421 fba->sattr.emu_type = fb->fb_fbtype.fb_type; 422 fba->sattr.dev_specific[0] = -1; 423 fba->emu_types[0] = fb->fb_fbtype.fb_type; 424 fba->emu_types[1] = -1; 425 return (0); 426 } 427 428 /* FBIOGVIDEO: */ 429 static int cg4gvideo(fb, data) 430 struct fbdevice *fb; 431 void *data; 432 { 433 struct cg4_softc *sc = fb->fb_private; 434 int *on = data; 435 436 *on = sc->sc_video_on; 437 return (0); 438 } 439 440 /* FBIOSVIDEO: */ 441 static int cg4svideo(fb, data) 442 struct fbdevice *fb; 443 void *data; 444 { 445 struct cg4_softc *sc = fb->fb_private; 446 int *on = data; 447 448 if (sc->sc_video_on == *on) 449 return (0); 450 sc->sc_video_on = *on; 451 452 (*sc->sc_ldcmap)(sc); 453 return (0); 454 } 455 456 /* 457 * FBIOGETCMAP: 458 * Copy current colormap out to user space. 459 */ 460 static int cg4getcmap(fb, data) 461 struct fbdevice *fb; 462 void *data; 463 { 464 struct cg4_softc *sc = fb->fb_private; 465 struct soft_cmap *cm = &sc->sc_cmap; 466 struct fbcmap *fbcm = data; 467 u_int start, count; 468 int error; 469 470 start = fbcm->index; 471 count = fbcm->count; 472 if (start >= CMAP_SIZE || count > CMAP_SIZE - start) 473 return (EINVAL); 474 475 if ((error = copyout(&cm->r[start], fbcm->red, count)) != 0) 476 return (error); 477 478 if ((error = copyout(&cm->g[start], fbcm->green, count)) != 0) 479 return (error); 480 481 if ((error = copyout(&cm->b[start], fbcm->blue, count)) != 0) 482 return (error); 483 484 return (0); 485 } 486 487 /* 488 * FBIOPUTCMAP: 489 * Copy new colormap from user space and load. 490 */ 491 static int cg4putcmap(fb, data) 492 struct fbdevice *fb; 493 void *data; 494 { 495 struct cg4_softc *sc = fb->fb_private; 496 struct soft_cmap *cm = &sc->sc_cmap; 497 struct fbcmap *fbcm = data; 498 u_int start, count; 499 int error; 500 501 start = fbcm->index; 502 count = fbcm->count; 503 if (start >= CMAP_SIZE || count > CMAP_SIZE - start) 504 return (EINVAL); 505 506 if ((error = copyin(fbcm->red, &cm->r[start], count)) != 0) 507 return (error); 508 509 if ((error = copyin(fbcm->green, &cm->g[start], count)) != 0) 510 return (error); 511 512 if ((error = copyin(fbcm->blue, &cm->b[start], count)) != 0) 513 return (error); 514 515 (*sc->sc_ldcmap)(sc); 516 return (0); 517 } 518 519 /**************************************************************** 520 * Routines for the "Type A" hardware 521 ****************************************************************/ 522 #ifdef _SUN3_ 523 524 static void 525 cg4a_init(sc) 526 struct cg4_softc *sc; 527 { 528 volatile struct amd_regs *ar = sc->sc_va_cmap; 529 struct soft_cmap *cm = &sc->sc_cmap; 530 int i; 531 532 /* Grab initial (current) color map. */ 533 for(i = 0; i < 256; i++) { 534 cm->r[i] = ar->r[i]; 535 cm->g[i] = ar->g[i]; 536 cm->b[i] = ar->b[i]; 537 } 538 } 539 540 static void 541 cg4a_ldcmap(sc) 542 struct cg4_softc *sc; 543 { 544 volatile struct amd_regs *ar = sc->sc_va_cmap; 545 struct soft_cmap *cm = &sc->sc_cmap; 546 int i; 547 548 /* 549 * Now blast them into the chip! 550 * XXX Should use retrace interrupt! 551 * Just set a "need load" bit and let the 552 * retrace interrupt handler do the work. 553 */ 554 if (sc->sc_video_on) { 555 /* Update H/W colormap. */ 556 for (i = 0; i < 256; i++) { 557 ar->r[i] = cm->r[i]; 558 ar->g[i] = cm->g[i]; 559 ar->b[i] = cm->b[i]; 560 } 561 } else { 562 /* Clear H/W colormap. */ 563 for (i = 0; i < 256; i++) { 564 ar->r[i] = 0; 565 ar->g[i] = 0; 566 ar->b[i] = 0; 567 } 568 } 569 } 570 #endif /* SUN3 */ 571 572 /**************************************************************** 573 * Routines for the "Type B" hardware 574 ****************************************************************/ 575 576 static void 577 cg4b_init(sc) 578 struct cg4_softc *sc; 579 { 580 volatile struct bt_regs *bt = sc->sc_va_cmap; 581 struct soft_cmap *cm = &sc->sc_cmap; 582 union bt_cmap_u *btcm; 583 int i; 584 585 /* Need a buffer for colormap format translation. */ 586 btcm = malloc(sizeof(*btcm), M_DEVBUF, M_WAITOK); 587 sc->sc_btcm = btcm; 588 589 /* 590 * BT458 chip initialization as described in Brooktree's 591 * 1993 Graphics and Imaging Product Databook (DB004-1/93). 592 * 593 * It appears that the 3/60 uses the low byte, and the 3/80 594 * uses the high byte, while both ignore the other bytes. 595 * Writing same value to all bytes works on both. 596 */ 597 bt->bt_addr = 0x04040404; /* select read mask register */ 598 bt->bt_ctrl = ~0; /* all planes on */ 599 bt->bt_addr = 0x05050505; /* select blink mask register */ 600 bt->bt_ctrl = 0; /* all planes non-blinking */ 601 bt->bt_addr = 0x06060606; /* select command register */ 602 bt->bt_ctrl = 0x43434343; /* palette enabled, overlay planes enabled */ 603 bt->bt_addr = 0x07070707; /* select test register */ 604 bt->bt_ctrl = 0; /* not test mode */ 605 606 /* grab initial (current) color map */ 607 bt->bt_addr = 0; 608 #ifdef _SUN3_ 609 /* Sun3/60 wants 32-bit access, packed. */ 610 for (i = 0; i < (256 * 3 / 4); i++) 611 btcm->btcm_int[i] = bt->bt_cmap; 612 #else /* SUN3 */ 613 /* Sun3/80 wants 8-bits in the high byte. */ 614 for (i = 0; i < (256 * 3); i++) 615 btcm->btcm_char[i] = bt->bt_cmap >> 24; 616 #endif /* SUN3 */ 617 618 /* Transpose into H/W cmap into S/W form. */ 619 for (i = 0; i < 256; i++) { 620 cm->r[i] = btcm->btcm_rgb[i][0]; 621 cm->g[i] = btcm->btcm_rgb[i][1]; 622 cm->b[i] = btcm->btcm_rgb[i][2]; 623 } 624 } 625 626 static void 627 cg4b_ldcmap(sc) 628 struct cg4_softc *sc; 629 { 630 volatile struct bt_regs *bt = sc->sc_va_cmap; 631 struct soft_cmap *cm = &sc->sc_cmap; 632 union bt_cmap_u *btcm = sc->sc_btcm; 633 int i; 634 635 /* Transpose S/W cmap into H/W form. */ 636 for (i = 0; i < 256; i++) { 637 btcm->btcm_rgb[i][0] = cm->r[i]; 638 btcm->btcm_rgb[i][1] = cm->g[i]; 639 btcm->btcm_rgb[i][2] = cm->b[i]; 640 } 641 642 /* 643 * Now blast them into the chip! 644 * XXX Should use retrace interrupt! 645 * Just set a "need load" bit and let the 646 * retrace interrupt handler do the work. 647 */ 648 bt->bt_addr = 0; 649 650 #ifdef _SUN3_ 651 /* Sun3/60 wants 32-bit access, packed. */ 652 if (sc->sc_video_on) { 653 /* Update H/W colormap. */ 654 for (i = 0; i < (256 * 3 / 4); i++) 655 bt->bt_cmap = btcm->btcm_int[i]; 656 } else { 657 /* Clear H/W colormap. */ 658 for (i = 0; i < (256 * 3 / 4); i++) 659 bt->bt_cmap = 0; 660 } 661 #else /* SUN3 */ 662 /* Sun3/80 wants 8-bits in the high byte. */ 663 if (sc->sc_video_on) { 664 /* Update H/W colormap. */ 665 for (i = 0; i < (256 * 3); i++) 666 bt->bt_cmap = btcm->btcm_char[i] << 24; 667 } else { 668 /* Clear H/W colormap. */ 669 for (i = 0; i < (256 * 3); i++) 670 bt->bt_cmap = 0; 671 } 672 #endif /* SUN3 */ 673 } 674 675