1 /* $NetBSD: esp.c,v 1.14 2001/04/25 17:53:24 bouyer Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jeremy Cooper and Gordon W. Ross 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * "Front end" glue for the ncr53c9x chip, formerly known as the 41 * Emulex SCSI Processor (ESP) which is what we actually have. 42 */ 43 44 #include <sys/types.h> 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/kernel.h> 48 #include <sys/errno.h> 49 #include <sys/device.h> 50 #include <sys/buf.h> 51 52 #include <dev/scsipi/scsi_all.h> 53 #include <dev/scsipi/scsipi_all.h> 54 #include <dev/scsipi/scsiconf.h> 55 #include <dev/scsipi/scsi_message.h> 56 57 #include <machine/autoconf.h> 58 59 #include <dev/ic/ncr53c9xreg.h> 60 #include <dev/ic/ncr53c9xvar.h> 61 62 #include <sun3/dev/dmareg.h> 63 #include <sun3/dev/dmavar.h> 64 65 #define ESP_REG_SIZE (12*4) 66 67 struct esp_softc { 68 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 69 volatile u_char *sc_reg; /* the registers */ 70 struct dma_softc *sc_dma; /* pointer to my dma */ 71 }; 72 73 static int espmatch __P((struct device *, struct cfdata *, void *)); 74 static void espattach __P((struct device *, struct device *, void *)); 75 76 struct cfattach esp_ca = { 77 sizeof(struct esp_softc), espmatch, espattach 78 }; 79 80 /* 81 * Functions and the switch for the MI code. 82 */ 83 static u_char esp_read_reg __P((struct ncr53c9x_softc *, int)); 84 static void esp_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 85 static int esp_dma_isintr __P((struct ncr53c9x_softc *)); 86 static void esp_dma_reset __P((struct ncr53c9x_softc *)); 87 static int esp_dma_intr __P((struct ncr53c9x_softc *)); 88 static int esp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 89 size_t *, int, size_t *)); 90 static void esp_dma_go __P((struct ncr53c9x_softc *)); 91 static void esp_dma_stop __P((struct ncr53c9x_softc *)); 92 static int esp_dma_isactive __P((struct ncr53c9x_softc *)); 93 94 static struct ncr53c9x_glue esp_glue = { 95 esp_read_reg, 96 esp_write_reg, 97 esp_dma_isintr, 98 esp_dma_reset, 99 esp_dma_intr, 100 esp_dma_setup, 101 esp_dma_go, 102 esp_dma_stop, 103 esp_dma_isactive, 104 NULL, /* gl_clear_latched_intr */ 105 }; 106 107 static int 108 espmatch(parent, cf, aux) 109 struct device *parent; 110 struct cfdata *cf; 111 void *aux; 112 { 113 struct confargs *ca = aux; 114 115 /* 116 * Check for the esp registers. 117 */ 118 if (bus_peek(ca->ca_bustype, 119 ca->ca_paddr + (NCR_STAT * 4), 1) == -1) 120 return (0); 121 122 /* If default ipl, fill it in. */ 123 if (ca->ca_intpri == -1) 124 ca->ca_intpri = 2; 125 126 return (1); 127 } 128 129 static void 130 espattach(parent, self, aux) 131 struct device *parent, *self; 132 void *aux; 133 { 134 struct confargs *ca = aux; 135 struct esp_softc *esc = (void *)self; 136 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 137 138 /* 139 * Set up glue for MI code early; we use some of it here. 140 */ 141 sc->sc_glue = &esp_glue; 142 143 /* 144 * Map in the ESP registers. 145 */ 146 esc->sc_reg = 147 bus_mapin(ca->ca_bustype, ca->ca_paddr, ESP_REG_SIZE); 148 149 /* Other settings */ 150 sc->sc_id = 7; 151 sc->sc_freq = 20; /* The 3/80 esp runs at 20 Mhz */ 152 153 /* 154 * Hook up the DMA driver. 155 */ 156 esc->sc_dma = espdmafind(sc->sc_dev.dv_unit); 157 esc->sc_dma->sc_esp = sc; /* Point back to us */ 158 159 /* 160 * XXX More of this should be in ncr53c9x_attach(), but 161 * XXX should we really poke around the chip that much in 162 * XXX the MI code? Think about this more... 163 */ 164 165 /* 166 * It is necessary to try to load the 2nd config register here, 167 * to find out what rev the esp chip is, else the ncr53c9x_reset 168 * will not set up the defaults correctly. 169 */ 170 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 171 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE; 172 sc->sc_cfg3 = NCRCFG3_CDB; 173 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 174 175 if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) != 176 (NCRCFG2_SCSI2 | NCRCFG2_RPE)) { 177 sc->sc_rev = NCR_VARIANT_ESP100; 178 } else { 179 sc->sc_cfg2 = NCRCFG2_SCSI2; 180 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 181 sc->sc_cfg3 = 0; 182 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 183 sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK); 184 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 185 if (NCR_READ_REG(sc, NCR_CFG3) != 186 (NCRCFG3_CDB | NCRCFG3_FCLK)) { 187 sc->sc_rev = NCR_VARIANT_ESP100A; 188 } else { 189 /* NCRCFG2_FE enables > 64K transfers */ 190 sc->sc_cfg2 |= NCRCFG2_FE; 191 sc->sc_cfg3 = 0; 192 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 193 sc->sc_rev = NCR_VARIANT_ESP200; 194 } 195 } 196 197 /* 198 * XXX minsync and maxxfer _should_ be set up in MI code, 199 * XXX but it appears to have some dependency on what sort 200 * XXX of DMA we're hooked up to, etc. 201 */ 202 203 /* 204 * This is the value used to start sync negotiations 205 * Note that the NCR register "SYNCTP" is programmed 206 * in "clocks per byte", and has a minimum value of 4. 207 * The SCSI period used in negotiation is one-fourth 208 * of the time (in nanoseconds) needed to transfer one byte. 209 * Since the chip's clock is given in MHz, we have the following 210 * formula: 4 * period = (1000 / freq) * 4 211 */ 212 sc->sc_minsync = 1000 / sc->sc_freq; 213 214 /* 215 * Alas, we must now modify the value a bit, because it's 216 * only valid when can switch on FASTCLK and FASTSCSI bits 217 * in config register 3... 218 */ 219 switch (sc->sc_rev) { 220 case NCR_VARIANT_ESP100: 221 sc->sc_maxxfer = 64 * 1024; 222 sc->sc_minsync = 0; /* No synch on old chip? */ 223 break; 224 225 case NCR_VARIANT_ESP100A: 226 sc->sc_maxxfer = 64 * 1024; 227 /* Min clocks/byte is 5 */ 228 sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5); 229 break; 230 231 case NCR_VARIANT_ESP200: 232 sc->sc_maxxfer = 16 * 1024 * 1024; 233 /* XXX - do actually set FAST* bits */ 234 break; 235 } 236 237 /* and the interuppts */ 238 isr_add_autovect(ncr53c9x_intr, sc, ca->ca_intpri); 239 evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, NULL, 240 sc->sc_dev.dv_xname, "intr"); 241 242 /* Do the common parts of attachment. */ 243 sc->sc_adapter.adapt_minphys = minphys; 244 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 245 ncr53c9x_attach(sc); 246 247 #if 0 248 /* XXX - This doesn't work yet. Not sure why... */ 249 /* Turn on target selection using the `dma' method */ 250 sc->sc_features |= NCR_F_DMASELECT; /* XXX - OK? */ 251 #endif 252 } 253 254 255 /* 256 * Glue functions. 257 */ 258 259 u_char 260 esp_read_reg(sc, reg) 261 struct ncr53c9x_softc *sc; 262 int reg; 263 { 264 struct esp_softc *esc = (struct esp_softc *)sc; 265 266 return (esc->sc_reg[reg * 4]); 267 } 268 269 void 270 esp_write_reg(sc, reg, val) 271 struct ncr53c9x_softc *sc; 272 int reg; 273 u_char val; 274 { 275 struct esp_softc *esc = (struct esp_softc *)sc; 276 277 esc->sc_reg[reg * 4] = val; 278 } 279 280 int 281 esp_dma_isintr(sc) 282 struct ncr53c9x_softc *sc; 283 { 284 struct esp_softc *esc = (struct esp_softc *)sc; 285 u_int32_t csr; 286 287 csr = DMACSR(esc->sc_dma); 288 return (csr & (D_INT_PEND|D_ERR_PEND)); 289 } 290 291 void 292 esp_dma_reset(sc) 293 struct ncr53c9x_softc *sc; 294 { 295 struct esp_softc *esc = (struct esp_softc *)sc; 296 297 dma_reset(esc->sc_dma); 298 } 299 300 int 301 esp_dma_intr(sc) 302 struct ncr53c9x_softc *sc; 303 { 304 struct esp_softc *esc = (struct esp_softc *)sc; 305 306 return (espdmaintr(esc->sc_dma)); 307 } 308 309 int 310 esp_dma_setup(sc, addr, len, datain, dmasize) 311 struct ncr53c9x_softc *sc; 312 caddr_t *addr; 313 size_t *len; 314 int datain; 315 size_t *dmasize; 316 { 317 struct esp_softc *esc = (struct esp_softc *)sc; 318 319 return (dma_setup(esc->sc_dma, addr, len, datain, dmasize)); 320 } 321 322 void 323 esp_dma_go(sc) 324 struct ncr53c9x_softc *sc; 325 { 326 struct esp_softc *esc = (struct esp_softc *)sc; 327 328 /* Start DMA */ 329 DMACSR(esc->sc_dma) |= D_EN_DMA; 330 esc->sc_dma->sc_active = 1; 331 } 332 333 void 334 esp_dma_stop(sc) 335 struct ncr53c9x_softc *sc; 336 { 337 struct esp_softc *esc = (struct esp_softc *)sc; 338 339 DMACSR(esc->sc_dma) &= ~D_EN_DMA; 340 } 341 342 int 343 esp_dma_isactive(sc) 344 struct ncr53c9x_softc *sc; 345 { 346 struct esp_softc *esc = (struct esp_softc *)sc; 347 348 return (esc->sc_dma->sc_active); 349 } 350