1 /* $NetBSD: esp.c,v 1.17 2002/10/02 16:02:25 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jeremy Cooper and Gordon W. Ross 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * "Front end" glue for the ncr53c9x chip, formerly known as the 41 * Emulex SCSI Processor (ESP) which is what we actually have. 42 */ 43 44 #include <sys/types.h> 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/kernel.h> 48 #include <sys/errno.h> 49 #include <sys/device.h> 50 #include <sys/buf.h> 51 52 #include <dev/scsipi/scsi_all.h> 53 #include <dev/scsipi/scsipi_all.h> 54 #include <dev/scsipi/scsiconf.h> 55 #include <dev/scsipi/scsi_message.h> 56 57 #include <machine/autoconf.h> 58 59 #include <dev/ic/ncr53c9xreg.h> 60 #include <dev/ic/ncr53c9xvar.h> 61 62 #include <sun3/dev/dmareg.h> 63 #include <sun3/dev/dmavar.h> 64 65 #define ESP_REG_SIZE (12*4) 66 67 struct esp_softc { 68 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 69 volatile u_char *sc_reg; /* the registers */ 70 struct dma_softc *sc_dma; /* pointer to my dma */ 71 }; 72 73 static int espmatch __P((struct device *, struct cfdata *, void *)); 74 static void espattach __P((struct device *, struct device *, void *)); 75 76 CFATTACH_DECL(esp, sizeof(struct esp_softc), 77 espmatch, espattach, NULL, NULL); 78 79 /* 80 * Functions and the switch for the MI code. 81 */ 82 static u_char esp_read_reg __P((struct ncr53c9x_softc *, int)); 83 static void esp_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 84 static int esp_dma_isintr __P((struct ncr53c9x_softc *)); 85 static void esp_dma_reset __P((struct ncr53c9x_softc *)); 86 static int esp_dma_intr __P((struct ncr53c9x_softc *)); 87 static int esp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 88 size_t *, int, size_t *)); 89 static void esp_dma_go __P((struct ncr53c9x_softc *)); 90 static void esp_dma_stop __P((struct ncr53c9x_softc *)); 91 static int esp_dma_isactive __P((struct ncr53c9x_softc *)); 92 93 static struct ncr53c9x_glue esp_glue = { 94 esp_read_reg, 95 esp_write_reg, 96 esp_dma_isintr, 97 esp_dma_reset, 98 esp_dma_intr, 99 esp_dma_setup, 100 esp_dma_go, 101 esp_dma_stop, 102 esp_dma_isactive, 103 NULL, /* gl_clear_latched_intr */ 104 }; 105 106 static int 107 espmatch(parent, cf, aux) 108 struct device *parent; 109 struct cfdata *cf; 110 void *aux; 111 { 112 struct confargs *ca = aux; 113 114 /* 115 * Check for the esp registers. 116 */ 117 if (bus_peek(ca->ca_bustype, 118 ca->ca_paddr + (NCR_STAT * 4), 1) == -1) 119 return (0); 120 121 /* If default ipl, fill it in. */ 122 if (ca->ca_intpri == -1) 123 ca->ca_intpri = 2; 124 125 return (1); 126 } 127 128 static void 129 espattach(parent, self, aux) 130 struct device *parent, *self; 131 void *aux; 132 { 133 struct confargs *ca = aux; 134 struct esp_softc *esc = (void *)self; 135 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 136 137 /* 138 * Set up glue for MI code early; we use some of it here. 139 */ 140 sc->sc_glue = &esp_glue; 141 142 /* 143 * Map in the ESP registers. 144 */ 145 esc->sc_reg = 146 bus_mapin(ca->ca_bustype, ca->ca_paddr, ESP_REG_SIZE); 147 148 /* Other settings */ 149 sc->sc_id = 7; 150 sc->sc_freq = 20; /* The 3/80 esp runs at 20 Mhz */ 151 152 /* 153 * Hook up the DMA driver. 154 */ 155 esc->sc_dma = espdmafind(sc->sc_dev.dv_unit); 156 esc->sc_dma->sc_esp = sc; /* Point back to us */ 157 158 /* 159 * XXX More of this should be in ncr53c9x_attach(), but 160 * XXX should we really poke around the chip that much in 161 * XXX the MI code? Think about this more... 162 */ 163 164 /* 165 * It is necessary to try to load the 2nd config register here, 166 * to find out what rev the esp chip is, else the ncr53c9x_reset 167 * will not set up the defaults correctly. 168 */ 169 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 170 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE; 171 sc->sc_cfg3 = NCRCFG3_CDB; 172 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 173 174 if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) != 175 (NCRCFG2_SCSI2 | NCRCFG2_RPE)) { 176 sc->sc_rev = NCR_VARIANT_ESP100; 177 } else { 178 sc->sc_cfg2 = NCRCFG2_SCSI2; 179 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 180 sc->sc_cfg3 = 0; 181 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 182 sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK); 183 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 184 if (NCR_READ_REG(sc, NCR_CFG3) != 185 (NCRCFG3_CDB | NCRCFG3_FCLK)) { 186 sc->sc_rev = NCR_VARIANT_ESP100A; 187 } else { 188 /* NCRCFG2_FE enables > 64K transfers */ 189 sc->sc_cfg2 |= NCRCFG2_FE; 190 sc->sc_cfg3 = 0; 191 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 192 sc->sc_rev = NCR_VARIANT_ESP200; 193 } 194 } 195 196 /* 197 * XXX minsync and maxxfer _should_ be set up in MI code, 198 * XXX but it appears to have some dependency on what sort 199 * XXX of DMA we're hooked up to, etc. 200 */ 201 202 /* 203 * This is the value used to start sync negotiations 204 * Note that the NCR register "SYNCTP" is programmed 205 * in "clocks per byte", and has a minimum value of 4. 206 * The SCSI period used in negotiation is one-fourth 207 * of the time (in nanoseconds) needed to transfer one byte. 208 * Since the chip's clock is given in MHz, we have the following 209 * formula: 4 * period = (1000 / freq) * 4 210 */ 211 sc->sc_minsync = 1000 / sc->sc_freq; 212 213 /* 214 * Alas, we must now modify the value a bit, because it's 215 * only valid when can switch on FASTCLK and FASTSCSI bits 216 * in config register 3... 217 */ 218 switch (sc->sc_rev) { 219 case NCR_VARIANT_ESP100: 220 sc->sc_maxxfer = 64 * 1024; 221 sc->sc_minsync = 0; /* No synch on old chip? */ 222 break; 223 224 case NCR_VARIANT_ESP100A: 225 sc->sc_maxxfer = 64 * 1024; 226 /* Min clocks/byte is 5 */ 227 sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5); 228 break; 229 230 case NCR_VARIANT_ESP200: 231 sc->sc_maxxfer = 16 * 1024 * 1024; 232 /* XXX - do actually set FAST* bits */ 233 break; 234 } 235 236 /* and the interuppts */ 237 isr_add_autovect(ncr53c9x_intr, sc, ca->ca_intpri); 238 evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, NULL, 239 sc->sc_dev.dv_xname, "intr"); 240 241 /* Do the common parts of attachment. */ 242 sc->sc_adapter.adapt_minphys = minphys; 243 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 244 ncr53c9x_attach(sc); 245 246 #if 0 247 /* XXX - This doesn't work yet. Not sure why... */ 248 /* Turn on target selection using the `dma' method */ 249 sc->sc_features |= NCR_F_DMASELECT; /* XXX - OK? */ 250 #endif 251 } 252 253 254 /* 255 * Glue functions. 256 */ 257 258 u_char 259 esp_read_reg(sc, reg) 260 struct ncr53c9x_softc *sc; 261 int reg; 262 { 263 struct esp_softc *esc = (struct esp_softc *)sc; 264 265 return (esc->sc_reg[reg * 4]); 266 } 267 268 void 269 esp_write_reg(sc, reg, val) 270 struct ncr53c9x_softc *sc; 271 int reg; 272 u_char val; 273 { 274 struct esp_softc *esc = (struct esp_softc *)sc; 275 276 esc->sc_reg[reg * 4] = val; 277 } 278 279 int 280 esp_dma_isintr(sc) 281 struct ncr53c9x_softc *sc; 282 { 283 struct esp_softc *esc = (struct esp_softc *)sc; 284 u_int32_t csr; 285 286 csr = DMACSR(esc->sc_dma); 287 return (csr & (D_INT_PEND|D_ERR_PEND)); 288 } 289 290 void 291 esp_dma_reset(sc) 292 struct ncr53c9x_softc *sc; 293 { 294 struct esp_softc *esc = (struct esp_softc *)sc; 295 296 dma_reset(esc->sc_dma); 297 } 298 299 int 300 esp_dma_intr(sc) 301 struct ncr53c9x_softc *sc; 302 { 303 struct esp_softc *esc = (struct esp_softc *)sc; 304 305 return (espdmaintr(esc->sc_dma)); 306 } 307 308 int 309 esp_dma_setup(sc, addr, len, datain, dmasize) 310 struct ncr53c9x_softc *sc; 311 caddr_t *addr; 312 size_t *len; 313 int datain; 314 size_t *dmasize; 315 { 316 struct esp_softc *esc = (struct esp_softc *)sc; 317 318 return (dma_setup(esc->sc_dma, addr, len, datain, dmasize)); 319 } 320 321 void 322 esp_dma_go(sc) 323 struct ncr53c9x_softc *sc; 324 { 325 struct esp_softc *esc = (struct esp_softc *)sc; 326 327 /* Start DMA */ 328 DMACSR(esc->sc_dma) |= D_EN_DMA; 329 esc->sc_dma->sc_active = 1; 330 } 331 332 void 333 esp_dma_stop(sc) 334 struct ncr53c9x_softc *sc; 335 { 336 struct esp_softc *esc = (struct esp_softc *)sc; 337 338 DMACSR(esc->sc_dma) &= ~D_EN_DMA; 339 } 340 341 int 342 esp_dma_isactive(sc) 343 struct ncr53c9x_softc *sc; 344 { 345 struct esp_softc *esc = (struct esp_softc *)sc; 346 347 return (esc->sc_dma->sc_active); 348 } 349