1 /* $NetBSD: si_obio.c,v 1.22 2001/08/20 12:00:51 wiz Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Adam Glass, David Jones, and Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * This file contains only the machine-dependent parts of the 41 * Sun3 SCSI driver. (Autoconfig stuff and DMA functions.) 42 * The machine-independent parts are in ncr5380sbc.c 43 * 44 * Supported hardware includes: 45 * Sun SCSI-3 on OBIO (Sun3/50,Sun3/60) 46 * Sun SCSI-3 on VME (Sun3/160,Sun3/260) 47 * 48 * Could be made to support the Sun3/E if someone wanted to. 49 * 50 * Note: Both supported variants of the Sun SCSI-3 adapter have 51 * some really unusual "features" for this driver to deal with, 52 * generally related to the DMA engine. The OBIO variant will 53 * ignore any attempt to write the FIFO count register while the 54 * SCSI bus is in DATA_IN or DATA_OUT phase. This is dealt with 55 * by setting the FIFO count early in COMMAND or MSG_IN phase. 56 * 57 * The VME variant has a bit to enable or disable the DMA engine, 58 * but that bit also gates the interrupt line from the NCR5380! 59 * Therefore, in order to get any interrupt from the 5380, (i.e. 60 * for reselect) one must clear the DMA engine transfer count and 61 * then enable DMA. This has the further complication that you 62 * CAN NOT touch the NCR5380 while the DMA enable bit is set, so 63 * we have to turn DMA back off before we even look at the 5380. 64 * 65 * What wonderfully whacky hardware this is! 66 * 67 * Credits, history: 68 * 69 * David Jones wrote the initial version of this module, which 70 * included support for the VME adapter only. (no reselection). 71 * 72 * Gordon Ross added support for the OBIO adapter, and re-worked 73 * both the VME and OBIO code to support disconnect/reselect. 74 * (Required figuring out the hardware "features" noted above.) 75 * 76 * The autoconfiguration boilerplate came from Adam Glass. 77 */ 78 79 /***************************************************************** 80 * OBIO functions for DMA 81 ****************************************************************/ 82 83 #include <sys/param.h> 84 #include <sys/systm.h> 85 #include <sys/errno.h> 86 #include <sys/kernel.h> 87 #include <sys/malloc.h> 88 #include <sys/device.h> 89 #include <sys/buf.h> 90 #include <sys/proc.h> 91 #include <sys/user.h> 92 93 #include <dev/scsipi/scsi_all.h> 94 #include <dev/scsipi/scsipi_all.h> 95 #include <dev/scsipi/scsipi_debug.h> 96 #include <dev/scsipi/scsiconf.h> 97 98 #include <machine/autoconf.h> 99 #include <machine/dvma.h> 100 101 /* #define DEBUG XXX */ 102 103 #include <dev/ic/ncr5380reg.h> 104 #include <dev/ic/ncr5380var.h> 105 106 #include "sireg.h" 107 #include "sivar.h" 108 #include "am9516.h" 109 110 /* 111 * How many uS. to delay after touching the am9516 UDC. 112 */ 113 #define UDC_WAIT_USEC 5 114 115 void si_obio_dma_setup __P((struct ncr5380_softc *)); 116 void si_obio_dma_start __P((struct ncr5380_softc *)); 117 void si_obio_dma_eop __P((struct ncr5380_softc *)); 118 void si_obio_dma_stop __P((struct ncr5380_softc *)); 119 120 static void si_obio_reset __P((struct ncr5380_softc *)); 121 122 static __inline__ void si_obio_udc_write 123 __P((volatile struct si_regs *si, int regnum, int value)); 124 static __inline__ int si_obio_udc_read 125 __P((volatile struct si_regs *si, int regnum)); 126 127 128 /* 129 * New-style autoconfig attachment 130 */ 131 132 static int si_obio_match __P((struct device *, struct cfdata *, void *)); 133 static void si_obio_attach __P((struct device *, struct device *, void *)); 134 135 struct cfattach si_obio_ca = { 136 sizeof(struct si_softc), si_obio_match, si_obio_attach 137 }; 138 139 /* 140 * Options for disconnect/reselect, DMA, and interrupts. 141 * By default, allow disconnect/reselect on targets 4-6. 142 * Those are normally tapes that really need it enabled. 143 */ 144 int si_obio_options = 0x0f; 145 146 147 static int 148 si_obio_match(parent, cf, aux) 149 struct device *parent; 150 struct cfdata *cf; 151 void *aux; 152 { 153 struct confargs *ca = aux; 154 155 /* Make sure something is there... */ 156 if (bus_peek(ca->ca_bustype, ca->ca_paddr + 1, 1) == -1) 157 return (0); 158 159 /* Default interrupt priority. */ 160 if (ca->ca_intpri == -1) 161 ca->ca_intpri = 2; 162 163 return (1); 164 } 165 166 static void 167 si_obio_attach(parent, self, args) 168 struct device *parent, *self; 169 void *args; 170 { 171 struct si_softc *sc = (struct si_softc *) self; 172 struct ncr5380_softc *ncr_sc = &sc->ncr_sc; 173 struct cfdata *cf = self->dv_cfdata; 174 struct confargs *ca = args; 175 176 /* Get options from config flags if specified. */ 177 if (cf->cf_flags) 178 sc->sc_options = cf->cf_flags; 179 else 180 sc->sc_options = si_obio_options; 181 182 printf(": options=0x%x\n", sc->sc_options); 183 184 sc->sc_adapter_type = ca->ca_bustype; 185 sc->sc_regs = bus_mapin(ca->ca_bustype, 186 ca->ca_paddr, sizeof(struct si_regs)); 187 188 /* 189 * MD function pointers used by the MI code. 190 */ 191 ncr_sc->sc_pio_out = ncr5380_pio_out; 192 ncr_sc->sc_pio_in = ncr5380_pio_in; 193 ncr_sc->sc_dma_alloc = si_dma_alloc; 194 ncr_sc->sc_dma_free = si_dma_free; 195 ncr_sc->sc_dma_setup = si_obio_dma_setup; 196 ncr_sc->sc_dma_start = si_obio_dma_start; 197 ncr_sc->sc_dma_poll = si_dma_poll; 198 ncr_sc->sc_dma_eop = si_obio_dma_eop; 199 ncr_sc->sc_dma_stop = si_obio_dma_stop; 200 ncr_sc->sc_intr_on = NULL; 201 ncr_sc->sc_intr_off = NULL; 202 203 /* Need DVMA-capable memory for the UDC command block. */ 204 sc->sc_dmacmd = dvma_malloc(sizeof (struct udc_table)); 205 206 /* Attach interrupt handler. */ 207 isr_add_autovect(si_intr, (void *)sc, ca->ca_intpri); 208 209 /* Reset the hardware. */ 210 si_obio_reset(ncr_sc); 211 212 /* Do the common attach stuff. */ 213 si_attach(sc); 214 } 215 216 static void 217 si_obio_reset(struct ncr5380_softc *ncr_sc) 218 { 219 struct si_softc *sc = (struct si_softc *)ncr_sc; 220 volatile struct si_regs *si = sc->sc_regs; 221 222 #ifdef DEBUG 223 if (si_debug) { 224 printf("si_obio_reset\n"); 225 } 226 #endif 227 228 /* 229 * The SCSI3 controller has an 8K FIFO to buffer data between the 230 * 5380 and the DMA. Make sure it starts out empty. 231 * 232 * The reset bits in the CSR are active low. 233 */ 234 si->si_csr = 0; 235 delay(10); 236 si->si_csr = SI_CSR_FIFO_RES | SI_CSR_SCSI_RES | SI_CSR_INTR_EN; 237 delay(10); 238 si->fifo_count = 0; 239 } 240 241 static __inline__ void 242 si_obio_udc_write(si, regnum, value) 243 volatile struct si_regs *si; 244 int regnum, value; 245 { 246 si->udc_addr = regnum; 247 delay(UDC_WAIT_USEC); 248 si->udc_data = value; 249 delay(UDC_WAIT_USEC); 250 } 251 252 static __inline__ int 253 si_obio_udc_read(si, regnum) 254 volatile struct si_regs *si; 255 int regnum; 256 { 257 int value; 258 259 si->udc_addr = regnum; 260 delay(UDC_WAIT_USEC); 261 value = si->udc_data; 262 delay(UDC_WAIT_USEC); 263 264 return (value); 265 } 266 267 268 /* 269 * This function is called during the COMMAND or MSG_IN phase 270 * that precedes a DATA_IN or DATA_OUT phase, in case we need 271 * to setup the DMA engine before the bus enters a DATA phase. 272 * 273 * The OBIO "si" IGNORES any attempt to set the FIFO count 274 * register after the SCSI bus goes into any DATA phase, so 275 * this function has to setup the evil FIFO logic. 276 */ 277 void 278 si_obio_dma_setup(ncr_sc) 279 struct ncr5380_softc *ncr_sc; 280 { 281 struct si_softc *sc = (struct si_softc *)ncr_sc; 282 struct sci_req *sr = ncr_sc->sc_current; 283 struct si_dma_handle *dh = sr->sr_dma_hand; 284 volatile struct si_regs *si = sc->sc_regs; 285 struct udc_table *cmd; 286 long data_pa, cmd_pa; 287 int xlen; 288 289 /* 290 * Get the DVMA mapping for this segment. 291 * XXX - Should separate allocation and mapin. 292 */ 293 data_pa = dvma_kvtopa(dh->dh_dvma, sc->sc_adapter_type); 294 data_pa += (ncr_sc->sc_dataptr - dh->dh_addr); 295 if (data_pa & 1) 296 panic("si_dma_start: bad pa=0x%lx", data_pa); 297 xlen = ncr_sc->sc_datalen; 298 sc->sc_reqlen = xlen; /* XXX: or less? */ 299 300 #ifdef DEBUG 301 if (si_debug & 2) { 302 printf("si_dma_setup: dh=%p, pa=0x%lx, xlen=0x%x\n", 303 dh, data_pa, xlen); 304 } 305 #endif 306 307 /* Reset the UDC. (In case not already reset?) */ 308 si_obio_udc_write(si, UDC_ADR_COMMAND, UDC_CMD_RESET); 309 310 /* Reset the FIFO */ 311 si->si_csr &= ~SI_CSR_FIFO_RES; /* active low */ 312 si->si_csr |= SI_CSR_FIFO_RES; 313 314 /* Set direction (send/recv) */ 315 if (dh->dh_flags & SIDH_OUT) { 316 si->si_csr |= SI_CSR_SEND; 317 } else { 318 si->si_csr &= ~SI_CSR_SEND; 319 } 320 321 /* Set the FIFO counter. */ 322 si->fifo_count = xlen; 323 324 /* Reset the UDC. */ 325 si_obio_udc_write(si, UDC_ADR_COMMAND, UDC_CMD_RESET); 326 327 /* 328 * XXX: Reset the FIFO again! Comment from Sprite: 329 * Go through reset again becuase of the bug on the 3/50 330 * where bytes occasionally linger in the DMA fifo. 331 */ 332 si->si_csr &= ~SI_CSR_FIFO_RES; /* active low */ 333 si->si_csr |= SI_CSR_FIFO_RES; 334 335 #ifdef DEBUG 336 /* Make sure the extra FIFO reset did not hit the count. */ 337 if (si->fifo_count != xlen) { 338 printf("si_dma_setup: fifo_count=0x%x, xlen=0x%x\n", 339 si->fifo_count, xlen); 340 Debugger(); 341 } 342 #endif 343 344 /* 345 * Set up the DMA controller. The DMA controller on 346 * OBIO needs a command block in DVMA space. 347 */ 348 cmd = sc->sc_dmacmd; 349 cmd->addrh = ((data_pa & 0xFF0000) >> 8) | UDC_ADDR_INFO; 350 cmd->addrl = data_pa & 0xFFFF; 351 cmd->count = xlen / 2; /* bytes -> words */ 352 cmd->cmrh = UDC_CMR_HIGH; 353 if (dh->dh_flags & SIDH_OUT) { 354 if (xlen & 1) 355 cmd->count++; 356 cmd->cmrl = UDC_CMR_LSEND; 357 cmd->rsel = UDC_RSEL_SEND; 358 } else { 359 cmd->cmrl = UDC_CMR_LRECV; 360 cmd->rsel = UDC_RSEL_RECV; 361 } 362 363 /* Tell the DMA chip where the control block is. */ 364 cmd_pa = dvma_kvtopa(cmd, BUS_OBIO); 365 si_obio_udc_write(si, UDC_ADR_CAR_HIGH, 366 (cmd_pa & 0xff0000) >> 8); 367 si_obio_udc_write(si, UDC_ADR_CAR_LOW, 368 (cmd_pa & 0xffff)); 369 370 /* Tell the chip to be a DMA master. */ 371 si_obio_udc_write(si, UDC_ADR_MODE, UDC_MODE); 372 373 /* Tell the chip to interrupt on error. */ 374 si_obio_udc_write(si, UDC_ADR_COMMAND, UDC_CMD_CIE); 375 376 /* Will do "start chain" command in _dma_start. */ 377 } 378 379 380 void 381 si_obio_dma_start(ncr_sc) 382 struct ncr5380_softc *ncr_sc; 383 { 384 struct si_softc *sc = (struct si_softc *)ncr_sc; 385 struct sci_req *sr = ncr_sc->sc_current; 386 struct si_dma_handle *dh = sr->sr_dma_hand; 387 volatile struct si_regs *si = sc->sc_regs; 388 int s; 389 390 #ifdef DEBUG 391 if (si_debug & 2) { 392 printf("si_dma_start: sr=%p\n", sr); 393 } 394 #endif 395 396 /* This MAY be time critical (not sure). */ 397 s = splhigh(); 398 399 /* Finally, give the UDC a "start chain" command. */ 400 si_obio_udc_write(si, UDC_ADR_COMMAND, UDC_CMD_STRT_CHN); 401 402 /* 403 * Acknowledge the phase change. (After DMA setup!) 404 * Put the SBIC into DMA mode, and start the transfer. 405 */ 406 if (dh->dh_flags & SIDH_OUT) { 407 *ncr_sc->sci_tcmd = PHASE_DATA_OUT; 408 SCI_CLR_INTR(ncr_sc); 409 *ncr_sc->sci_icmd = SCI_ICMD_DATA; 410 *ncr_sc->sci_mode |= (SCI_MODE_DMA | SCI_MODE_DMA_IE); 411 *ncr_sc->sci_dma_send = 0; /* start it */ 412 } else { 413 *ncr_sc->sci_tcmd = PHASE_DATA_IN; 414 SCI_CLR_INTR(ncr_sc); 415 *ncr_sc->sci_icmd = 0; 416 *ncr_sc->sci_mode |= (SCI_MODE_DMA | SCI_MODE_DMA_IE); 417 *ncr_sc->sci_irecv = 0; /* start it */ 418 } 419 420 splx(s); 421 ncr_sc->sc_state |= NCR_DOINGDMA; 422 423 #ifdef DEBUG 424 if (si_debug & 2) { 425 printf("si_dma_start: started, flags=0x%x\n", 426 ncr_sc->sc_state); 427 } 428 #endif 429 } 430 431 432 void 433 si_obio_dma_eop(ncr_sc) 434 struct ncr5380_softc *ncr_sc; 435 { 436 437 /* Not needed - DMA was stopped prior to examining sci_csr */ 438 } 439 440 441 void 442 si_obio_dma_stop(ncr_sc) 443 struct ncr5380_softc *ncr_sc; 444 { 445 struct si_softc *sc = (struct si_softc *)ncr_sc; 446 struct sci_req *sr = ncr_sc->sc_current; 447 struct si_dma_handle *dh = sr->sr_dma_hand; 448 volatile struct si_regs *si = sc->sc_regs; 449 int resid, ntrans, tmo, udc_cnt; 450 451 if ((ncr_sc->sc_state & NCR_DOINGDMA) == 0) { 452 #ifdef DEBUG 453 printf("si_dma_stop: dma not running\n"); 454 #endif 455 return; 456 } 457 ncr_sc->sc_state &= ~NCR_DOINGDMA; 458 459 NCR_TRACE("si_dma_stop: top, csr=0x%x\n", si->si_csr); 460 461 /* OK, have either phase mis-match or end of DMA. */ 462 /* Set an impossible phase to prevent data movement? */ 463 *ncr_sc->sci_tcmd = PHASE_INVALID; 464 465 /* Check for DMA errors. */ 466 if (si->si_csr & (SI_CSR_DMA_CONFLICT | SI_CSR_DMA_BUS_ERR)) { 467 printf("si: DMA error, csr=0x%x, reset\n", si->si_csr); 468 sr->sr_xs->error = XS_DRIVER_STUFFUP; 469 ncr_sc->sc_state |= NCR_ABORTING; 470 si_obio_reset(ncr_sc); 471 goto out; 472 } 473 474 /* Note that timeout may have set the error flag. */ 475 if (ncr_sc->sc_state & NCR_ABORTING) 476 goto out; 477 478 /* 479 * After a read, wait for the FIFO to empty. 480 * Note: this only works on the OBIO version. 481 */ 482 if ((dh->dh_flags & SIDH_OUT) == 0) { 483 tmo = 200000; /* X10 = 2 sec. */ 484 for (;;) { 485 if (si->si_csr & SI_CSR_FIFO_EMPTY) 486 break; 487 if (--tmo <= 0) { 488 printf("si: dma fifo did not empty, reset\n"); 489 ncr_sc->sc_state |= NCR_ABORTING; 490 /* si_obio_reset(ncr_sc); */ 491 goto out; 492 } 493 delay(10); 494 } 495 } 496 497 /* 498 * Now try to figure out how much actually transferred. 499 * The fifo_count might not reflect how many bytes were 500 * actually transferred. 501 */ 502 resid = si->fifo_count & 0xFFFF; 503 ntrans = sc->sc_reqlen - resid; 504 505 #ifdef DEBUG 506 if (si_debug & 2) { 507 printf("si_dma_stop: resid=0x%x ntrans=0x%x\n", 508 resid, ntrans); 509 } 510 #endif 511 512 /* XXX: Treat (ntrans==0) as a special, non-error case? */ 513 if (ntrans < MIN_DMA_LEN) { 514 printf("si: fifo count: 0x%x\n", resid); 515 ncr_sc->sc_state |= NCR_ABORTING; 516 goto out; 517 } 518 if (ntrans > ncr_sc->sc_datalen) 519 panic("si_dma_stop: excess transfer"); 520 521 /* Adjust data pointer */ 522 ncr_sc->sc_dataptr += ntrans; 523 ncr_sc->sc_datalen -= ntrans; 524 525 /* 526 * After a read, we may need to clean-up 527 * "Left-over bytes" (yuck!) 528 */ 529 if ((dh->dh_flags & SIDH_OUT) == 0) { 530 /* If odd transfer count, grab last byte by hand. */ 531 if (ntrans & 1) { 532 NCR_TRACE("si_dma_stop: leftover 1 at 0x%x\n", 533 (int) ncr_sc->sc_dataptr - 1); 534 ncr_sc->sc_dataptr[-1] = 535 (si->fifo_data & 0xff00) >> 8; 536 goto out; 537 } 538 /* UDC might not have transfered the last word. */ 539 udc_cnt = si_obio_udc_read(si, UDC_ADR_COUNT); 540 if (((udc_cnt * 2) - resid) == 2) { 541 NCR_TRACE("si_dma_stop: leftover 2 at 0x%x\n", 542 (int) ncr_sc->sc_dataptr - 2); 543 ncr_sc->sc_dataptr[-2] = 544 (si->fifo_data & 0xff00) >> 8; 545 ncr_sc->sc_dataptr[-1] = 546 (si->fifo_data & 0x00ff); 547 } 548 } 549 550 out: 551 /* Reset the UDC. */ 552 si_obio_udc_write(si, UDC_ADR_COMMAND, UDC_CMD_RESET); 553 si->fifo_count = 0; 554 si->si_csr &= ~SI_CSR_SEND; 555 556 /* Reset the FIFO */ 557 si->si_csr &= ~SI_CSR_FIFO_RES; /* active low */ 558 si->si_csr |= SI_CSR_FIFO_RES; 559 560 /* Put SBIC back in PIO mode. */ 561 /* XXX: set tcmd to PHASE_INVALID? */ 562 *ncr_sc->sci_mode &= ~(SCI_MODE_DMA | SCI_MODE_DMA_IE); 563 *ncr_sc->sci_icmd = 0; 564 } 565 566