1 /* $NetBSD: si_vme.c,v 1.16 2001/08/20 12:00:51 wiz Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Adam Glass, David Jones, and Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * This file contains only the machine-dependent parts of the 41 * Sun3 SCSI driver. (Autoconfig stuff and DMA functions.) 42 * The machine-independent parts are in ncr5380sbc.c 43 * 44 * Supported hardware includes: 45 * Sun SCSI-3 on OBIO (Sun3/50,Sun3/60) 46 * Sun SCSI-3 on VME (Sun3/160,Sun3/260) 47 * 48 * Could be made to support the Sun3/E if someone wanted to. 49 * 50 * Note: Both supported variants of the Sun SCSI-3 adapter have 51 * some really unusual "features" for this driver to deal with, 52 * generally related to the DMA engine. The OBIO variant will 53 * ignore any attempt to write the FIFO count register while the 54 * SCSI bus is in DATA_IN or DATA_OUT phase. This is dealt with 55 * by setting the FIFO count early in COMMAND or MSG_IN phase. 56 * 57 * The VME variant has a bit to enable or disable the DMA engine, 58 * but that bit also gates the interrupt line from the NCR5380! 59 * Therefore, in order to get any interrupt from the 5380, (i.e. 60 * for reselect) one must clear the DMA engine transfer count and 61 * then enable DMA. This has the further complication that you 62 * CAN NOT touch the NCR5380 while the DMA enable bit is set, so 63 * we have to turn DMA back off before we even look at the 5380. 64 * 65 * What wonderfully whacky hardware this is! 66 * 67 * Credits, history: 68 * 69 * David Jones wrote the initial version of this module, which 70 * included support for the VME adapter only. (no reselection). 71 * 72 * Gordon Ross added support for the OBIO adapter, and re-worked 73 * both the VME and OBIO code to support disconnect/reselect. 74 * (Required figuring out the hardware "features" noted above.) 75 * 76 * The autoconfiguration boilerplate came from Adam Glass. 77 */ 78 79 /***************************************************************** 80 * VME functions for DMA 81 ****************************************************************/ 82 83 #include <sys/param.h> 84 #include <sys/systm.h> 85 #include <sys/errno.h> 86 #include <sys/kernel.h> 87 #include <sys/malloc.h> 88 #include <sys/device.h> 89 #include <sys/buf.h> 90 #include <sys/proc.h> 91 #include <sys/user.h> 92 93 #include <dev/scsipi/scsi_all.h> 94 #include <dev/scsipi/scsipi_all.h> 95 #include <dev/scsipi/scsipi_debug.h> 96 #include <dev/scsipi/scsiconf.h> 97 98 #include <machine/autoconf.h> 99 #include <machine/dvma.h> 100 101 /* #define DEBUG XXX */ 102 103 #include <dev/ic/ncr5380reg.h> 104 #include <dev/ic/ncr5380var.h> 105 106 #include "sireg.h" 107 #include "sivar.h" 108 109 void si_vme_dma_setup __P((struct ncr5380_softc *)); 110 void si_vme_dma_start __P((struct ncr5380_softc *)); 111 void si_vme_dma_eop __P((struct ncr5380_softc *)); 112 void si_vme_dma_stop __P((struct ncr5380_softc *)); 113 114 void si_vme_intr_on __P((struct ncr5380_softc *)); 115 void si_vme_intr_off __P((struct ncr5380_softc *)); 116 117 static void si_vme_reset __P((struct ncr5380_softc *)); 118 119 /* 120 * New-style autoconfig attachment 121 */ 122 123 static int si_vme_match __P((struct device *, struct cfdata *, void *)); 124 static void si_vme_attach __P((struct device *, struct device *, void *)); 125 126 struct cfattach si_vme_ca = { 127 sizeof(struct si_softc), si_vme_match, si_vme_attach 128 }; 129 130 /* 131 * Options for disconnect/reselect, DMA, and interrupts. 132 * By default, allow disconnect/reselect on targets 4-6. 133 * Those are normally tapes that really need it enabled. 134 */ 135 int si_vme_options = 0x0f; 136 137 138 static int 139 si_vme_match(parent, cf, aux) 140 struct device *parent; 141 struct cfdata *cf; 142 void *aux; 143 { 144 struct confargs *ca = aux; 145 int probe_addr; 146 147 /* No default VME address. */ 148 if (ca->ca_paddr == -1) 149 return (0); 150 151 /* Make sure something is there... */ 152 probe_addr = ca->ca_paddr + 1; 153 if (bus_peek(ca->ca_bustype, probe_addr, 1) == -1) 154 return (0); 155 156 /* 157 * If this is a VME SCSI board, we have to determine whether 158 * it is an "sc" (Sun2) or "si" (Sun3) SCSI board. This can 159 * be determined using the fact that the "sc" board occupies 160 * 4K bytes in VME space but the "si" board occupies 2K bytes. 161 */ 162 /* Note: the "si" board should NOT respond here. */ 163 probe_addr = ca->ca_paddr + 0x801; 164 if (bus_peek(ca->ca_bustype, probe_addr, 1) != -1) { 165 /* Something responded at 2K+1. Maybe an "sc" board? */ 166 #ifdef DEBUG 167 printf("si_vme_match: May be an `sc' board at pa=0x%x\n", 168 ca->ca_paddr); 169 #endif 170 return(0); 171 } 172 173 /* Default interrupt priority. */ 174 if (ca->ca_intpri == -1) 175 ca->ca_intpri = 2; 176 177 return (1); 178 } 179 180 static void 181 si_vme_attach(parent, self, args) 182 struct device *parent, *self; 183 void *args; 184 { 185 struct si_softc *sc = (struct si_softc *) self; 186 struct ncr5380_softc *ncr_sc = &sc->ncr_sc; 187 struct cfdata *cf = self->dv_cfdata; 188 struct confargs *ca = args; 189 190 /* Get options from config flags if specified. */ 191 if (cf->cf_flags) 192 sc->sc_options = cf->cf_flags; 193 else 194 sc->sc_options = si_vme_options; 195 196 printf(": options=0x%x\n", sc->sc_options); 197 198 sc->sc_adapter_type = ca->ca_bustype; 199 sc->sc_regs = (struct si_regs *) 200 bus_mapin(ca->ca_bustype, ca->ca_paddr, 201 sizeof(struct si_regs)); 202 sc->sc_adapter_iv_am = 203 VME_SUPV_DATA_24 | (ca->ca_intvec & 0xFF); 204 205 /* 206 * MD function pointers used by the MI code. 207 */ 208 ncr_sc->sc_pio_out = ncr5380_pio_out; 209 ncr_sc->sc_pio_in = ncr5380_pio_in; 210 ncr_sc->sc_dma_alloc = si_dma_alloc; 211 ncr_sc->sc_dma_free = si_dma_free; 212 ncr_sc->sc_dma_setup = si_vme_dma_setup; 213 ncr_sc->sc_dma_start = si_vme_dma_start; 214 ncr_sc->sc_dma_poll = si_dma_poll; 215 ncr_sc->sc_dma_eop = si_vme_dma_eop; 216 ncr_sc->sc_dma_stop = si_vme_dma_stop; 217 ncr_sc->sc_intr_on = si_vme_intr_on; 218 ncr_sc->sc_intr_off = si_vme_intr_off; 219 220 /* Attach interrupt handler. */ 221 isr_add_vectored(si_intr, (void *)sc, 222 ca->ca_intpri, ca->ca_intvec); 223 224 /* Reset the hardware. */ 225 si_vme_reset(ncr_sc); 226 227 /* Do the common attach stuff. */ 228 si_attach(sc); 229 } 230 231 static void 232 si_vme_reset(struct ncr5380_softc *ncr_sc) 233 { 234 struct si_softc *sc = (struct si_softc *)ncr_sc; 235 volatile struct si_regs *si = sc->sc_regs; 236 237 #ifdef DEBUG 238 if (si_debug) { 239 printf("si_vme_reset\n"); 240 } 241 #endif 242 243 /* 244 * The SCSI3 controller has an 8K FIFO to buffer data between the 245 * 5380 and the DMA. Make sure it starts out empty. 246 * 247 * The reset bits in the CSR are active low. 248 */ 249 si->si_csr = 0; 250 delay(10); 251 si->si_csr = SI_CSR_FIFO_RES | SI_CSR_SCSI_RES | SI_CSR_INTR_EN; 252 delay(10); 253 si->fifo_count = 0; 254 255 /* Make sure the DMA engine is stopped. */ 256 si->dma_addrh = 0; 257 si->dma_addrl = 0; 258 si->dma_counth = 0; 259 si->dma_countl = 0; 260 si->si_iv_am = sc->sc_adapter_iv_am; 261 si->fifo_cnt_hi = 0; 262 } 263 264 /* 265 * This is called when the bus is going idle, 266 * so we want to enable the SBC interrupts. 267 * That is controlled by the DMA enable! 268 * Who would have guessed! 269 * What a NASTY trick! 270 */ 271 void 272 si_vme_intr_on(ncr_sc) 273 struct ncr5380_softc *ncr_sc; 274 { 275 struct si_softc *sc = (struct si_softc *)ncr_sc; 276 volatile struct si_regs *si = sc->sc_regs; 277 278 /* receive mode should be safer */ 279 si->si_csr &= ~SI_CSR_SEND; 280 281 /* Clear the count so nothing happens. */ 282 si->dma_counth = 0; 283 si->dma_countl = 0; 284 285 /* Clear the start address too. (paranoid?) */ 286 si->dma_addrh = 0; 287 si->dma_addrl = 0; 288 289 /* Finally, enable the DMA engine. */ 290 si->si_csr |= SI_CSR_DMA_EN; 291 } 292 293 /* 294 * This is called when the bus is idle and we are 295 * about to start playing with the SBC chip. 296 */ 297 void 298 si_vme_intr_off(ncr_sc) 299 struct ncr5380_softc *ncr_sc; 300 { 301 struct si_softc *sc = (struct si_softc *)ncr_sc; 302 volatile struct si_regs *si = sc->sc_regs; 303 304 si->si_csr &= ~SI_CSR_DMA_EN; 305 } 306 307 /* 308 * This function is called during the COMMAND or MSG_IN phase 309 * that precedes a DATA_IN or DATA_OUT phase, in case we need 310 * to setup the DMA engine before the bus enters a DATA phase. 311 * 312 * XXX: The VME adapter appears to suppress SBC interrupts 313 * when the FIFO is not empty or the FIFO count is non-zero! 314 * 315 * On the VME version, setup the start addres, but clear the 316 * count (to make sure it stays idle) and set that later. 317 */ 318 void 319 si_vme_dma_setup(ncr_sc) 320 struct ncr5380_softc *ncr_sc; 321 { 322 struct si_softc *sc = (struct si_softc *)ncr_sc; 323 struct sci_req *sr = ncr_sc->sc_current; 324 struct si_dma_handle *dh = sr->sr_dma_hand; 325 volatile struct si_regs *si = sc->sc_regs; 326 long data_pa; 327 int xlen; 328 329 /* 330 * Get the DVMA mapping for this segment. 331 * XXX - Should separate allocation and mapin. 332 */ 333 data_pa = dvma_kvtopa(dh->dh_dvma, sc->sc_adapter_type); 334 data_pa += (ncr_sc->sc_dataptr - dh->dh_addr); 335 if (data_pa & 1) 336 panic("si_dma_start: bad pa=0x%lx", data_pa); 337 xlen = ncr_sc->sc_datalen; 338 xlen &= ~1; /* XXX: necessary? */ 339 sc->sc_reqlen = xlen; /* XXX: or less? */ 340 341 #ifdef DEBUG 342 if (si_debug & 2) { 343 printf("si_dma_setup: dh=%p, pa=0x%lx, xlen=0x%x\n", 344 dh, data_pa, xlen); 345 } 346 #endif 347 348 /* Set direction (send/recv) */ 349 if (dh->dh_flags & SIDH_OUT) { 350 si->si_csr |= SI_CSR_SEND; 351 } else { 352 si->si_csr &= ~SI_CSR_SEND; 353 } 354 355 /* Reset the FIFO. */ 356 si->si_csr &= ~SI_CSR_FIFO_RES; /* active low */ 357 si->si_csr |= SI_CSR_FIFO_RES; 358 359 if (data_pa & 2) { 360 si->si_csr |= SI_CSR_BPCON; 361 } else { 362 si->si_csr &= ~SI_CSR_BPCON; 363 } 364 365 /* Load the start address. */ 366 si->dma_addrh = (ushort)(data_pa >> 16); 367 si->dma_addrl = (ushort)(data_pa & 0xFFFF); 368 369 /* 370 * Keep the count zero or it may start early! 371 */ 372 si->dma_counth = 0; 373 si->dma_countl = 0; 374 375 #if 0 376 /* Clear FIFO counter. (also hits dma_count) */ 377 si->fifo_cnt_hi = 0; 378 si->fifo_count = 0; 379 #endif 380 } 381 382 383 void 384 si_vme_dma_start(ncr_sc) 385 struct ncr5380_softc *ncr_sc; 386 { 387 struct si_softc *sc = (struct si_softc *)ncr_sc; 388 struct sci_req *sr = ncr_sc->sc_current; 389 struct si_dma_handle *dh = sr->sr_dma_hand; 390 volatile struct si_regs *si = sc->sc_regs; 391 int s, xlen; 392 393 xlen = sc->sc_reqlen; 394 395 /* This MAY be time critical (not sure). */ 396 s = splhigh(); 397 398 si->dma_counth = (ushort)(xlen >> 16); 399 si->dma_countl = (ushort)(xlen & 0xFFFF); 400 401 /* Set it anyway, even though dma_count hits it. */ 402 si->fifo_cnt_hi = (ushort)(xlen >> 16); 403 si->fifo_count = (ushort)(xlen & 0xFFFF); 404 405 /* 406 * Acknowledge the phase change. (After DMA setup!) 407 * Put the SBIC into DMA mode, and start the transfer. 408 */ 409 if (dh->dh_flags & SIDH_OUT) { 410 *ncr_sc->sci_tcmd = PHASE_DATA_OUT; 411 SCI_CLR_INTR(ncr_sc); 412 *ncr_sc->sci_icmd = SCI_ICMD_DATA; 413 *ncr_sc->sci_mode |= (SCI_MODE_DMA | SCI_MODE_DMA_IE); 414 *ncr_sc->sci_dma_send = 0; /* start it */ 415 } else { 416 *ncr_sc->sci_tcmd = PHASE_DATA_IN; 417 SCI_CLR_INTR(ncr_sc); 418 *ncr_sc->sci_icmd = 0; 419 *ncr_sc->sci_mode |= (SCI_MODE_DMA | SCI_MODE_DMA_IE); 420 *ncr_sc->sci_irecv = 0; /* start it */ 421 } 422 423 /* Let'er rip! */ 424 si->si_csr |= SI_CSR_DMA_EN; 425 426 splx(s); 427 ncr_sc->sc_state |= NCR_DOINGDMA; 428 429 #ifdef DEBUG 430 if (si_debug & 2) { 431 printf("si_dma_start: started, flags=0x%x\n", 432 ncr_sc->sc_state); 433 } 434 #endif 435 } 436 437 438 void 439 si_vme_dma_eop(ncr_sc) 440 struct ncr5380_softc *ncr_sc; 441 { 442 443 /* Not needed - DMA was stopped prior to examining sci_csr */ 444 } 445 446 447 void 448 si_vme_dma_stop(ncr_sc) 449 struct ncr5380_softc *ncr_sc; 450 { 451 struct si_softc *sc = (struct si_softc *)ncr_sc; 452 struct sci_req *sr = ncr_sc->sc_current; 453 struct si_dma_handle *dh = sr->sr_dma_hand; 454 volatile struct si_regs *si = sc->sc_regs; 455 int resid, ntrans; 456 457 if ((ncr_sc->sc_state & NCR_DOINGDMA) == 0) { 458 #ifdef DEBUG 459 printf("si_dma_stop: dma not running\n"); 460 #endif 461 return; 462 } 463 ncr_sc->sc_state &= ~NCR_DOINGDMA; 464 465 /* First, halt the DMA engine. */ 466 si->si_csr &= ~SI_CSR_DMA_EN; /* VME only */ 467 468 /* Set an impossible phase to prevent data movement? */ 469 *ncr_sc->sci_tcmd = PHASE_INVALID; 470 471 if (si->si_csr & (SI_CSR_DMA_CONFLICT | SI_CSR_DMA_BUS_ERR)) { 472 printf("si: DMA error, csr=0x%x, reset\n", si->si_csr); 473 sr->sr_xs->error = XS_DRIVER_STUFFUP; 474 ncr_sc->sc_state |= NCR_ABORTING; 475 si_vme_reset(ncr_sc); 476 goto out; 477 } 478 479 /* Note that timeout may have set the error flag. */ 480 if (ncr_sc->sc_state & NCR_ABORTING) 481 goto out; 482 483 /* XXX: Wait for DMA to actually finish? */ 484 485 /* 486 * Now try to figure out how much actually transferred 487 * 488 * The fifo_count does not reflect how many bytes were 489 * actually transferred for VME. 490 * 491 * SCSI-3 VME interface is a little funny on writes: 492 * if we have a disconnect, the dma has overshot by 493 * one byte and the resid needs to be incremented. 494 * Only happens for partial transfers. 495 * (Thanks to Matt Jacob) 496 */ 497 498 resid = si->fifo_count & 0xFFFF; 499 if (dh->dh_flags & SIDH_OUT) 500 if ((resid > 0) && (resid < sc->sc_reqlen)) 501 resid++; 502 ntrans = sc->sc_reqlen - resid; 503 504 #ifdef DEBUG 505 if (si_debug & 2) { 506 printf("si_dma_stop: resid=0x%x ntrans=0x%x\n", 507 resid, ntrans); 508 } 509 #endif 510 511 if (ntrans < MIN_DMA_LEN) { 512 printf("si: fifo count: 0x%x\n", resid); 513 ncr_sc->sc_state |= NCR_ABORTING; 514 goto out; 515 } 516 if (ntrans > ncr_sc->sc_datalen) 517 panic("si_dma_stop: excess transfer"); 518 519 /* Adjust data pointer */ 520 ncr_sc->sc_dataptr += ntrans; 521 ncr_sc->sc_datalen -= ntrans; 522 523 /* 524 * After a read, we may need to clean-up 525 * "Left-over bytes" (yuck!) 526 */ 527 if (((dh->dh_flags & SIDH_OUT) == 0) && 528 ((si->si_csr & SI_CSR_LOB) != 0)) 529 { 530 char *cp = ncr_sc->sc_dataptr; 531 #ifdef DEBUG 532 printf("si: Got Left-over bytes!\n"); 533 #endif 534 if (si->si_csr & SI_CSR_BPCON) { 535 /* have SI_CSR_BPCON */ 536 cp[-1] = (si->si_bprl & 0xff00) >> 8; 537 } else { 538 switch (si->si_csr & SI_CSR_LOB) { 539 case SI_CSR_LOB_THREE: 540 cp[-3] = (si->si_bprh & 0xff00) >> 8; 541 cp[-2] = (si->si_bprh & 0x00ff); 542 cp[-1] = (si->si_bprl & 0xff00) >> 8; 543 break; 544 case SI_CSR_LOB_TWO: 545 cp[-2] = (si->si_bprh & 0xff00) >> 8; 546 cp[-1] = (si->si_bprh & 0x00ff); 547 break; 548 case SI_CSR_LOB_ONE: 549 cp[-1] = (si->si_bprh & 0xff00) >> 8; 550 break; 551 } 552 } 553 } 554 555 out: 556 si->dma_addrh = 0; 557 si->dma_addrl = 0; 558 559 si->dma_counth = 0; 560 si->dma_countl = 0; 561 562 si->fifo_cnt_hi = 0; 563 si->fifo_count = 0; 564 565 /* Put SBIC back in PIO mode. */ 566 *ncr_sc->sci_mode &= ~(SCI_MODE_DMA | SCI_MODE_DMA_IE); 567 *ncr_sc->sci_icmd = 0; 568 } 569