1 /* $NetBSD: si_vme.c,v 1.20 2002/10/08 21:29:46 jdolecek Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Adam Glass, David Jones, and Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * This file contains only the machine-dependent parts of the 41 * Sun3 SCSI driver. (Autoconfig stuff and DMA functions.) 42 * The machine-independent parts are in ncr5380sbc.c 43 * 44 * Supported hardware includes: 45 * Sun SCSI-3 on OBIO (Sun3/50,Sun3/60) 46 * Sun SCSI-3 on VME (Sun3/160,Sun3/260) 47 * 48 * Could be made to support the Sun3/E if someone wanted to. 49 * 50 * Note: Both supported variants of the Sun SCSI-3 adapter have 51 * some really unusual "features" for this driver to deal with, 52 * generally related to the DMA engine. The OBIO variant will 53 * ignore any attempt to write the FIFO count register while the 54 * SCSI bus is in DATA_IN or DATA_OUT phase. This is dealt with 55 * by setting the FIFO count early in COMMAND or MSG_IN phase. 56 * 57 * The VME variant has a bit to enable or disable the DMA engine, 58 * but that bit also gates the interrupt line from the NCR5380! 59 * Therefore, in order to get any interrupt from the 5380, (i.e. 60 * for reselect) one must clear the DMA engine transfer count and 61 * then enable DMA. This has the further complication that you 62 * CAN NOT touch the NCR5380 while the DMA enable bit is set, so 63 * we have to turn DMA back off before we even look at the 5380. 64 * 65 * What wonderfully whacky hardware this is! 66 * 67 * Credits, history: 68 * 69 * David Jones wrote the initial version of this module, which 70 * included support for the VME adapter only. (no reselection). 71 * 72 * Gordon Ross added support for the OBIO adapter, and re-worked 73 * both the VME and OBIO code to support disconnect/reselect. 74 * (Required figuring out the hardware "features" noted above.) 75 * 76 * The autoconfiguration boilerplate came from Adam Glass. 77 */ 78 79 /***************************************************************** 80 * VME functions for DMA 81 ****************************************************************/ 82 83 #include <sys/param.h> 84 #include <sys/systm.h> 85 #include <sys/errno.h> 86 #include <sys/kernel.h> 87 #include <sys/malloc.h> 88 #include <sys/device.h> 89 #include <sys/buf.h> 90 #include <sys/proc.h> 91 #include <sys/user.h> 92 93 #include <dev/scsipi/scsi_all.h> 94 #include <dev/scsipi/scsipi_all.h> 95 #include <dev/scsipi/scsipi_debug.h> 96 #include <dev/scsipi/scsiconf.h> 97 98 #include <machine/autoconf.h> 99 #include <machine/dvma.h> 100 101 /* #define DEBUG XXX */ 102 103 #include <dev/ic/ncr5380reg.h> 104 #include <dev/ic/ncr5380var.h> 105 106 #include "sireg.h" 107 #include "sivar.h" 108 109 void si_vme_dma_setup __P((struct ncr5380_softc *)); 110 void si_vme_dma_start __P((struct ncr5380_softc *)); 111 void si_vme_dma_eop __P((struct ncr5380_softc *)); 112 void si_vme_dma_stop __P((struct ncr5380_softc *)); 113 114 void si_vme_intr_on __P((struct ncr5380_softc *)); 115 void si_vme_intr_off __P((struct ncr5380_softc *)); 116 117 static void si_vme_reset __P((struct ncr5380_softc *)); 118 119 /* 120 * New-style autoconfig attachment 121 */ 122 123 static int si_vme_match __P((struct device *, struct cfdata *, void *)); 124 static void si_vme_attach __P((struct device *, struct device *, void *)); 125 126 CFATTACH_DECL(si_vme, sizeof(struct si_softc), 127 si_vme_match, si_vme_attach, NULL, NULL); 128 129 /* 130 * Options for disconnect/reselect, DMA, and interrupts. 131 * By default, allow disconnect/reselect on targets 4-6. 132 * Those are normally tapes that really need it enabled. 133 */ 134 int si_vme_options = 0x0f; 135 136 137 static int 138 si_vme_match(parent, cf, aux) 139 struct device *parent; 140 struct cfdata *cf; 141 void *aux; 142 { 143 struct confargs *ca = aux; 144 int probe_addr; 145 146 /* No default VME address. */ 147 if (ca->ca_paddr == -1) 148 return (0); 149 150 /* Make sure something is there... */ 151 probe_addr = ca->ca_paddr + 1; 152 if (bus_peek(ca->ca_bustype, probe_addr, 1) == -1) 153 return (0); 154 155 /* 156 * If this is a VME SCSI board, we have to determine whether 157 * it is an "sc" (Sun2) or "si" (Sun3) SCSI board. This can 158 * be determined using the fact that the "sc" board occupies 159 * 4K bytes in VME space but the "si" board occupies 2K bytes. 160 */ 161 /* Note: the "si" board should NOT respond here. */ 162 probe_addr = ca->ca_paddr + 0x801; 163 if (bus_peek(ca->ca_bustype, probe_addr, 1) != -1) { 164 /* Something responded at 2K+1. Maybe an "sc" board? */ 165 #ifdef DEBUG 166 printf("si_vme_match: May be an `sc' board at pa=0x%x\n", 167 ca->ca_paddr); 168 #endif 169 return(0); 170 } 171 172 /* Default interrupt priority. */ 173 if (ca->ca_intpri == -1) 174 ca->ca_intpri = 2; 175 176 return (1); 177 } 178 179 static void 180 si_vme_attach(parent, self, args) 181 struct device *parent, *self; 182 void *args; 183 { 184 struct si_softc *sc = (struct si_softc *) self; 185 struct ncr5380_softc *ncr_sc = &sc->ncr_sc; 186 struct cfdata *cf = self->dv_cfdata; 187 struct confargs *ca = args; 188 189 /* Get options from config flags if specified. */ 190 if (cf->cf_flags) 191 sc->sc_options = cf->cf_flags; 192 else 193 sc->sc_options = si_vme_options; 194 195 printf(": options=0x%x\n", sc->sc_options); 196 197 sc->sc_adapter_type = ca->ca_bustype; 198 sc->sc_regs = (struct si_regs *) 199 bus_mapin(ca->ca_bustype, ca->ca_paddr, 200 sizeof(struct si_regs)); 201 sc->sc_adapter_iv_am = 202 VME_SUPV_DATA_24 | (ca->ca_intvec & 0xFF); 203 204 /* 205 * MD function pointers used by the MI code. 206 */ 207 ncr_sc->sc_pio_out = ncr5380_pio_out; 208 ncr_sc->sc_pio_in = ncr5380_pio_in; 209 ncr_sc->sc_dma_alloc = si_dma_alloc; 210 ncr_sc->sc_dma_free = si_dma_free; 211 ncr_sc->sc_dma_setup = si_vme_dma_setup; 212 ncr_sc->sc_dma_start = si_vme_dma_start; 213 ncr_sc->sc_dma_poll = si_dma_poll; 214 ncr_sc->sc_dma_eop = si_vme_dma_eop; 215 ncr_sc->sc_dma_stop = si_vme_dma_stop; 216 ncr_sc->sc_intr_on = si_vme_intr_on; 217 ncr_sc->sc_intr_off = si_vme_intr_off; 218 219 /* Attach interrupt handler. */ 220 isr_add_vectored(si_intr, (void *)sc, 221 ca->ca_intpri, ca->ca_intvec); 222 223 /* Reset the hardware. */ 224 si_vme_reset(ncr_sc); 225 226 /* Do the common attach stuff. */ 227 si_attach(sc); 228 } 229 230 static void 231 si_vme_reset(struct ncr5380_softc *ncr_sc) 232 { 233 struct si_softc *sc = (struct si_softc *)ncr_sc; 234 volatile struct si_regs *si = sc->sc_regs; 235 236 #ifdef DEBUG 237 if (si_debug) { 238 printf("si_vme_reset\n"); 239 } 240 #endif 241 242 /* 243 * The SCSI3 controller has an 8K FIFO to buffer data between the 244 * 5380 and the DMA. Make sure it starts out empty. 245 * 246 * The reset bits in the CSR are active low. 247 */ 248 si->si_csr = 0; 249 delay(10); 250 si->si_csr = SI_CSR_FIFO_RES | SI_CSR_SCSI_RES | SI_CSR_INTR_EN; 251 delay(10); 252 si->fifo_count = 0; 253 254 /* Make sure the DMA engine is stopped. */ 255 si->dma_addrh = 0; 256 si->dma_addrl = 0; 257 si->dma_counth = 0; 258 si->dma_countl = 0; 259 si->si_iv_am = sc->sc_adapter_iv_am; 260 si->fifo_cnt_hi = 0; 261 } 262 263 /* 264 * This is called when the bus is going idle, 265 * so we want to enable the SBC interrupts. 266 * That is controlled by the DMA enable! 267 * Who would have guessed! 268 * What a NASTY trick! 269 */ 270 void 271 si_vme_intr_on(ncr_sc) 272 struct ncr5380_softc *ncr_sc; 273 { 274 struct si_softc *sc = (struct si_softc *)ncr_sc; 275 volatile struct si_regs *si = sc->sc_regs; 276 277 /* receive mode should be safer */ 278 si->si_csr &= ~SI_CSR_SEND; 279 280 /* Clear the count so nothing happens. */ 281 si->dma_counth = 0; 282 si->dma_countl = 0; 283 284 /* Clear the start address too. (paranoid?) */ 285 si->dma_addrh = 0; 286 si->dma_addrl = 0; 287 288 /* Finally, enable the DMA engine. */ 289 si->si_csr |= SI_CSR_DMA_EN; 290 } 291 292 /* 293 * This is called when the bus is idle and we are 294 * about to start playing with the SBC chip. 295 */ 296 void 297 si_vme_intr_off(ncr_sc) 298 struct ncr5380_softc *ncr_sc; 299 { 300 struct si_softc *sc = (struct si_softc *)ncr_sc; 301 volatile struct si_regs *si = sc->sc_regs; 302 303 si->si_csr &= ~SI_CSR_DMA_EN; 304 } 305 306 /* 307 * This function is called during the COMMAND or MSG_IN phase 308 * that precedes a DATA_IN or DATA_OUT phase, in case we need 309 * to setup the DMA engine before the bus enters a DATA phase. 310 * 311 * XXX: The VME adapter appears to suppress SBC interrupts 312 * when the FIFO is not empty or the FIFO count is non-zero! 313 * 314 * On the VME version, setup the start addres, but clear the 315 * count (to make sure it stays idle) and set that later. 316 */ 317 void 318 si_vme_dma_setup(ncr_sc) 319 struct ncr5380_softc *ncr_sc; 320 { 321 struct si_softc *sc = (struct si_softc *)ncr_sc; 322 struct sci_req *sr = ncr_sc->sc_current; 323 struct si_dma_handle *dh = sr->sr_dma_hand; 324 volatile struct si_regs *si = sc->sc_regs; 325 long data_pa; 326 int xlen; 327 328 /* 329 * Get the DVMA mapping for this segment. 330 * XXX - Should separate allocation and mapin. 331 */ 332 data_pa = dvma_kvtopa(dh->dh_dvma, sc->sc_adapter_type); 333 data_pa += (ncr_sc->sc_dataptr - dh->dh_addr); 334 if (data_pa & 1) 335 panic("si_dma_start: bad pa=0x%lx", data_pa); 336 xlen = ncr_sc->sc_datalen; 337 xlen &= ~1; /* XXX: necessary? */ 338 sc->sc_reqlen = xlen; /* XXX: or less? */ 339 340 #ifdef DEBUG 341 if (si_debug & 2) { 342 printf("si_dma_setup: dh=%p, pa=0x%lx, xlen=0x%x\n", 343 dh, data_pa, xlen); 344 } 345 #endif 346 347 /* Set direction (send/recv) */ 348 if (dh->dh_flags & SIDH_OUT) { 349 si->si_csr |= SI_CSR_SEND; 350 } else { 351 si->si_csr &= ~SI_CSR_SEND; 352 } 353 354 /* Reset the FIFO. */ 355 si->si_csr &= ~SI_CSR_FIFO_RES; /* active low */ 356 si->si_csr |= SI_CSR_FIFO_RES; 357 358 if (data_pa & 2) { 359 si->si_csr |= SI_CSR_BPCON; 360 } else { 361 si->si_csr &= ~SI_CSR_BPCON; 362 } 363 364 /* Load the start address. */ 365 si->dma_addrh = (ushort)(data_pa >> 16); 366 si->dma_addrl = (ushort)(data_pa & 0xFFFF); 367 368 /* 369 * Keep the count zero or it may start early! 370 */ 371 si->dma_counth = 0; 372 si->dma_countl = 0; 373 374 #if 0 375 /* Clear FIFO counter. (also hits dma_count) */ 376 si->fifo_cnt_hi = 0; 377 si->fifo_count = 0; 378 #endif 379 } 380 381 382 void 383 si_vme_dma_start(ncr_sc) 384 struct ncr5380_softc *ncr_sc; 385 { 386 struct si_softc *sc = (struct si_softc *)ncr_sc; 387 struct sci_req *sr = ncr_sc->sc_current; 388 struct si_dma_handle *dh = sr->sr_dma_hand; 389 volatile struct si_regs *si = sc->sc_regs; 390 int s, xlen; 391 392 xlen = sc->sc_reqlen; 393 394 /* This MAY be time critical (not sure). */ 395 s = splhigh(); 396 397 si->dma_counth = (ushort)(xlen >> 16); 398 si->dma_countl = (ushort)(xlen & 0xFFFF); 399 400 /* Set it anyway, even though dma_count hits it. */ 401 si->fifo_cnt_hi = (ushort)(xlen >> 16); 402 si->fifo_count = (ushort)(xlen & 0xFFFF); 403 404 /* 405 * Acknowledge the phase change. (After DMA setup!) 406 * Put the SBIC into DMA mode, and start the transfer. 407 */ 408 if (dh->dh_flags & SIDH_OUT) { 409 *ncr_sc->sci_tcmd = PHASE_DATA_OUT; 410 SCI_CLR_INTR(ncr_sc); 411 *ncr_sc->sci_icmd = SCI_ICMD_DATA; 412 *ncr_sc->sci_mode |= (SCI_MODE_DMA | SCI_MODE_DMA_IE); 413 *ncr_sc->sci_dma_send = 0; /* start it */ 414 } else { 415 *ncr_sc->sci_tcmd = PHASE_DATA_IN; 416 SCI_CLR_INTR(ncr_sc); 417 *ncr_sc->sci_icmd = 0; 418 *ncr_sc->sci_mode |= (SCI_MODE_DMA | SCI_MODE_DMA_IE); 419 *ncr_sc->sci_irecv = 0; /* start it */ 420 } 421 422 /* Let'er rip! */ 423 si->si_csr |= SI_CSR_DMA_EN; 424 425 splx(s); 426 ncr_sc->sc_state |= NCR_DOINGDMA; 427 428 #ifdef DEBUG 429 if (si_debug & 2) { 430 printf("si_dma_start: started, flags=0x%x\n", 431 ncr_sc->sc_state); 432 } 433 #endif 434 } 435 436 437 void 438 si_vme_dma_eop(ncr_sc) 439 struct ncr5380_softc *ncr_sc; 440 { 441 442 /* Not needed - DMA was stopped prior to examining sci_csr */ 443 } 444 445 446 void 447 si_vme_dma_stop(ncr_sc) 448 struct ncr5380_softc *ncr_sc; 449 { 450 struct si_softc *sc = (struct si_softc *)ncr_sc; 451 struct sci_req *sr = ncr_sc->sc_current; 452 struct si_dma_handle *dh = sr->sr_dma_hand; 453 volatile struct si_regs *si = sc->sc_regs; 454 int resid, ntrans; 455 456 if ((ncr_sc->sc_state & NCR_DOINGDMA) == 0) { 457 #ifdef DEBUG 458 printf("si_dma_stop: dma not running\n"); 459 #endif 460 return; 461 } 462 ncr_sc->sc_state &= ~NCR_DOINGDMA; 463 464 /* First, halt the DMA engine. */ 465 si->si_csr &= ~SI_CSR_DMA_EN; /* VME only */ 466 467 /* Set an impossible phase to prevent data movement? */ 468 *ncr_sc->sci_tcmd = PHASE_INVALID; 469 470 if (si->si_csr & (SI_CSR_DMA_CONFLICT | SI_CSR_DMA_BUS_ERR)) { 471 printf("si: DMA error, csr=0x%x, reset\n", si->si_csr); 472 sr->sr_xs->error = XS_DRIVER_STUFFUP; 473 ncr_sc->sc_state |= NCR_ABORTING; 474 si_vme_reset(ncr_sc); 475 goto out; 476 } 477 478 /* Note that timeout may have set the error flag. */ 479 if (ncr_sc->sc_state & NCR_ABORTING) 480 goto out; 481 482 /* XXX: Wait for DMA to actually finish? */ 483 484 /* 485 * Now try to figure out how much actually transferred 486 * 487 * The fifo_count does not reflect how many bytes were 488 * actually transferred for VME. 489 * 490 * SCSI-3 VME interface is a little funny on writes: 491 * if we have a disconnect, the dma has overshot by 492 * one byte and the resid needs to be incremented. 493 * Only happens for partial transfers. 494 * (Thanks to Matt Jacob) 495 */ 496 497 resid = si->fifo_count & 0xFFFF; 498 if (dh->dh_flags & SIDH_OUT) 499 if ((resid > 0) && (resid < sc->sc_reqlen)) 500 resid++; 501 ntrans = sc->sc_reqlen - resid; 502 503 #ifdef DEBUG 504 if (si_debug & 2) { 505 printf("si_dma_stop: resid=0x%x ntrans=0x%x\n", 506 resid, ntrans); 507 } 508 #endif 509 510 if (ntrans < MIN_DMA_LEN) { 511 printf("si: fifo count: 0x%x\n", resid); 512 ncr_sc->sc_state |= NCR_ABORTING; 513 goto out; 514 } 515 if (ntrans > ncr_sc->sc_datalen) 516 panic("si_dma_stop: excess transfer"); 517 518 /* Adjust data pointer */ 519 ncr_sc->sc_dataptr += ntrans; 520 ncr_sc->sc_datalen -= ntrans; 521 522 /* 523 * After a read, we may need to clean-up 524 * "Left-over bytes" (yuck!) 525 */ 526 if (((dh->dh_flags & SIDH_OUT) == 0) && 527 ((si->si_csr & SI_CSR_LOB) != 0)) 528 { 529 char *cp = ncr_sc->sc_dataptr; 530 #ifdef DEBUG 531 printf("si: Got Left-over bytes!\n"); 532 #endif 533 if (si->si_csr & SI_CSR_BPCON) { 534 /* have SI_CSR_BPCON */ 535 cp[-1] = (si->si_bprl & 0xff00) >> 8; 536 } else { 537 switch (si->si_csr & SI_CSR_LOB) { 538 case SI_CSR_LOB_THREE: 539 cp[-3] = (si->si_bprh & 0xff00) >> 8; 540 cp[-2] = (si->si_bprh & 0x00ff); 541 cp[-1] = (si->si_bprl & 0xff00) >> 8; 542 break; 543 case SI_CSR_LOB_TWO: 544 cp[-2] = (si->si_bprh & 0xff00) >> 8; 545 cp[-1] = (si->si_bprh & 0x00ff); 546 break; 547 case SI_CSR_LOB_ONE: 548 cp[-1] = (si->si_bprh & 0xff00) >> 8; 549 break; 550 } 551 } 552 } 553 554 out: 555 si->dma_addrh = 0; 556 si->dma_addrl = 0; 557 558 si->dma_counth = 0; 559 si->dma_countl = 0; 560 561 si->fifo_cnt_hi = 0; 562 si->fifo_count = 0; 563 564 /* Put SBIC back in PIO mode. */ 565 *ncr_sc->sci_mode &= ~(SCI_MODE_DMA | SCI_MODE_DMA_IE); 566 *ncr_sc->sci_icmd = 0; 567 } 568