1 /* $NetBSD: mc68851.h,v 1.5 1997/05/14 01:37:23 jeremy Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jeremy Cooper. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * This file contains the machine-independent definitions 41 * related to the Motorola MC68851 Memory Management Unit (MMU). 42 * Things that depend on the contents of the Translation Control 43 * (TC) register are in <machine/pte.h>. 44 */ 45 46 #ifndef _SUN3X_MC68851_H 47 #define _SUN3X_MC68851_H 48 49 /**************************** MMU STRUCTURES **************************** 50 * MMU structures define the format of data used by the MC68851. * 51 ************************************************************************ 52 ** MC68851 Root Pointer 53 * All address translations begin with the examination of the value 54 * in the MC68851 Root Pointer register. It describes the base address 55 * (in physical memory) of the root table to be used as well as any limits 56 * to the address range it supports. Its structure is identical to a Long 57 * Format Table Descriptor (described below.) 58 */ 59 struct mmu_rootptr { 60 u_long rp_attr; /* Lower/Upper Limit and access flags */ 61 u_long rp_addr; /* Physical Base Address */ 62 }; 63 typedef struct mmu_rootptr mmu_rootptr_t; 64 65 66 /** MC68851 Long Format Table Descriptor 67 * The root table for a sun3x pmap is a 128 element array of 'long format 68 * table descriptors'. The structure of a long format table descriptor is: 69 * 70 * 63 48 71 * +---+---.---.---.---.---.---.---.---.---.---.---.---.---.---.---+ 72 * |L/U| LIMIT | 73 * +---+---.---+---.---.---+---+---+---+---+---+---+---+---+---.---+ 74 * | RAL | WAL |SG | S | 0 | 0 | 0 | 0 | U |WP |DT (10)| 75 * +---.---.---+---.---.---+---+---+---+---+---+---+---+---+---.---+ 76 * | TABLE PHYSICAL ADDRESS (BITS 31-16) | 77 * +---.---.---.---.---.---.---.---.---.---.---.---+---.---.---.---+ 78 * | TABLE PHYSICAL ADDRESS (15-4) | UNUSED | 79 * +---.---.---.---.---.---.---.---.---.---.---.---+---.---.---.---+ 80 * 15 0 81 * 82 * Note: keep the unused bits set to zero so that no masking of the 83 * base address is needed. 84 */ 85 struct mmu_long_dte_struct { /* 'dte' stands for 'descriptor table entry' */ 86 union { 87 struct { 88 char lu_flag:1; /* Lower/Upper Limit flag */ 89 int limit:15; /* Table Size limit */ 90 char ral:3; /* Read Access Level */ 91 char wal:3; /* Write Access Level */ 92 char sg:1; /* Shared Globally flag */ 93 char supv:1; /* Supervisor Only flag */ 94 char rsvd:4; /* Reserved (All zeros) */ 95 char u:1; /* Used flag */ 96 char wp:1; /* Write Protect flag */ 97 char dt:2; /* Descriptor Type */ 98 /* Bit masks for fields above */ 99 #define MMU_LONG_DTE_LU 0x80000000 100 #define MMU_LONG_DTE_LIMIT 0x7fff0000 101 #define MMU_LONG_DTE_RAL 0x0000e000 102 #define MMU_LONG_DTE_WAL 0x00001c00 103 #define MMU_LONG_DTE_SG 0x00000200 104 #define MMU_LONG_DTE_SUPV 0x00000100 105 #define MMU_LONG_DTE_USED 0x00000008 106 #define MMU_LONG_DTE_WP 0x00000004 107 #define MMU_LONG_DTE_DT 0x00000003 108 } attr_struct; 109 u_long raw; /* struct above, addressable as a long */ 110 } attr; 111 union { 112 struct { 113 int base_addr:28; /* Physical base address 114 char unused:4; * of the table pointed to 115 * by this entry. 116 */ 117 /* Bit masks for fields above */ 118 #define MMU_LONG_DTE_BASEADDR 0xfffffff0 119 } addr_struct; 120 u_long raw; /* struct above, addressable as a long */ 121 } addr; 122 }; 123 typedef struct mmu_long_dte_struct mmu_long_dte_t; 124 typedef struct mmu_long_dte_struct *mmu_long_dtbl_t; 125 126 /** MC68851 Long Format Page Descriptor 127 * Although not likely to be used in this implementation, a level 128 * 'A' table may contain long format PAGE descriptors. A long format 129 * page descriptor is the same size as a long format table descriptor. 130 * Its discriminating feature to the MMU is its descriptor field: 01. 131 * 63 48 132 * +---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---+ 133 * | UNUSED | 134 * +---.---.---+---.---.---+---+---+---+---+---+---+---+---+---.---+ 135 * | RAL | WAL |SG | S | G |CI | L | M | U |WP |DT (01)| 136 * +---.---.---+---.---.---+---+---+---+---+---+---+---+---+---.---+ 137 * | TABLE PHYSICAL ADDRESS (BITS 31-16) | 138 * +---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---+ 139 * |TABLE PHYS. ADDRESS (15-8) | UNUSED | 140 * +---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---+ 141 * 15 0 142 */ 143 struct mmu_long_pte_struct { /* 'pte' stands for 'page table entry' */ 144 union { 145 struct { 146 int unused:16; /* Unused */ 147 char ral:3; /* Read Access Level */ 148 char wal:3; /* Write Access Level */ 149 char sg:1; /* Shared Globally flag */ 150 char supv:1; /* Supervisor Only flag */ 151 char g:1; /* Gate allowed */ 152 char ci:1; /* Cache inhibit */ 153 char l:1; /* Lock entry */ 154 char m:1; /* Modified flag */ 155 char u:1; /* Used flag */ 156 char wp:1; /* Write Protect flag */ 157 char dt:2; /* Descriptor Type */ 158 /* Bit masks for fields above */ 159 #define MMU_LONG_PTE_RAL 0x0000e000 160 #define MMU_LONG_PTE_WAL 0x00001c00 161 #define MMU_LONG_PTE_SG 0x00000200 162 #define MMU_LONG_PTE_SUPV 0x00000100 163 #define MMU_LONG_PTE_GATE 0x00000080 164 #define MMU_LONG_PTE_CI 0x00000040 165 #define MMU_LONG_PTE_LOCK 0x00000020 166 #define MMU_LONG_PTE_M 0x00000010 167 #define MMU_LONG_PTE_USED 0x00000008 168 #define MMU_LONG_PTE_WP 0x00000004 169 #define MMU_LONG_PTE_DT 0x00000003 170 } attr_struct; 171 u_long raw; /* struct above, addressable as a long */ 172 } attr; 173 union { 174 struct { 175 long base_addr:24; /* Physical base address 176 char unused:8; * of page this entry 177 * points to. 178 */ 179 /* Bit masks for fields above */ 180 #define MMU_LONG_PTE_BASEADDR 0xffffff00 181 } addr_struct; 182 u_long raw; /* struct above, addressable as a long */ 183 } addr; 184 }; 185 typedef struct mmu_long_pte_struct mmu_long_pte_t; 186 typedef struct mmu_long_pte_struct *mmu_long_ptbl_t; 187 188 /* Every entry in the level A table (except for the page entries 189 * described above) points to a level B table. Level B tables are 190 * arrays of 'short format' table descriptors. Their structure 191 * is smaller than an A table descriptor and is as follows: 192 * 193 * 31 16 194 * +---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---+ 195 * | TABLE PHYSICAL BASE ADDRESS (BITS 31-16) | 196 * +---.---.---.---.---.---.---.---.---.---.---.---+---+---+---.---+ 197 * | TABLE PHYSICAL BASE ADDRESS (15-4) | U |WP |DT (10)| 198 * +---.---.---.---.---.---.---.---.---.---.---.---+---+---+---.---+ 199 * 15 0 200 */ 201 struct mmu_short_dte_struct { /* 'dte' stands for 'descriptor table entry' */ 202 union { 203 struct { 204 long base_addr:28; 205 char u:1; 206 char wp:1; 207 char dt:2; 208 #define MMU_SHORT_DTE_BASEADDR 0xfffffff0 209 #define MMU_SHORT_DTE_USED 0x00000008 210 #define MMU_SHORT_DTE_WP 0x00000004 211 #define MMU_SHORT_DTE_DT 0x00000003 212 } attr_struct; 213 u_long raw; 214 } attr; 215 }; 216 typedef struct mmu_short_dte_struct mmu_short_dte_t; 217 typedef struct mmu_short_dte_struct *mmu_short_dtbl_t; 218 219 /* Every entry in a level B table points to a level C table. Level C tables 220 * contain arrays of short format page 'entry' descriptors. A short format 221 * page 'entry' is the same size as a short format page 'table' 222 * descriptor (a B table entry). Thus B and C tables can be allocated 223 * interchangeably from the same pool. However, we will keep them separate. 224 * 225 * The descriptor type (DT) field of a Page Table Entry (PTE) is '01'. This 226 * indicates to the MMU that the address contained in the PTE's 'base 227 * address' field is the base address for a physical page in memory to which 228 * the VA should be mapped, and not a base address for a yet another 229 * descriptor table, thus ending the table walk. 230 * 231 * 31 16 232 * +---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---+ 233 * | TABLE PHYSICAL BASE ADDRESS (BITS 31-16) | 234 * +---.---.---.---.---.---.---.---+---+---+---+---+---+---+---.---+ 235 * |TABLE PHYS. BASE ADDRESS (15-8)| G |CI | L | M | U |WP |DT (10)| 236 * +---.---.---.---.---.---.---.---+---+---+---+---+---+---+---.---+ 237 * 15 0 238 */ 239 struct mmu_short_pte_struct { /* 'pte' stands for 'page table entry' */ 240 union { 241 struct { 242 long base_addr:24; 243 char g:1; 244 char ci:1; 245 char l:1; 246 char m:1; 247 char u:1; 248 char wp:1; 249 char dt:2; 250 #define MMU_SHORT_PTE_BASEADDR 0xffffff00 251 #define MMU_SHORT_PTE_UN2 0x00000080 252 #define MMU_SHORT_PTE_CI 0x00000040 253 #define MMU_SHORT_PTE_UN1 0x00000020 254 #define MMU_SHORT_PTE_M 0x00000010 255 #define MMU_SHORT_PTE_USED 0x00000008 256 #define MMU_SHORT_PTE_WP 0x00000004 257 #define MMU_SHORT_PTE_DT 0x00000003 258 } attr_struct; 259 u_long raw; 260 } attr; 261 }; 262 typedef struct mmu_short_pte_struct mmu_short_pte_t; 263 typedef struct mmu_short_pte_struct *mmu_short_ptbl_t; 264 265 /* These are bit masks and other values that are common to all types of 266 * descriptors. 267 */ 268 /* Page table descriptors have a 'Descriptor Type' field describing the 269 * format of the tables they point to. It is two bits wide and is one of: 270 */ 271 #define MMU_DT_INVALID 0x0 /* Invalid descriptor entry */ 272 #define MMU_DT_PAGE 0x1 /* Descriptor describes a page entry */ 273 #define MMU_DT_SHORT 0x2 /* describes a short format table */ 274 #define MMU_DT_LONG 0x3 /* describes a long format table */ 275 #define MMU_DT_MASK 0x00000003 /* Bit location of the DT field */ 276 277 /* Various macros for manipulating and setting MMU descriptor 278 * characteristics. 279 */ 280 /* returns true if a descriptor is valid. */ 281 #define MMU_VALID_DT(dte) ((dte).attr.raw & MMU_DT_MASK) 282 /* returns true if a descriptor is invalid */ 283 #define MMU_INVALID_DT(dte) (!((dte).attr.raw & MMU_DT_MASK)) 284 /* returns true if a descriptor has been referenced */ 285 #define MMU_PTE_USED(pte) ((pte).attr.raw & MMU_SHORT_PTE_USED) 286 /* returns true if a descriptor has been modified */ 287 #define MMU_PTE_MODIFIED(pte) ((pte).attr.raw & MMU_SHORT_PTE_M) 288 /* extracts the physical address from a pte */ 289 #define MMU_PTE_PA(pte) ((pte).attr.raw & MMU_SHORT_PTE_BASEADDR) 290 /* extracts the physical address from a dte */ 291 #define MMU_DTE_PA(dte) ((dte).attr.raw & MMU_SHORT_DTE_BASEADDR) 292 293 #endif /* _SUN3X_MC68851_H */ 294