1 /* $NetBSD: pte3x.h,v 1.7 1998/02/05 04:57:00 gwr Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jeremy Cooper. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * This file should contain the machine-dependent details about 41 * Page Table Entries (PTEs) and related things. For example, 42 * things that depend on the MMU configuration (number of levels 43 * in the translation structure) should go here. 44 */ 45 46 #ifndef _MACHINE_PTE3X_H 47 #define _MACHINE_PTE3X_H 48 49 #include <machine/mc68851.h> 50 51 /************************************************************************* 52 * Translation Control Register Settings * 53 ************************************************************************* 54 * The following settings are set by the ROM monitor and used by the 55 * kernel. If they are changed, appropriate code must be written into 56 * the kernel startup to set them. 57 * 58 * A virtual address is translated into a physical address by dividing its 59 * bits into four fields. The first three fields are used as indexes into 60 * descriptor tables and the last field (the 13 lowest significant 61 * bits) is an offset to be added to the base address found at the final 62 * table. The first three fields are named TIA, TIB and TIC respectively. 63 * 31 12 0 64 * +-.-.-.-.-.-.-+-.-.-.-.-.-+-.-.-.-.-.-+-.-.-.-.-.-.-.-.-.-.-.-.-+ 65 * | TIA | TIB | TIC | OFFSET | 66 * +-.-.-.-.-.-.-+-.-.-.-.-.-+-.-.-.-.-.-+-.-.-.-.-.-.-.-.-.-.-.-.-+ 67 */ 68 #define MMU_TIA_SHIFT (13+6+6) 69 #define MMU_TIA_MASK (0xfe000000) 70 #define MMU_TIA_RANGE (0x02000000) 71 #define MMU_TIB_SHIFT (13+6) 72 #define MMU_TIB_MASK (0x01f80000) 73 #define MMU_TIB_RANGE (0x00080000) 74 #define MMU_TIC_SHIFT (13) 75 #define MMU_TIC_MASK (0x0007e000) 76 #define MMU_TIC_RANGE (0x00002000) 77 #define MMU_PAGE_SHIFT (13) 78 #define MMU_PAGE_MASK (0xffffe000) 79 #define MMU_PAGE_SIZE (0x00002000) 80 81 /* 82 * Macros which extract each of these fields out of a given 83 * VA. 84 */ 85 #define MMU_TIA(va) \ 86 ((unsigned long) ((va) & MMU_TIA_MASK) >> MMU_TIA_SHIFT) 87 #define MMU_TIB(va) \ 88 ((unsigned long) ((va) & MMU_TIB_MASK) >> MMU_TIB_SHIFT) 89 #define MMU_TIC(va) \ 90 ((unsigned long) ((va) & MMU_TIC_MASK) >> MMU_TIC_SHIFT) 91 92 /* 93 * The widths of the TIA, TIB, and TIC fields determine the size (in 94 * elements) of the tables they index. 95 */ 96 #define MMU_A_TBL_SIZE (128) 97 #define MMU_B_TBL_SIZE (64) 98 #define MMU_C_TBL_SIZE (64) 99 100 /* 101 * Rounding macros. 102 * The MMU_ROUND macros are named misleadingly. MMU_ROUND_A actually 103 * rounds an address to the nearest B table boundary, and so on. 104 * MMU_ROUND_C() is synonmous with m68k_round_page(). 105 */ 106 #define MMU_ROUND_A(pa)\ 107 ((unsigned long) (pa) & MMU_TIA_MASK) 108 #define MMU_ROUND_UP_A(pa)\ 109 ((unsigned long) (pa + MMU_TIA_RANGE - 1) & MMU_TIA_MASK) 110 #define MMU_ROUND_B(pa)\ 111 ((unsigned long) (pa) & (MMU_TIA_MASK|MMU_TIB_MASK)) 112 #define MMU_ROUND_UP_B(pa)\ 113 ((unsigned long) (pa + MMU_TIB_RANGE - 1) & (MMU_TIA_MASK|MMU_TIB_MASK)) 114 #define MMU_ROUND_C(pa)\ 115 ((unsigned long) (pa) & MMU_PAGE_MASK) 116 #define MMU_ROUND_UP_C(pa)\ 117 ((unsigned long) (pa + MMU_PAGE_SIZE - 1) & MMU_PAGE_MASK) 118 119 /* Compatibility... */ 120 #define PG_FRAME MMU_SHORT_PTE_BASEADDR 121 #define PG_PA(pte) ((pte) & PG_FRAME) 122 #define PG_PFNUM(pte) (PG_PA(pte) >> PGSHIFT) 123 #define PG_VALID MMU_DT_PAGE 124 125 #endif /* _MACHINE_PTE3X_H */ 126