1 /* $NetBSD: pmap.c,v 1.75 2002/10/20 02:37:38 chs Exp $ */ 2 3 /*- 4 * Copyright (c) 1996, 1997 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jeremy Cooper. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * XXX These comments aren't quite accurate. Need to change. 41 * The sun3x uses the MC68851 Memory Management Unit, which is built 42 * into the CPU. The 68851 maps virtual to physical addresses using 43 * a multi-level table lookup, which is stored in the very memory that 44 * it maps. The number of levels of lookup is configurable from one 45 * to four. In this implementation, we use three, named 'A' through 'C'. 46 * 47 * The MMU translates virtual addresses into physical addresses by 48 * traversing these tables in a proccess called a 'table walk'. The most 49 * significant 7 bits of the Virtual Address ('VA') being translated are 50 * used as an index into the level A table, whose base in physical memory 51 * is stored in a special MMU register, the 'CPU Root Pointer' or CRP. The 52 * address found at that index in the A table is used as the base 53 * address for the next table, the B table. The next six bits of the VA are 54 * used as an index into the B table, which in turn gives the base address 55 * of the third and final C table. 56 * 57 * The next six bits of the VA are used as an index into the C table to 58 * locate a Page Table Entry (PTE). The PTE is a physical address in memory 59 * to which the remaining 13 bits of the VA are added, producing the 60 * mapped physical address. 61 * 62 * To map the entire memory space in this manner would require 2114296 bytes 63 * of page tables per process - quite expensive. Instead we will 64 * allocate a fixed but considerably smaller space for the page tables at 65 * the time the VM system is initialized. When the pmap code is asked by 66 * the kernel to map a VA to a PA, it allocates tables as needed from this 67 * pool. When there are no more tables in the pool, tables are stolen 68 * from the oldest mapped entries in the tree. This is only possible 69 * because all memory mappings are stored in the kernel memory map 70 * structures, independent of the pmap structures. A VA which references 71 * one of these invalidated maps will cause a page fault. The kernel 72 * will determine that the page fault was caused by a task using a valid 73 * VA, but for some reason (which does not concern it), that address was 74 * not mapped. It will ask the pmap code to re-map the entry and then 75 * it will resume executing the faulting task. 76 * 77 * In this manner the most efficient use of the page table space is 78 * achieved. Tasks which do not execute often will have their tables 79 * stolen and reused by tasks which execute more frequently. The best 80 * size for the page table pool will probably be determined by 81 * experimentation. 82 * 83 * You read all of the comments so far. Good for you. 84 * Now go play! 85 */ 86 87 /*** A Note About the 68851 Address Translation Cache 88 * The MC68851 has a 64 entry cache, called the Address Translation Cache 89 * or 'ATC'. This cache stores the most recently used page descriptors 90 * accessed by the MMU when it does translations. Using a marker called a 91 * 'task alias' the MMU can store the descriptors from 8 different table 92 * spaces concurrently. The task alias is associated with the base 93 * address of the level A table of that address space. When an address 94 * space is currently active (the CRP currently points to its A table) 95 * the only cached descriptors that will be obeyed are ones which have a 96 * matching task alias of the current space associated with them. 97 * 98 * Since the cache is always consulted before any table lookups are done, 99 * it is important that it accurately reflect the state of the MMU tables. 100 * Whenever a change has been made to a table that has been loaded into 101 * the MMU, the code must be sure to flush any cached entries that are 102 * affected by the change. These instances are documented in the code at 103 * various points. 104 */ 105 /*** A Note About the Note About the 68851 Address Translation Cache 106 * 4 months into this code I discovered that the sun3x does not have 107 * a MC68851 chip. Instead, it has a version of this MMU that is part of the 108 * the 68030 CPU. 109 * All though it behaves very similarly to the 68851, it only has 1 task 110 * alias and a 22 entry cache. So sadly (or happily), the first paragraph 111 * of the previous note does not apply to the sun3x pmap. 112 */ 113 114 #include "opt_ddb.h" 115 116 #include <sys/param.h> 117 #include <sys/systm.h> 118 #include <sys/proc.h> 119 #include <sys/malloc.h> 120 #include <sys/pool.h> 121 #include <sys/user.h> 122 #include <sys/queue.h> 123 #include <sys/kcore.h> 124 125 #include <uvm/uvm.h> 126 127 #include <machine/cpu.h> 128 #include <machine/kcore.h> 129 #include <machine/mon.h> 130 #include <machine/pmap.h> 131 #include <machine/pte.h> 132 #include <machine/vmparam.h> 133 #include <m68k/cacheops.h> 134 135 #include <sun3/sun3/cache.h> 136 #include <sun3/sun3/machdep.h> 137 138 #include "pmap_pvt.h" 139 140 /* XXX - What headers declare these? */ 141 extern struct pcb *curpcb; 142 extern int physmem; 143 144 /* Defined in locore.s */ 145 extern char kernel_text[]; 146 147 /* Defined by the linker */ 148 extern char etext[], edata[], end[]; 149 extern char *esym; /* DDB */ 150 151 /*************************** DEBUGGING DEFINITIONS *********************** 152 * Macros, preprocessor defines and variables used in debugging can make * 153 * code hard to read. Anything used exclusively for debugging purposes * 154 * is defined here to avoid having such mess scattered around the file. * 155 *************************************************************************/ 156 #ifdef PMAP_DEBUG 157 /* 158 * To aid the debugging process, macros should be expanded into smaller steps 159 * that accomplish the same goal, yet provide convenient places for placing 160 * breakpoints. When this code is compiled with PMAP_DEBUG mode defined, the 161 * 'INLINE' keyword is defined to an empty string. This way, any function 162 * defined to be a 'static INLINE' will become 'outlined' and compiled as 163 * a separate function, which is much easier to debug. 164 */ 165 #define INLINE /* nothing */ 166 167 /* 168 * It is sometimes convenient to watch the activity of a particular table 169 * in the system. The following variables are used for that purpose. 170 */ 171 a_tmgr_t *pmap_watch_atbl = 0; 172 b_tmgr_t *pmap_watch_btbl = 0; 173 c_tmgr_t *pmap_watch_ctbl = 0; 174 175 int pmap_debug = 0; 176 #define DPRINT(args) if (pmap_debug) printf args 177 178 #else /********** Stuff below is defined if NOT debugging **************/ 179 180 #define INLINE inline 181 #define DPRINT(args) /* nada */ 182 183 #endif /* PMAP_DEBUG */ 184 /*********************** END OF DEBUGGING DEFINITIONS ********************/ 185 186 /*** Management Structure - Memory Layout 187 * For every MMU table in the sun3x pmap system there must be a way to 188 * manage it; we must know which process is using it, what other tables 189 * depend on it, and whether or not it contains any locked pages. This 190 * is solved by the creation of 'table management' or 'tmgr' 191 * structures. One for each MMU table in the system. 192 * 193 * MAP OF MEMORY USED BY THE PMAP SYSTEM 194 * 195 * towards lower memory 196 * kernAbase -> +-------------------------------------------------------+ 197 * | Kernel MMU A level table | 198 * kernBbase -> +-------------------------------------------------------+ 199 * | Kernel MMU B level tables | 200 * kernCbase -> +-------------------------------------------------------+ 201 * | | 202 * | Kernel MMU C level tables | 203 * | | 204 * mmuCbase -> +-------------------------------------------------------+ 205 * | User MMU C level tables | 206 * mmuAbase -> +-------------------------------------------------------+ 207 * | | 208 * | User MMU A level tables | 209 * | | 210 * mmuBbase -> +-------------------------------------------------------+ 211 * | User MMU B level tables | 212 * tmgrAbase -> +-------------------------------------------------------+ 213 * | TMGR A level table structures | 214 * tmgrBbase -> +-------------------------------------------------------+ 215 * | TMGR B level table structures | 216 * tmgrCbase -> +-------------------------------------------------------+ 217 * | TMGR C level table structures | 218 * pvbase -> +-------------------------------------------------------+ 219 * | Physical to Virtual mapping table (list heads) | 220 * pvebase -> +-------------------------------------------------------+ 221 * | Physical to Virtual mapping table (list elements) | 222 * | | 223 * +-------------------------------------------------------+ 224 * towards higher memory 225 * 226 * For every A table in the MMU A area, there will be a corresponding 227 * a_tmgr structure in the TMGR A area. The same will be true for 228 * the B and C tables. This arrangement will make it easy to find the 229 * controling tmgr structure for any table in the system by use of 230 * (relatively) simple macros. 231 */ 232 233 /* 234 * Global variables for storing the base addresses for the areas 235 * labeled above. 236 */ 237 static vaddr_t kernAphys; 238 static mmu_long_dte_t *kernAbase; 239 static mmu_short_dte_t *kernBbase; 240 static mmu_short_pte_t *kernCbase; 241 static mmu_short_pte_t *mmuCbase; 242 static mmu_short_dte_t *mmuBbase; 243 static mmu_long_dte_t *mmuAbase; 244 static a_tmgr_t *Atmgrbase; 245 static b_tmgr_t *Btmgrbase; 246 static c_tmgr_t *Ctmgrbase; 247 static pv_t *pvbase; 248 static pv_elem_t *pvebase; 249 struct pmap kernel_pmap; 250 251 /* 252 * This holds the CRP currently loaded into the MMU. 253 */ 254 struct mmu_rootptr kernel_crp; 255 256 /* 257 * Just all around global variables. 258 */ 259 static TAILQ_HEAD(a_pool_head_struct, a_tmgr_struct) a_pool; 260 static TAILQ_HEAD(b_pool_head_struct, b_tmgr_struct) b_pool; 261 static TAILQ_HEAD(c_pool_head_struct, c_tmgr_struct) c_pool; 262 263 264 /* 265 * Flags used to mark the safety/availability of certain operations or 266 * resources. 267 */ 268 static boolean_t bootstrap_alloc_enabled = FALSE; /*Safe to use pmap_bootstrap_alloc().*/ 269 int tmp_vpages_inuse; /* Temporary virtual pages are in use */ 270 271 /* 272 * XXX: For now, retain the traditional variables that were 273 * used in the old pmap/vm interface (without NONCONTIG). 274 */ 275 /* Kernel virtual address space available: */ 276 vaddr_t virtual_avail, virtual_end; 277 /* Physical address space available: */ 278 paddr_t avail_start, avail_end; 279 280 /* This keep track of the end of the contiguously mapped range. */ 281 vaddr_t virtual_contig_end; 282 283 /* Physical address used by pmap_next_page() */ 284 paddr_t avail_next; 285 286 /* These are used by pmap_copy_page(), etc. */ 287 vaddr_t tmp_vpages[2]; 288 289 /* memory pool for pmap structures */ 290 struct pool pmap_pmap_pool; 291 292 /* 293 * The 3/80 is the only member of the sun3x family that has non-contiguous 294 * physical memory. Memory is divided into 4 banks which are physically 295 * locatable on the system board. Although the size of these banks varies 296 * with the size of memory they contain, their base addresses are 297 * permenently fixed. The following structure, which describes these 298 * banks, is initialized by pmap_bootstrap() after it reads from a similar 299 * structure provided by the ROM Monitor. 300 * 301 * For the other machines in the sun3x architecture which do have contiguous 302 * RAM, this list will have only one entry, which will describe the entire 303 * range of available memory. 304 */ 305 struct pmap_physmem_struct avail_mem[SUN3X_NPHYS_RAM_SEGS]; 306 u_int total_phys_mem; 307 308 /*************************************************************************/ 309 310 /* 311 * XXX - Should "tune" these based on statistics. 312 * 313 * My first guess about the relative numbers of these needed is 314 * based on the fact that a "typical" process will have several 315 * pages mapped at low virtual addresses (text, data, bss), then 316 * some mapped shared libraries, and then some stack pages mapped 317 * near the high end of the VA space. Each process can use only 318 * one A table, and most will use only two B tables (maybe three) 319 * and probably about four C tables. Therefore, the first guess 320 * at the relative numbers of these needed is 1:2:4 -gwr 321 * 322 * The number of C tables needed is closely related to the amount 323 * of physical memory available plus a certain amount attributable 324 * to the use of double mappings. With a few simulation statistics 325 * we can find a reasonably good estimation of this unknown value. 326 * Armed with that and the above ratios, we have a good idea of what 327 * is needed at each level. -j 328 * 329 * Note: It is not physical memory memory size, but the total mapped 330 * virtual space required by the combined working sets of all the 331 * currently _runnable_ processes. (Sleeping ones don't count.) 332 * The amount of physical memory should be irrelevant. -gwr 333 */ 334 #ifdef FIXED_NTABLES 335 #define NUM_A_TABLES 16 336 #define NUM_B_TABLES 32 337 #define NUM_C_TABLES 64 338 #else 339 unsigned int NUM_A_TABLES, NUM_B_TABLES, NUM_C_TABLES; 340 #endif /* FIXED_NTABLES */ 341 342 /* 343 * This determines our total virtual mapping capacity. 344 * Yes, it is a FIXED value so we can pre-allocate. 345 */ 346 #define NUM_USER_PTES (NUM_C_TABLES * MMU_C_TBL_SIZE) 347 348 /* 349 * The size of the Kernel Virtual Address Space (KVAS) 350 * for purposes of MMU table allocation is -KERNBASE 351 * (length from KERNBASE to 0xFFFFffff) 352 */ 353 #define KVAS_SIZE (-KERNBASE) 354 355 /* Numbers of kernel MMU tables to support KVAS_SIZE. */ 356 #define KERN_B_TABLES (KVAS_SIZE >> MMU_TIA_SHIFT) 357 #define KERN_C_TABLES (KVAS_SIZE >> MMU_TIB_SHIFT) 358 #define NUM_KERN_PTES (KVAS_SIZE >> MMU_TIC_SHIFT) 359 360 /*************************** MISCELANEOUS MACROS *************************/ 361 #define pmap_lock(pmap) simple_lock(&pmap->pm_lock) 362 #define pmap_unlock(pmap) simple_unlock(&pmap->pm_lock) 363 #define pmap_add_ref(pmap) ++pmap->pm_refcount 364 #define pmap_del_ref(pmap) --pmap->pm_refcount 365 #define pmap_refcount(pmap) pmap->pm_refcount 366 367 void *pmap_bootstrap_alloc(int); 368 369 static INLINE void *mmu_ptov __P((paddr_t)); 370 static INLINE paddr_t mmu_vtop __P((void *)); 371 372 #if 0 373 static INLINE a_tmgr_t * mmuA2tmgr __P((mmu_long_dte_t *)); 374 #endif /* 0 */ 375 static INLINE b_tmgr_t * mmuB2tmgr __P((mmu_short_dte_t *)); 376 static INLINE c_tmgr_t * mmuC2tmgr __P((mmu_short_pte_t *)); 377 378 static INLINE pv_t *pa2pv __P((paddr_t)); 379 static INLINE int pteidx __P((mmu_short_pte_t *)); 380 static INLINE pmap_t current_pmap __P((void)); 381 382 /* 383 * We can always convert between virtual and physical addresses 384 * for anything in the range [KERNBASE ... avail_start] because 385 * that range is GUARANTEED to be mapped linearly. 386 * We rely heavily upon this feature! 387 */ 388 static INLINE void * 389 mmu_ptov(pa) 390 paddr_t pa; 391 { 392 vaddr_t va; 393 394 va = (pa + KERNBASE); 395 #ifdef PMAP_DEBUG 396 if ((va < KERNBASE) || (va >= virtual_contig_end)) 397 panic("mmu_ptov"); 398 #endif 399 return ((void*)va); 400 } 401 402 static INLINE paddr_t 403 mmu_vtop(vva) 404 void *vva; 405 { 406 vaddr_t va; 407 408 va = (vaddr_t)vva; 409 #ifdef PMAP_DEBUG 410 if ((va < KERNBASE) || (va >= virtual_contig_end)) 411 panic("mmu_vtop"); 412 #endif 413 return (va - KERNBASE); 414 } 415 416 /* 417 * These macros map MMU tables to their corresponding manager structures. 418 * They are needed quite often because many of the pointers in the pmap 419 * system reference MMU tables and not the structures that control them. 420 * There needs to be a way to find one when given the other and these 421 * macros do so by taking advantage of the memory layout described above. 422 * Here's a quick step through the first macro, mmuA2tmgr(): 423 * 424 * 1) find the offset of the given MMU A table from the base of its table 425 * pool (table - mmuAbase). 426 * 2) convert this offset into a table index by dividing it by the 427 * size of one MMU 'A' table. (sizeof(mmu_long_dte_t) * MMU_A_TBL_SIZE) 428 * 3) use this index to select the corresponding 'A' table manager 429 * structure from the 'A' table manager pool (Atmgrbase[index]). 430 */ 431 /* This function is not currently used. */ 432 #if 0 433 static INLINE a_tmgr_t * 434 mmuA2tmgr(mmuAtbl) 435 mmu_long_dte_t *mmuAtbl; 436 { 437 int idx; 438 439 /* Which table is this in? */ 440 idx = (mmuAtbl - mmuAbase) / MMU_A_TBL_SIZE; 441 #ifdef PMAP_DEBUG 442 if ((idx < 0) || (idx >= NUM_A_TABLES)) 443 panic("mmuA2tmgr"); 444 #endif 445 return (&Atmgrbase[idx]); 446 } 447 #endif /* 0 */ 448 449 static INLINE b_tmgr_t * 450 mmuB2tmgr(mmuBtbl) 451 mmu_short_dte_t *mmuBtbl; 452 { 453 int idx; 454 455 /* Which table is this in? */ 456 idx = (mmuBtbl - mmuBbase) / MMU_B_TBL_SIZE; 457 #ifdef PMAP_DEBUG 458 if ((idx < 0) || (idx >= NUM_B_TABLES)) 459 panic("mmuB2tmgr"); 460 #endif 461 return (&Btmgrbase[idx]); 462 } 463 464 /* mmuC2tmgr INTERNAL 465 ** 466 * Given a pte known to belong to a C table, return the address of 467 * that table's management structure. 468 */ 469 static INLINE c_tmgr_t * 470 mmuC2tmgr(mmuCtbl) 471 mmu_short_pte_t *mmuCtbl; 472 { 473 int idx; 474 475 /* Which table is this in? */ 476 idx = (mmuCtbl - mmuCbase) / MMU_C_TBL_SIZE; 477 #ifdef PMAP_DEBUG 478 if ((idx < 0) || (idx >= NUM_C_TABLES)) 479 panic("mmuC2tmgr"); 480 #endif 481 return (&Ctmgrbase[idx]); 482 } 483 484 /* This is now a function call below. 485 * #define pa2pv(pa) \ 486 * (&pvbase[(unsigned long)\ 487 * m68k_btop(pa)\ 488 * ]) 489 */ 490 491 /* pa2pv INTERNAL 492 ** 493 * Return the pv_list_head element which manages the given physical 494 * address. 495 */ 496 static INLINE pv_t * 497 pa2pv(pa) 498 paddr_t pa; 499 { 500 struct pmap_physmem_struct *bank; 501 int idx; 502 503 bank = &avail_mem[0]; 504 while (pa >= bank->pmem_end) 505 bank = bank->pmem_next; 506 507 pa -= bank->pmem_start; 508 idx = bank->pmem_pvbase + m68k_btop(pa); 509 #ifdef PMAP_DEBUG 510 if ((idx < 0) || (idx >= physmem)) 511 panic("pa2pv"); 512 #endif 513 return &pvbase[idx]; 514 } 515 516 /* pteidx INTERNAL 517 ** 518 * Return the index of the given PTE within the entire fixed table of 519 * PTEs. 520 */ 521 static INLINE int 522 pteidx(pte) 523 mmu_short_pte_t *pte; 524 { 525 return (pte - kernCbase); 526 } 527 528 /* 529 * This just offers a place to put some debugging checks, 530 * and reduces the number of places "curproc" appears... 531 */ 532 static INLINE pmap_t 533 current_pmap() 534 { 535 struct proc *p; 536 struct vmspace *vm; 537 struct vm_map *map; 538 pmap_t pmap; 539 540 p = curproc; /* XXX */ 541 if (p == NULL) 542 pmap = &kernel_pmap; 543 else { 544 vm = p->p_vmspace; 545 map = &vm->vm_map; 546 pmap = vm_map_pmap(map); 547 } 548 549 return (pmap); 550 } 551 552 553 /*************************** FUNCTION DEFINITIONS ************************ 554 * These appear here merely for the compiler to enforce type checking on * 555 * all function calls. * 556 *************************************************************************/ 557 558 /** Internal functions 559 ** Most functions used only within this module are defined in 560 ** pmap_pvt.h (why not here if used only here?) 561 **/ 562 static void pmap_page_upload __P((void)); 563 564 /** Interface functions 565 ** - functions required by the Mach VM Pmap interface, with MACHINE_CONTIG 566 ** defined. 567 **/ 568 void pmap_pinit __P((pmap_t)); 569 void pmap_release __P((pmap_t)); 570 571 /********************************** CODE ******************************** 572 * Functions that are called from other parts of the kernel are labeled * 573 * as 'INTERFACE' functions. Functions that are only called from * 574 * within the pmap module are labeled as 'INTERNAL' functions. * 575 * Functions that are internal, but are not (currently) used at all are * 576 * labeled 'INTERNAL_X'. * 577 ************************************************************************/ 578 579 /* pmap_bootstrap INTERNAL 580 ** 581 * Initializes the pmap system. Called at boot time from 582 * locore2.c:_vm_init() 583 * 584 * Reminder: having a pmap_bootstrap_alloc() and also having the VM 585 * system implement pmap_steal_memory() is redundant. 586 * Don't release this code without removing one or the other! 587 */ 588 void 589 pmap_bootstrap(nextva) 590 vaddr_t nextva; 591 { 592 struct physmemory *membank; 593 struct pmap_physmem_struct *pmap_membank; 594 vaddr_t va, eva; 595 paddr_t pa; 596 int b, c, i, j; /* running table counts */ 597 int size, resvmem; 598 599 /* 600 * This function is called by __bootstrap after it has 601 * determined the type of machine and made the appropriate 602 * patches to the ROM vectors (XXX- I don't quite know what I meant 603 * by that.) It allocates and sets up enough of the pmap system 604 * to manage the kernel's address space. 605 */ 606 607 /* 608 * Determine the range of kernel virtual and physical 609 * space available. Note that we ABSOLUTELY DEPEND on 610 * the fact that the first bank of memory (4MB) is 611 * mapped linearly to KERNBASE (which we guaranteed in 612 * the first instructions of locore.s). 613 * That is plenty for our bootstrap work. 614 */ 615 virtual_avail = m68k_round_page(nextva); 616 virtual_contig_end = KERNBASE + 0x400000; /* +4MB */ 617 virtual_end = VM_MAX_KERNEL_ADDRESS; 618 /* Don't need avail_start til later. */ 619 620 /* We may now call pmap_bootstrap_alloc(). */ 621 bootstrap_alloc_enabled = TRUE; 622 623 /* 624 * This is a somewhat unwrapped loop to deal with 625 * copying the PROM's 'phsymem' banks into the pmap's 626 * banks. The following is always assumed: 627 * 1. There is always at least one bank of memory. 628 * 2. There is always a last bank of memory, and its 629 * pmem_next member must be set to NULL. 630 */ 631 membank = romVectorPtr->v_physmemory; 632 pmap_membank = avail_mem; 633 total_phys_mem = 0; 634 635 for (;;) { /* break on !membank */ 636 pmap_membank->pmem_start = membank->address; 637 pmap_membank->pmem_end = membank->address + membank->size; 638 total_phys_mem += membank->size; 639 membank = membank->next; 640 if (!membank) 641 break; 642 /* This silly syntax arises because pmap_membank 643 * is really a pre-allocated array, but it is put into 644 * use as a linked list. 645 */ 646 pmap_membank->pmem_next = pmap_membank + 1; 647 pmap_membank = pmap_membank->pmem_next; 648 } 649 /* This is the last element. */ 650 pmap_membank->pmem_next = NULL; 651 652 /* 653 * Note: total_phys_mem, physmem represent 654 * actual physical memory, including that 655 * reserved for the PROM monitor. 656 */ 657 physmem = btoc(total_phys_mem); 658 659 /* 660 * Avail_end is set to the first byte of physical memory 661 * after the end of the last bank. We use this only to 662 * determine if a physical address is "managed" memory. 663 * This address range should be reduced to prevent the 664 * physical pages needed by the PROM monitor from being used 665 * in the VM system. 666 */ 667 resvmem = total_phys_mem - *(romVectorPtr->memoryAvail); 668 resvmem = m68k_round_page(resvmem); 669 avail_end = pmap_membank->pmem_end - resvmem; 670 671 /* 672 * First allocate enough kernel MMU tables to map all 673 * of kernel virtual space from KERNBASE to 0xFFFFFFFF. 674 * Note: All must be aligned on 256 byte boundaries. 675 * Start with the level-A table (one of those). 676 */ 677 size = sizeof(mmu_long_dte_t) * MMU_A_TBL_SIZE; 678 kernAbase = pmap_bootstrap_alloc(size); 679 memset(kernAbase, 0, size); 680 681 /* Now the level-B kernel tables... */ 682 size = sizeof(mmu_short_dte_t) * MMU_B_TBL_SIZE * KERN_B_TABLES; 683 kernBbase = pmap_bootstrap_alloc(size); 684 memset(kernBbase, 0, size); 685 686 /* Now the level-C kernel tables... */ 687 size = sizeof(mmu_short_pte_t) * MMU_C_TBL_SIZE * KERN_C_TABLES; 688 kernCbase = pmap_bootstrap_alloc(size); 689 memset(kernCbase, 0, size); 690 /* 691 * Note: In order for the PV system to work correctly, the kernel 692 * and user-level C tables must be allocated contiguously. 693 * Nothing should be allocated between here and the allocation of 694 * mmuCbase below. XXX: Should do this as one allocation, and 695 * then compute a pointer for mmuCbase instead of this... 696 * 697 * Allocate user MMU tables. 698 * These must be contiguous with the preceding. 699 */ 700 701 #ifndef FIXED_NTABLES 702 /* 703 * The number of user-level C tables that should be allocated is 704 * related to the size of physical memory. In general, there should 705 * be enough tables to map four times the amount of available RAM. 706 * The extra amount is needed because some table space is wasted by 707 * fragmentation. 708 */ 709 NUM_C_TABLES = (total_phys_mem * 4) / (MMU_C_TBL_SIZE * MMU_PAGE_SIZE); 710 NUM_B_TABLES = NUM_C_TABLES / 2; 711 NUM_A_TABLES = NUM_B_TABLES / 2; 712 #endif /* !FIXED_NTABLES */ 713 714 size = sizeof(mmu_short_pte_t) * MMU_C_TBL_SIZE * NUM_C_TABLES; 715 mmuCbase = pmap_bootstrap_alloc(size); 716 717 size = sizeof(mmu_short_dte_t) * MMU_B_TBL_SIZE * NUM_B_TABLES; 718 mmuBbase = pmap_bootstrap_alloc(size); 719 720 size = sizeof(mmu_long_dte_t) * MMU_A_TBL_SIZE * NUM_A_TABLES; 721 mmuAbase = pmap_bootstrap_alloc(size); 722 723 /* 724 * Fill in the never-changing part of the kernel tables. 725 * For simplicity, the kernel's mappings will be editable as a 726 * flat array of page table entries at kernCbase. The 727 * higher level 'A' and 'B' tables must be initialized to point 728 * to this lower one. 729 */ 730 b = c = 0; 731 732 /* 733 * Invalidate all mappings below KERNBASE in the A table. 734 * This area has already been zeroed out, but it is good 735 * practice to explicitly show that we are interpreting 736 * it as a list of A table descriptors. 737 */ 738 for (i = 0; i < MMU_TIA(KERNBASE); i++) { 739 kernAbase[i].addr.raw = 0; 740 } 741 742 /* 743 * Set up the kernel A and B tables so that they will reference the 744 * correct spots in the contiguous table of PTEs allocated for the 745 * kernel's virtual memory space. 746 */ 747 for (i = MMU_TIA(KERNBASE); i < MMU_A_TBL_SIZE; i++) { 748 kernAbase[i].attr.raw = 749 MMU_LONG_DTE_LU | MMU_LONG_DTE_SUPV | MMU_DT_SHORT; 750 kernAbase[i].addr.raw = mmu_vtop(&kernBbase[b]); 751 752 for (j=0; j < MMU_B_TBL_SIZE; j++) { 753 kernBbase[b + j].attr.raw = mmu_vtop(&kernCbase[c]) 754 | MMU_DT_SHORT; 755 c += MMU_C_TBL_SIZE; 756 } 757 b += MMU_B_TBL_SIZE; 758 } 759 760 pmap_alloc_usermmu(); /* Allocate user MMU tables. */ 761 pmap_alloc_usertmgr(); /* Allocate user MMU table managers.*/ 762 pmap_alloc_pv(); /* Allocate physical->virtual map. */ 763 764 /* 765 * We are now done with pmap_bootstrap_alloc(). Round up 766 * `virtual_avail' to the nearest page, and set the flag 767 * to prevent use of pmap_bootstrap_alloc() hereafter. 768 */ 769 pmap_bootstrap_aalign(NBPG); 770 bootstrap_alloc_enabled = FALSE; 771 772 /* 773 * Now that we are done with pmap_bootstrap_alloc(), we 774 * must save the virtual and physical addresses of the 775 * end of the linearly mapped range, which are stored in 776 * virtual_contig_end and avail_start, respectively. 777 * These variables will never change after this point. 778 */ 779 virtual_contig_end = virtual_avail; 780 avail_start = virtual_avail - KERNBASE; 781 782 /* 783 * `avail_next' is a running pointer used by pmap_next_page() to 784 * keep track of the next available physical page to be handed 785 * to the VM system during its initialization, in which it 786 * asks for physical pages, one at a time. 787 */ 788 avail_next = avail_start; 789 790 /* 791 * Now allocate some virtual addresses, but not the physical pages 792 * behind them. Note that virtual_avail is already page-aligned. 793 * 794 * tmp_vpages[] is an array of two virtual pages used for temporary 795 * kernel mappings in the pmap module to facilitate various physical 796 * address-oritented operations. 797 */ 798 tmp_vpages[0] = virtual_avail; 799 virtual_avail += NBPG; 800 tmp_vpages[1] = virtual_avail; 801 virtual_avail += NBPG; 802 803 /** Initialize the PV system **/ 804 pmap_init_pv(); 805 806 /* 807 * Fill in the kernel_pmap structure and kernel_crp. 808 */ 809 kernAphys = mmu_vtop(kernAbase); 810 kernel_pmap.pm_a_tmgr = NULL; 811 kernel_pmap.pm_a_phys = kernAphys; 812 kernel_pmap.pm_refcount = 1; /* always in use */ 813 simple_lock_init(&kernel_pmap.pm_lock); 814 815 kernel_crp.rp_attr = MMU_LONG_DTE_LU | MMU_DT_LONG; 816 kernel_crp.rp_addr = kernAphys; 817 818 /* 819 * Now pmap_enter_kernel() may be used safely and will be 820 * the main interface used hereafter to modify the kernel's 821 * virtual address space. Note that since we are still running 822 * under the PROM's address table, none of these table modifications 823 * actually take effect until pmap_takeover_mmu() is called. 824 * 825 * Note: Our tables do NOT have the PROM linear mappings! 826 * Only the mappings created here exist in our tables, so 827 * remember to map anything we expect to use. 828 */ 829 va = (vaddr_t)KERNBASE; 830 pa = 0; 831 832 /* 833 * The first page of the kernel virtual address space is the msgbuf 834 * page. The page attributes (data, non-cached) are set here, while 835 * the address is assigned to this global pointer in cpu_startup(). 836 * It is non-cached, mostly due to paranoia. 837 */ 838 pmap_enter_kernel(va, pa|PMAP_NC, VM_PROT_ALL); 839 va += NBPG; pa += NBPG; 840 841 /* Next page is used as the temporary stack. */ 842 pmap_enter_kernel(va, pa, VM_PROT_ALL); 843 va += NBPG; pa += NBPG; 844 845 /* 846 * Map all of the kernel's text segment as read-only and cacheable. 847 * (Cacheable is implied by default). Unfortunately, the last bytes 848 * of kernel text and the first bytes of kernel data will often be 849 * sharing the same page. Therefore, the last page of kernel text 850 * has to be mapped as read/write, to accomodate the data. 851 */ 852 eva = m68k_trunc_page((vaddr_t)etext); 853 for (; va < eva; va += NBPG, pa += NBPG) 854 pmap_enter_kernel(va, pa, VM_PROT_READ|VM_PROT_EXECUTE); 855 856 /* 857 * Map all of the kernel's data as read/write and cacheable. 858 * This includes: data, BSS, symbols, and everything in the 859 * contiguous memory used by pmap_bootstrap_alloc() 860 */ 861 for (; pa < avail_start; va += NBPG, pa += NBPG) 862 pmap_enter_kernel(va, pa, VM_PROT_READ|VM_PROT_WRITE); 863 864 /* 865 * At this point we are almost ready to take over the MMU. But first 866 * we must save the PROM's address space in our map, as we call its 867 * routines and make references to its data later in the kernel. 868 */ 869 pmap_bootstrap_copyprom(); 870 pmap_takeover_mmu(); 871 pmap_bootstrap_setprom(); 872 873 /* Notify the VM system of our page size. */ 874 uvmexp.pagesize = NBPG; 875 uvm_setpagesize(); 876 877 pmap_page_upload(); 878 } 879 880 881 /* pmap_alloc_usermmu INTERNAL 882 ** 883 * Called from pmap_bootstrap() to allocate MMU tables that will 884 * eventually be used for user mappings. 885 */ 886 void 887 pmap_alloc_usermmu() 888 { 889 /* XXX: Moved into caller. */ 890 } 891 892 /* pmap_alloc_pv INTERNAL 893 ** 894 * Called from pmap_bootstrap() to allocate the physical 895 * to virtual mapping list. Each physical page of memory 896 * in the system has a corresponding element in this list. 897 */ 898 void 899 pmap_alloc_pv() 900 { 901 int i; 902 unsigned int total_mem; 903 904 /* 905 * Allocate a pv_head structure for every page of physical 906 * memory that will be managed by the system. Since memory on 907 * the 3/80 is non-contiguous, we cannot arrive at a total page 908 * count by subtraction of the lowest available address from the 909 * highest, but rather we have to step through each memory 910 * bank and add the number of pages in each to the total. 911 * 912 * At this time we also initialize the offset of each bank's 913 * starting pv_head within the pv_head list so that the physical 914 * memory state routines (pmap_is_referenced(), 915 * pmap_is_modified(), et al.) can quickly find coresponding 916 * pv_heads in spite of the non-contiguity. 917 */ 918 total_mem = 0; 919 for (i = 0; i < SUN3X_NPHYS_RAM_SEGS; i++) { 920 avail_mem[i].pmem_pvbase = m68k_btop(total_mem); 921 total_mem += avail_mem[i].pmem_end - 922 avail_mem[i].pmem_start; 923 if (avail_mem[i].pmem_next == NULL) 924 break; 925 } 926 pvbase = (pv_t *) pmap_bootstrap_alloc(sizeof(pv_t) * 927 m68k_btop(total_phys_mem)); 928 } 929 930 /* pmap_alloc_usertmgr INTERNAL 931 ** 932 * Called from pmap_bootstrap() to allocate the structures which 933 * facilitate management of user MMU tables. Each user MMU table 934 * in the system has one such structure associated with it. 935 */ 936 void 937 pmap_alloc_usertmgr() 938 { 939 /* Allocate user MMU table managers */ 940 /* It would be a lot simpler to just make these BSS, but */ 941 /* we may want to change their size at boot time... -j */ 942 Atmgrbase = (a_tmgr_t *) pmap_bootstrap_alloc(sizeof(a_tmgr_t) 943 * NUM_A_TABLES); 944 Btmgrbase = (b_tmgr_t *) pmap_bootstrap_alloc(sizeof(b_tmgr_t) 945 * NUM_B_TABLES); 946 Ctmgrbase = (c_tmgr_t *) pmap_bootstrap_alloc(sizeof(c_tmgr_t) 947 * NUM_C_TABLES); 948 949 /* 950 * Allocate PV list elements for the physical to virtual 951 * mapping system. 952 */ 953 pvebase = (pv_elem_t *) pmap_bootstrap_alloc( 954 sizeof(pv_elem_t) * (NUM_USER_PTES + NUM_KERN_PTES)); 955 } 956 957 /* pmap_bootstrap_copyprom() INTERNAL 958 ** 959 * Copy the PROM mappings into our own tables. Note, we 960 * can use physical addresses until __bootstrap returns. 961 */ 962 void 963 pmap_bootstrap_copyprom() 964 { 965 struct sunromvec *romp; 966 int *mon_ctbl; 967 mmu_short_pte_t *kpte; 968 int i, len; 969 970 romp = romVectorPtr; 971 972 /* 973 * Copy the mappings in SUN3X_MON_KDB_BASE...SUN3X_MONEND 974 * Note: mon_ctbl[0] maps SUN3X_MON_KDB_BASE 975 */ 976 mon_ctbl = *romp->monptaddr; 977 i = m68k_btop(SUN3X_MON_KDB_BASE - KERNBASE); 978 kpte = &kernCbase[i]; 979 len = m68k_btop(SUN3X_MONEND - SUN3X_MON_KDB_BASE); 980 981 for (i = 0; i < len; i++) { 982 kpte[i].attr.raw = mon_ctbl[i]; 983 } 984 985 /* 986 * Copy the mappings at MON_DVMA_BASE (to the end). 987 * Note, in here, mon_ctbl[0] maps MON_DVMA_BASE. 988 * Actually, we only want the last page, which the 989 * PROM has set up for use by the "ie" driver. 990 * (The i82686 needs its SCP there.) 991 * If we copy all the mappings, pmap_enter_kernel 992 * may complain about finding valid PTEs that are 993 * not recorded in our PV lists... 994 */ 995 mon_ctbl = *romp->shadowpteaddr; 996 i = m68k_btop(SUN3X_MON_DVMA_BASE - KERNBASE); 997 kpte = &kernCbase[i]; 998 len = m68k_btop(SUN3X_MON_DVMA_SIZE); 999 for (i = (len-1); i < len; i++) { 1000 kpte[i].attr.raw = mon_ctbl[i]; 1001 } 1002 } 1003 1004 /* pmap_takeover_mmu INTERNAL 1005 ** 1006 * Called from pmap_bootstrap() after it has copied enough of the 1007 * PROM mappings into the kernel map so that we can use our own 1008 * MMU table. 1009 */ 1010 void 1011 pmap_takeover_mmu() 1012 { 1013 1014 loadcrp(&kernel_crp); 1015 } 1016 1017 /* pmap_bootstrap_setprom() INTERNAL 1018 ** 1019 * Set the PROM mappings so it can see kernel space. 1020 * Note that physical addresses are used here, which 1021 * we can get away with because this runs with the 1022 * low 1GB set for transparent translation. 1023 */ 1024 void 1025 pmap_bootstrap_setprom() 1026 { 1027 mmu_long_dte_t *mon_dte; 1028 extern struct mmu_rootptr mon_crp; 1029 int i; 1030 1031 mon_dte = (mmu_long_dte_t *) mon_crp.rp_addr; 1032 for (i = MMU_TIA(KERNBASE); i < MMU_TIA(KERN_END); i++) { 1033 mon_dte[i].attr.raw = kernAbase[i].attr.raw; 1034 mon_dte[i].addr.raw = kernAbase[i].addr.raw; 1035 } 1036 } 1037 1038 1039 /* pmap_init INTERFACE 1040 ** 1041 * Called at the end of vm_init() to set up the pmap system to go 1042 * into full time operation. All initialization of kernel_pmap 1043 * should be already done by now, so this should just do things 1044 * needed for user-level pmaps to work. 1045 */ 1046 void 1047 pmap_init() 1048 { 1049 /** Initialize the manager pools **/ 1050 TAILQ_INIT(&a_pool); 1051 TAILQ_INIT(&b_pool); 1052 TAILQ_INIT(&c_pool); 1053 1054 /************************************************************** 1055 * Initialize all tmgr structures and MMU tables they manage. * 1056 **************************************************************/ 1057 /** Initialize A tables **/ 1058 pmap_init_a_tables(); 1059 /** Initialize B tables **/ 1060 pmap_init_b_tables(); 1061 /** Initialize C tables **/ 1062 pmap_init_c_tables(); 1063 1064 /** Initialize the pmap pools **/ 1065 pool_init(&pmap_pmap_pool, sizeof(struct pmap), 0, 0, 0, "pmappl", 1066 &pool_allocator_nointr); 1067 } 1068 1069 /* pmap_init_a_tables() INTERNAL 1070 ** 1071 * Initializes all A managers, their MMU A tables, and inserts 1072 * them into the A manager pool for use by the system. 1073 */ 1074 void 1075 pmap_init_a_tables() 1076 { 1077 int i; 1078 a_tmgr_t *a_tbl; 1079 1080 for (i=0; i < NUM_A_TABLES; i++) { 1081 /* Select the next available A manager from the pool */ 1082 a_tbl = &Atmgrbase[i]; 1083 1084 /* 1085 * Clear its parent entry. Set its wired and valid 1086 * entry count to zero. 1087 */ 1088 a_tbl->at_parent = NULL; 1089 a_tbl->at_wcnt = a_tbl->at_ecnt = 0; 1090 1091 /* Assign it the next available MMU A table from the pool */ 1092 a_tbl->at_dtbl = &mmuAbase[i * MMU_A_TBL_SIZE]; 1093 1094 /* 1095 * Initialize the MMU A table with the table in the `proc0', 1096 * or kernel, mapping. This ensures that every process has 1097 * the kernel mapped in the top part of its address space. 1098 */ 1099 memcpy(a_tbl->at_dtbl, kernAbase, MMU_A_TBL_SIZE * 1100 sizeof(mmu_long_dte_t)); 1101 1102 /* 1103 * Finally, insert the manager into the A pool, 1104 * making it ready to be used by the system. 1105 */ 1106 TAILQ_INSERT_TAIL(&a_pool, a_tbl, at_link); 1107 } 1108 } 1109 1110 /* pmap_init_b_tables() INTERNAL 1111 ** 1112 * Initializes all B table managers, their MMU B tables, and 1113 * inserts them into the B manager pool for use by the system. 1114 */ 1115 void 1116 pmap_init_b_tables() 1117 { 1118 int i,j; 1119 b_tmgr_t *b_tbl; 1120 1121 for (i=0; i < NUM_B_TABLES; i++) { 1122 /* Select the next available B manager from the pool */ 1123 b_tbl = &Btmgrbase[i]; 1124 1125 b_tbl->bt_parent = NULL; /* clear its parent, */ 1126 b_tbl->bt_pidx = 0; /* parent index, */ 1127 b_tbl->bt_wcnt = 0; /* wired entry count, */ 1128 b_tbl->bt_ecnt = 0; /* valid entry count. */ 1129 1130 /* Assign it the next available MMU B table from the pool */ 1131 b_tbl->bt_dtbl = &mmuBbase[i * MMU_B_TBL_SIZE]; 1132 1133 /* Invalidate every descriptor in the table */ 1134 for (j=0; j < MMU_B_TBL_SIZE; j++) 1135 b_tbl->bt_dtbl[j].attr.raw = MMU_DT_INVALID; 1136 1137 /* Insert the manager into the B pool */ 1138 TAILQ_INSERT_TAIL(&b_pool, b_tbl, bt_link); 1139 } 1140 } 1141 1142 /* pmap_init_c_tables() INTERNAL 1143 ** 1144 * Initializes all C table managers, their MMU C tables, and 1145 * inserts them into the C manager pool for use by the system. 1146 */ 1147 void 1148 pmap_init_c_tables() 1149 { 1150 int i,j; 1151 c_tmgr_t *c_tbl; 1152 1153 for (i=0; i < NUM_C_TABLES; i++) { 1154 /* Select the next available C manager from the pool */ 1155 c_tbl = &Ctmgrbase[i]; 1156 1157 c_tbl->ct_parent = NULL; /* clear its parent, */ 1158 c_tbl->ct_pidx = 0; /* parent index, */ 1159 c_tbl->ct_wcnt = 0; /* wired entry count, */ 1160 c_tbl->ct_ecnt = 0; /* valid entry count, */ 1161 c_tbl->ct_pmap = NULL; /* parent pmap, */ 1162 c_tbl->ct_va = 0; /* base of managed range */ 1163 1164 /* Assign it the next available MMU C table from the pool */ 1165 c_tbl->ct_dtbl = &mmuCbase[i * MMU_C_TBL_SIZE]; 1166 1167 for (j=0; j < MMU_C_TBL_SIZE; j++) 1168 c_tbl->ct_dtbl[j].attr.raw = MMU_DT_INVALID; 1169 1170 TAILQ_INSERT_TAIL(&c_pool, c_tbl, ct_link); 1171 } 1172 } 1173 1174 /* pmap_init_pv() INTERNAL 1175 ** 1176 * Initializes the Physical to Virtual mapping system. 1177 */ 1178 void 1179 pmap_init_pv() 1180 { 1181 int i; 1182 1183 /* Initialize every PV head. */ 1184 for (i = 0; i < m68k_btop(total_phys_mem); i++) { 1185 pvbase[i].pv_idx = PVE_EOL; /* Indicate no mappings */ 1186 pvbase[i].pv_flags = 0; /* Zero out page flags */ 1187 } 1188 } 1189 1190 /* get_a_table INTERNAL 1191 ** 1192 * Retrieve and return a level A table for use in a user map. 1193 */ 1194 a_tmgr_t * 1195 get_a_table() 1196 { 1197 a_tmgr_t *tbl; 1198 pmap_t pmap; 1199 1200 /* Get the top A table in the pool */ 1201 tbl = a_pool.tqh_first; 1202 if (tbl == NULL) { 1203 /* 1204 * XXX - Instead of panicing here and in other get_x_table 1205 * functions, we do have the option of sleeping on the head of 1206 * the table pool. Any function which updates the table pool 1207 * would then issue a wakeup() on the head, thus waking up any 1208 * processes waiting for a table. 1209 * 1210 * Actually, the place to sleep would be when some process 1211 * asks for a "wired" mapping that would run us short of 1212 * mapping resources. This design DEPENDS on always having 1213 * some mapping resources in the pool for stealing, so we 1214 * must make sure we NEVER let the pool become empty. -gwr 1215 */ 1216 panic("get_a_table: out of A tables."); 1217 } 1218 1219 TAILQ_REMOVE(&a_pool, tbl, at_link); 1220 /* 1221 * If the table has a non-null parent pointer then it is in use. 1222 * Forcibly abduct it from its parent and clear its entries. 1223 * No re-entrancy worries here. This table would not be in the 1224 * table pool unless it was available for use. 1225 * 1226 * Note that the second argument to free_a_table() is FALSE. This 1227 * indicates that the table should not be relinked into the A table 1228 * pool. That is a job for the function that called us. 1229 */ 1230 if (tbl->at_parent) { 1231 pmap = tbl->at_parent; 1232 free_a_table(tbl, FALSE); 1233 pmap->pm_a_tmgr = NULL; 1234 pmap->pm_a_phys = kernAphys; 1235 } 1236 return tbl; 1237 } 1238 1239 /* get_b_table INTERNAL 1240 ** 1241 * Return a level B table for use. 1242 */ 1243 b_tmgr_t * 1244 get_b_table() 1245 { 1246 b_tmgr_t *tbl; 1247 1248 /* See 'get_a_table' for comments. */ 1249 tbl = b_pool.tqh_first; 1250 if (tbl == NULL) 1251 panic("get_b_table: out of B tables."); 1252 TAILQ_REMOVE(&b_pool, tbl, bt_link); 1253 if (tbl->bt_parent) { 1254 tbl->bt_parent->at_dtbl[tbl->bt_pidx].attr.raw = MMU_DT_INVALID; 1255 tbl->bt_parent->at_ecnt--; 1256 free_b_table(tbl, FALSE); 1257 } 1258 return tbl; 1259 } 1260 1261 /* get_c_table INTERNAL 1262 ** 1263 * Return a level C table for use. 1264 */ 1265 c_tmgr_t * 1266 get_c_table() 1267 { 1268 c_tmgr_t *tbl; 1269 1270 /* See 'get_a_table' for comments */ 1271 tbl = c_pool.tqh_first; 1272 if (tbl == NULL) 1273 panic("get_c_table: out of C tables."); 1274 TAILQ_REMOVE(&c_pool, tbl, ct_link); 1275 if (tbl->ct_parent) { 1276 tbl->ct_parent->bt_dtbl[tbl->ct_pidx].attr.raw = MMU_DT_INVALID; 1277 tbl->ct_parent->bt_ecnt--; 1278 free_c_table(tbl, FALSE); 1279 } 1280 return tbl; 1281 } 1282 1283 /* 1284 * The following 'free_table' and 'steal_table' functions are called to 1285 * detach tables from their current obligations (parents and children) and 1286 * prepare them for reuse in another mapping. 1287 * 1288 * Free_table is used when the calling function will handle the fate 1289 * of the parent table, such as returning it to the free pool when it has 1290 * no valid entries. Functions that do not want to handle this should 1291 * call steal_table, in which the parent table's descriptors and entry 1292 * count are automatically modified when this table is removed. 1293 */ 1294 1295 /* free_a_table INTERNAL 1296 ** 1297 * Unmaps the given A table and all child tables from their current 1298 * mappings. Returns the number of pages that were invalidated. 1299 * If 'relink' is true, the function will return the table to the head 1300 * of the available table pool. 1301 * 1302 * Cache note: The MC68851 will automatically flush all 1303 * descriptors derived from a given A table from its 1304 * Automatic Translation Cache (ATC) if we issue a 1305 * 'PFLUSHR' instruction with the base address of the 1306 * table. This function should do, and does so. 1307 * Note note: We are using an MC68030 - there is no 1308 * PFLUSHR. 1309 */ 1310 int 1311 free_a_table(a_tbl, relink) 1312 a_tmgr_t *a_tbl; 1313 boolean_t relink; 1314 { 1315 int i, removed_cnt; 1316 mmu_long_dte_t *dte; 1317 mmu_short_dte_t *dtbl; 1318 b_tmgr_t *tmgr; 1319 1320 /* 1321 * Flush the ATC cache of all cached descriptors derived 1322 * from this table. 1323 * Sun3x does not use 68851's cached table feature 1324 * flush_atc_crp(mmu_vtop(a_tbl->dte)); 1325 */ 1326 1327 /* 1328 * Remove any pending cache flushes that were designated 1329 * for the pmap this A table belongs to. 1330 * a_tbl->parent->atc_flushq[0] = 0; 1331 * Not implemented in sun3x. 1332 */ 1333 1334 /* 1335 * All A tables in the system should retain a map for the 1336 * kernel. If the table contains any valid descriptors 1337 * (other than those for the kernel area), invalidate them all, 1338 * stopping short of the kernel's entries. 1339 */ 1340 removed_cnt = 0; 1341 if (a_tbl->at_ecnt) { 1342 dte = a_tbl->at_dtbl; 1343 for (i=0; i < MMU_TIA(KERNBASE); i++) { 1344 /* 1345 * If a table entry points to a valid B table, free 1346 * it and its children. 1347 */ 1348 if (MMU_VALID_DT(dte[i])) { 1349 /* 1350 * The following block does several things, 1351 * from innermost expression to the 1352 * outermost: 1353 * 1) It extracts the base (cc 1996) 1354 * address of the B table pointed 1355 * to in the A table entry dte[i]. 1356 * 2) It converts this base address into 1357 * the virtual address it can be 1358 * accessed with. (all MMU tables point 1359 * to physical addresses.) 1360 * 3) It finds the corresponding manager 1361 * structure which manages this MMU table. 1362 * 4) It frees the manager structure. 1363 * (This frees the MMU table and all 1364 * child tables. See 'free_b_table' for 1365 * details.) 1366 */ 1367 dtbl = mmu_ptov(dte[i].addr.raw); 1368 tmgr = mmuB2tmgr(dtbl); 1369 removed_cnt += free_b_table(tmgr, TRUE); 1370 dte[i].attr.raw = MMU_DT_INVALID; 1371 } 1372 } 1373 a_tbl->at_ecnt = 0; 1374 } 1375 if (relink) { 1376 a_tbl->at_parent = NULL; 1377 TAILQ_REMOVE(&a_pool, a_tbl, at_link); 1378 TAILQ_INSERT_HEAD(&a_pool, a_tbl, at_link); 1379 } 1380 return removed_cnt; 1381 } 1382 1383 /* free_b_table INTERNAL 1384 ** 1385 * Unmaps the given B table and all its children from their current 1386 * mappings. Returns the number of pages that were invalidated. 1387 * (For comments, see 'free_a_table()'). 1388 */ 1389 int 1390 free_b_table(b_tbl, relink) 1391 b_tmgr_t *b_tbl; 1392 boolean_t relink; 1393 { 1394 int i, removed_cnt; 1395 mmu_short_dte_t *dte; 1396 mmu_short_pte_t *dtbl; 1397 c_tmgr_t *tmgr; 1398 1399 removed_cnt = 0; 1400 if (b_tbl->bt_ecnt) { 1401 dte = b_tbl->bt_dtbl; 1402 for (i=0; i < MMU_B_TBL_SIZE; i++) { 1403 if (MMU_VALID_DT(dte[i])) { 1404 dtbl = mmu_ptov(MMU_DTE_PA(dte[i])); 1405 tmgr = mmuC2tmgr(dtbl); 1406 removed_cnt += free_c_table(tmgr, TRUE); 1407 dte[i].attr.raw = MMU_DT_INVALID; 1408 } 1409 } 1410 b_tbl->bt_ecnt = 0; 1411 } 1412 1413 if (relink) { 1414 b_tbl->bt_parent = NULL; 1415 TAILQ_REMOVE(&b_pool, b_tbl, bt_link); 1416 TAILQ_INSERT_HEAD(&b_pool, b_tbl, bt_link); 1417 } 1418 return removed_cnt; 1419 } 1420 1421 /* free_c_table INTERNAL 1422 ** 1423 * Unmaps the given C table from use and returns it to the pool for 1424 * re-use. Returns the number of pages that were invalidated. 1425 * 1426 * This function preserves any physical page modification information 1427 * contained in the page descriptors within the C table by calling 1428 * 'pmap_remove_pte().' 1429 */ 1430 int 1431 free_c_table(c_tbl, relink) 1432 c_tmgr_t *c_tbl; 1433 boolean_t relink; 1434 { 1435 int i, removed_cnt; 1436 1437 removed_cnt = 0; 1438 if (c_tbl->ct_ecnt) { 1439 for (i=0; i < MMU_C_TBL_SIZE; i++) { 1440 if (MMU_VALID_DT(c_tbl->ct_dtbl[i])) { 1441 pmap_remove_pte(&c_tbl->ct_dtbl[i]); 1442 removed_cnt++; 1443 } 1444 } 1445 c_tbl->ct_ecnt = 0; 1446 } 1447 1448 if (relink) { 1449 c_tbl->ct_parent = NULL; 1450 TAILQ_REMOVE(&c_pool, c_tbl, ct_link); 1451 TAILQ_INSERT_HEAD(&c_pool, c_tbl, ct_link); 1452 } 1453 return removed_cnt; 1454 } 1455 1456 1457 /* pmap_remove_pte INTERNAL 1458 ** 1459 * Unmap the given pte and preserve any page modification 1460 * information by transfering it to the pv head of the 1461 * physical page it maps to. This function does not update 1462 * any reference counts because it is assumed that the calling 1463 * function will do so. 1464 */ 1465 void 1466 pmap_remove_pte(pte) 1467 mmu_short_pte_t *pte; 1468 { 1469 u_short pv_idx, targ_idx; 1470 paddr_t pa; 1471 pv_t *pv; 1472 1473 pa = MMU_PTE_PA(*pte); 1474 if (is_managed(pa)) { 1475 pv = pa2pv(pa); 1476 targ_idx = pteidx(pte); /* Index of PTE being removed */ 1477 1478 /* 1479 * If the PTE being removed is the first (or only) PTE in 1480 * the list of PTEs currently mapped to this page, remove the 1481 * PTE by changing the index found on the PV head. Otherwise 1482 * a linear search through the list will have to be executed 1483 * in order to find the PVE which points to the PTE being 1484 * removed, so that it may be modified to point to its new 1485 * neighbor. 1486 */ 1487 1488 pv_idx = pv->pv_idx; /* Index of first PTE in PV list */ 1489 if (pv_idx == targ_idx) { 1490 pv->pv_idx = pvebase[targ_idx].pve_next; 1491 } else { 1492 1493 /* 1494 * Find the PV element pointing to the target 1495 * element. Note: may have pv_idx==PVE_EOL 1496 */ 1497 1498 for (;;) { 1499 if (pv_idx == PVE_EOL) { 1500 goto pv_not_found; 1501 } 1502 if (pvebase[pv_idx].pve_next == targ_idx) 1503 break; 1504 pv_idx = pvebase[pv_idx].pve_next; 1505 } 1506 1507 /* 1508 * At this point, pv_idx is the index of the PV 1509 * element just before the target element in the list. 1510 * Unlink the target. 1511 */ 1512 1513 pvebase[pv_idx].pve_next = pvebase[targ_idx].pve_next; 1514 } 1515 1516 /* 1517 * Save the mod/ref bits of the pte by simply 1518 * ORing the entire pte onto the pv_flags member 1519 * of the pv structure. 1520 * There is no need to use a separate bit pattern 1521 * for usage information on the pv head than that 1522 * which is used on the MMU ptes. 1523 */ 1524 1525 pv_not_found: 1526 pv->pv_flags |= (u_short) pte->attr.raw; 1527 } 1528 pte->attr.raw = MMU_DT_INVALID; 1529 } 1530 1531 /* pmap_stroll INTERNAL 1532 ** 1533 * Retrieve the addresses of all table managers involved in the mapping of 1534 * the given virtual address. If the table walk completed sucessfully, 1535 * return TRUE. If it was only partially sucessful, return FALSE. 1536 * The table walk performed by this function is important to many other 1537 * functions in this module. 1538 * 1539 * Note: This function ought to be easier to read. 1540 */ 1541 boolean_t 1542 pmap_stroll(pmap, va, a_tbl, b_tbl, c_tbl, pte, a_idx, b_idx, pte_idx) 1543 pmap_t pmap; 1544 vaddr_t va; 1545 a_tmgr_t **a_tbl; 1546 b_tmgr_t **b_tbl; 1547 c_tmgr_t **c_tbl; 1548 mmu_short_pte_t **pte; 1549 int *a_idx, *b_idx, *pte_idx; 1550 { 1551 mmu_long_dte_t *a_dte; /* A: long descriptor table */ 1552 mmu_short_dte_t *b_dte; /* B: short descriptor table */ 1553 1554 if (pmap == pmap_kernel()) 1555 return FALSE; 1556 1557 /* Does the given pmap have its own A table? */ 1558 *a_tbl = pmap->pm_a_tmgr; 1559 if (*a_tbl == NULL) 1560 return FALSE; /* No. Return unknown. */ 1561 /* Does the A table have a valid B table 1562 * under the corresponding table entry? 1563 */ 1564 *a_idx = MMU_TIA(va); 1565 a_dte = &((*a_tbl)->at_dtbl[*a_idx]); 1566 if (!MMU_VALID_DT(*a_dte)) 1567 return FALSE; /* No. Return unknown. */ 1568 /* Yes. Extract B table from the A table. */ 1569 *b_tbl = mmuB2tmgr(mmu_ptov(a_dte->addr.raw)); 1570 /* Does the B table have a valid C table 1571 * under the corresponding table entry? 1572 */ 1573 *b_idx = MMU_TIB(va); 1574 b_dte = &((*b_tbl)->bt_dtbl[*b_idx]); 1575 if (!MMU_VALID_DT(*b_dte)) 1576 return FALSE; /* No. Return unknown. */ 1577 /* Yes. Extract C table from the B table. */ 1578 *c_tbl = mmuC2tmgr(mmu_ptov(MMU_DTE_PA(*b_dte))); 1579 *pte_idx = MMU_TIC(va); 1580 *pte = &((*c_tbl)->ct_dtbl[*pte_idx]); 1581 1582 return TRUE; 1583 } 1584 1585 /* pmap_enter INTERFACE 1586 ** 1587 * Called by the kernel to map a virtual address 1588 * to a physical address in the given process map. 1589 * 1590 * Note: this function should apply an exclusive lock 1591 * on the pmap system for its duration. (it certainly 1592 * would save my hair!!) 1593 * This function ought to be easier to read. 1594 */ 1595 int 1596 pmap_enter(pmap, va, pa, prot, flags) 1597 pmap_t pmap; 1598 vaddr_t va; 1599 paddr_t pa; 1600 vm_prot_t prot; 1601 int flags; 1602 { 1603 boolean_t insert, managed; /* Marks the need for PV insertion.*/ 1604 u_short nidx; /* PV list index */ 1605 int mapflags; /* Flags for the mapping (see NOTE1) */ 1606 u_int a_idx, b_idx, pte_idx; /* table indices */ 1607 a_tmgr_t *a_tbl; /* A: long descriptor table manager */ 1608 b_tmgr_t *b_tbl; /* B: short descriptor table manager */ 1609 c_tmgr_t *c_tbl; /* C: short page table manager */ 1610 mmu_long_dte_t *a_dte; /* A: long descriptor table */ 1611 mmu_short_dte_t *b_dte; /* B: short descriptor table */ 1612 mmu_short_pte_t *c_pte; /* C: short page descriptor table */ 1613 pv_t *pv; /* pv list head */ 1614 boolean_t wired; /* is the mapping to be wired? */ 1615 enum {NONE, NEWA, NEWB, NEWC} llevel; /* used at end */ 1616 1617 if (pmap == pmap_kernel()) { 1618 pmap_enter_kernel(va, pa, prot); 1619 return 0; 1620 } 1621 1622 /* 1623 * Determine if the mapping should be wired. 1624 */ 1625 wired = ((flags & PMAP_WIRED) != 0); 1626 1627 /* 1628 * NOTE1: 1629 * 1630 * On November 13, 1999, someone changed the pmap_enter() API such 1631 * that it now accepts a 'flags' argument. This new argument 1632 * contains bit-flags for the architecture-independent (UVM) system to 1633 * use in signalling certain mapping requirements to the architecture- 1634 * dependent (pmap) system. The argument it replaces, 'wired', is now 1635 * one of the flags within it. 1636 * 1637 * In addition to flags signaled by the architecture-independent 1638 * system, parts of the architecture-dependent section of the sun3x 1639 * kernel pass their own flags in the lower, unused bits of the 1640 * physical address supplied to this function. These flags are 1641 * extracted and stored in the temporary variable 'mapflags'. 1642 * 1643 * Extract sun3x specific flags from the physical address. 1644 */ 1645 mapflags = (pa & ~MMU_PAGE_MASK); 1646 pa &= MMU_PAGE_MASK; 1647 1648 /* 1649 * Determine if the physical address being mapped is on-board RAM. 1650 * Any other area of the address space is likely to belong to a 1651 * device and hence it would be disasterous to cache its contents. 1652 */ 1653 if ((managed = is_managed(pa)) == FALSE) 1654 mapflags |= PMAP_NC; 1655 1656 /* 1657 * For user mappings we walk along the MMU tables of the given 1658 * pmap, reaching a PTE which describes the virtual page being 1659 * mapped or changed. If any level of the walk ends in an invalid 1660 * entry, a table must be allocated and the entry must be updated 1661 * to point to it. 1662 * There is a bit of confusion as to whether this code must be 1663 * re-entrant. For now we will assume it is. To support 1664 * re-entrancy we must unlink tables from the table pool before 1665 * we assume we may use them. Tables are re-linked into the pool 1666 * when we are finished with them at the end of the function. 1667 * But I don't feel like doing that until we have proof that this 1668 * needs to be re-entrant. 1669 * 'llevel' records which tables need to be relinked. 1670 */ 1671 llevel = NONE; 1672 1673 /* 1674 * Step 1 - Retrieve the A table from the pmap. If it has no 1675 * A table, allocate a new one from the available pool. 1676 */ 1677 1678 a_tbl = pmap->pm_a_tmgr; 1679 if (a_tbl == NULL) { 1680 /* 1681 * This pmap does not currently have an A table. Allocate 1682 * a new one. 1683 */ 1684 a_tbl = get_a_table(); 1685 a_tbl->at_parent = pmap; 1686 1687 /* 1688 * Assign this new A table to the pmap, and calculate its 1689 * physical address so that loadcrp() can be used to make 1690 * the table active. 1691 */ 1692 pmap->pm_a_tmgr = a_tbl; 1693 pmap->pm_a_phys = mmu_vtop(a_tbl->at_dtbl); 1694 1695 /* 1696 * If the process receiving a new A table is the current 1697 * process, we are responsible for setting the MMU so that 1698 * it becomes the current address space. This only adds 1699 * new mappings, so no need to flush anything. 1700 */ 1701 if (pmap == current_pmap()) { 1702 kernel_crp.rp_addr = pmap->pm_a_phys; 1703 loadcrp(&kernel_crp); 1704 } 1705 1706 if (!wired) 1707 llevel = NEWA; 1708 } else { 1709 /* 1710 * Use the A table already allocated for this pmap. 1711 * Unlink it from the A table pool if necessary. 1712 */ 1713 if (wired && !a_tbl->at_wcnt) 1714 TAILQ_REMOVE(&a_pool, a_tbl, at_link); 1715 } 1716 1717 /* 1718 * Step 2 - Walk into the B table. If there is no valid B table, 1719 * allocate one. 1720 */ 1721 1722 a_idx = MMU_TIA(va); /* Calculate the TIA of the VA. */ 1723 a_dte = &a_tbl->at_dtbl[a_idx]; /* Retrieve descriptor from table */ 1724 if (MMU_VALID_DT(*a_dte)) { /* Is the descriptor valid? */ 1725 /* The descriptor is valid. Use the B table it points to. */ 1726 /************************************* 1727 * a_idx * 1728 * v * 1729 * a_tbl -> +-+-+-+-+-+-+-+-+-+-+-+- * 1730 * | | | | | | | | | | | | * 1731 * +-+-+-+-+-+-+-+-+-+-+-+- * 1732 * | * 1733 * \- b_tbl -> +-+- * 1734 * | | * 1735 * +-+- * 1736 *************************************/ 1737 b_dte = mmu_ptov(a_dte->addr.raw); 1738 b_tbl = mmuB2tmgr(b_dte); 1739 1740 /* 1741 * If the requested mapping must be wired, but this table 1742 * being used to map it is not, the table must be removed 1743 * from the available pool and its wired entry count 1744 * incremented. 1745 */ 1746 if (wired && !b_tbl->bt_wcnt) { 1747 TAILQ_REMOVE(&b_pool, b_tbl, bt_link); 1748 a_tbl->at_wcnt++; 1749 } 1750 } else { 1751 /* The descriptor is invalid. Allocate a new B table. */ 1752 b_tbl = get_b_table(); 1753 1754 /* Point the parent A table descriptor to this new B table. */ 1755 a_dte->addr.raw = mmu_vtop(b_tbl->bt_dtbl); 1756 a_dte->attr.raw = MMU_LONG_DTE_LU | MMU_DT_SHORT; 1757 a_tbl->at_ecnt++; /* Update parent's valid entry count */ 1758 1759 /* Create the necessary back references to the parent table */ 1760 b_tbl->bt_parent = a_tbl; 1761 b_tbl->bt_pidx = a_idx; 1762 1763 /* 1764 * If this table is to be wired, make sure the parent A table 1765 * wired count is updated to reflect that it has another wired 1766 * entry. 1767 */ 1768 if (wired) 1769 a_tbl->at_wcnt++; 1770 else if (llevel == NONE) 1771 llevel = NEWB; 1772 } 1773 1774 /* 1775 * Step 3 - Walk into the C table, if there is no valid C table, 1776 * allocate one. 1777 */ 1778 1779 b_idx = MMU_TIB(va); /* Calculate the TIB of the VA */ 1780 b_dte = &b_tbl->bt_dtbl[b_idx]; /* Retrieve descriptor from table */ 1781 if (MMU_VALID_DT(*b_dte)) { /* Is the descriptor valid? */ 1782 /* The descriptor is valid. Use the C table it points to. */ 1783 /************************************** 1784 * c_idx * 1785 * | v * 1786 * \- b_tbl -> +-+-+-+-+-+-+-+-+-+-+- * 1787 * | | | | | | | | | | | * 1788 * +-+-+-+-+-+-+-+-+-+-+- * 1789 * | * 1790 * \- c_tbl -> +-+-- * 1791 * | | | * 1792 * +-+-- * 1793 **************************************/ 1794 c_pte = mmu_ptov(MMU_PTE_PA(*b_dte)); 1795 c_tbl = mmuC2tmgr(c_pte); 1796 1797 /* If mapping is wired and table is not */ 1798 if (wired && !c_tbl->ct_wcnt) { 1799 TAILQ_REMOVE(&c_pool, c_tbl, ct_link); 1800 b_tbl->bt_wcnt++; 1801 } 1802 } else { 1803 /* The descriptor is invalid. Allocate a new C table. */ 1804 c_tbl = get_c_table(); 1805 1806 /* Point the parent B table descriptor to this new C table. */ 1807 b_dte->attr.raw = mmu_vtop(c_tbl->ct_dtbl); 1808 b_dte->attr.raw |= MMU_DT_SHORT; 1809 b_tbl->bt_ecnt++; /* Update parent's valid entry count */ 1810 1811 /* Create the necessary back references to the parent table */ 1812 c_tbl->ct_parent = b_tbl; 1813 c_tbl->ct_pidx = b_idx; 1814 /* 1815 * Store the pmap and base virtual managed address for faster 1816 * retrieval in the PV functions. 1817 */ 1818 c_tbl->ct_pmap = pmap; 1819 c_tbl->ct_va = (va & (MMU_TIA_MASK|MMU_TIB_MASK)); 1820 1821 /* 1822 * If this table is to be wired, make sure the parent B table 1823 * wired count is updated to reflect that it has another wired 1824 * entry. 1825 */ 1826 if (wired) 1827 b_tbl->bt_wcnt++; 1828 else if (llevel == NONE) 1829 llevel = NEWC; 1830 } 1831 1832 /* 1833 * Step 4 - Deposit a page descriptor (PTE) into the appropriate 1834 * slot of the C table, describing the PA to which the VA is mapped. 1835 */ 1836 1837 pte_idx = MMU_TIC(va); 1838 c_pte = &c_tbl->ct_dtbl[pte_idx]; 1839 if (MMU_VALID_DT(*c_pte)) { /* Is the entry currently valid? */ 1840 /* 1841 * The PTE is currently valid. This particular call 1842 * is just a synonym for one (or more) of the following 1843 * operations: 1844 * change protection of a page 1845 * change wiring status of a page 1846 * remove the mapping of a page 1847 * 1848 * XXX - Semi critical: This code should unwire the PTE 1849 * and, possibly, associated parent tables if this is a 1850 * change wiring operation. Currently it does not. 1851 * 1852 * This may be ok if pmap_unwire() is the only 1853 * interface used to UNWIRE a page. 1854 */ 1855 1856 /* First check if this is a wiring operation. */ 1857 if (wired && (c_pte->attr.raw & MMU_SHORT_PTE_WIRED)) { 1858 /* 1859 * The PTE is already wired. To prevent it from being 1860 * counted as a new wiring operation, reset the 'wired' 1861 * variable. 1862 */ 1863 wired = FALSE; 1864 } 1865 1866 /* Is the new address the same as the old? */ 1867 if (MMU_PTE_PA(*c_pte) == pa) { 1868 /* 1869 * Yes, mark that it does not need to be reinserted 1870 * into the PV list. 1871 */ 1872 insert = FALSE; 1873 1874 /* 1875 * Clear all but the modified, referenced and wired 1876 * bits on the PTE. 1877 */ 1878 c_pte->attr.raw &= (MMU_SHORT_PTE_M 1879 | MMU_SHORT_PTE_USED | MMU_SHORT_PTE_WIRED); 1880 } else { 1881 /* No, remove the old entry */ 1882 pmap_remove_pte(c_pte); 1883 insert = TRUE; 1884 } 1885 1886 /* 1887 * TLB flush is only necessary if modifying current map. 1888 * However, in pmap_enter(), the pmap almost always IS 1889 * the current pmap, so don't even bother to check. 1890 */ 1891 TBIS(va); 1892 } else { 1893 /* 1894 * The PTE is invalid. Increment the valid entry count in 1895 * the C table manager to reflect the addition of a new entry. 1896 */ 1897 c_tbl->ct_ecnt++; 1898 1899 /* XXX - temporarily make sure the PTE is cleared. */ 1900 c_pte->attr.raw = 0; 1901 1902 /* It will also need to be inserted into the PV list. */ 1903 insert = TRUE; 1904 } 1905 1906 /* 1907 * If page is changing from unwired to wired status, set an unused bit 1908 * within the PTE to indicate that it is wired. Also increment the 1909 * wired entry count in the C table manager. 1910 */ 1911 if (wired) { 1912 c_pte->attr.raw |= MMU_SHORT_PTE_WIRED; 1913 c_tbl->ct_wcnt++; 1914 } 1915 1916 /* 1917 * Map the page, being careful to preserve modify/reference/wired 1918 * bits. At this point it is assumed that the PTE either has no bits 1919 * set, or if there are set bits, they are only modified, reference or 1920 * wired bits. If not, the following statement will cause erratic 1921 * behavior. 1922 */ 1923 #ifdef PMAP_DEBUG 1924 if (c_pte->attr.raw & ~(MMU_SHORT_PTE_M | 1925 MMU_SHORT_PTE_USED | MMU_SHORT_PTE_WIRED)) { 1926 printf("pmap_enter: junk left in PTE at %p\n", c_pte); 1927 Debugger(); 1928 } 1929 #endif 1930 c_pte->attr.raw |= ((u_long) pa | MMU_DT_PAGE); 1931 1932 /* 1933 * If the mapping should be read-only, set the write protect 1934 * bit in the PTE. 1935 */ 1936 if (!(prot & VM_PROT_WRITE)) 1937 c_pte->attr.raw |= MMU_SHORT_PTE_WP; 1938 1939 /* 1940 * If the mapping should be cache inhibited (indicated by the flag 1941 * bits found on the lower order of the physical address.) 1942 * mark the PTE as a cache inhibited page. 1943 */ 1944 if (mapflags & PMAP_NC) 1945 c_pte->attr.raw |= MMU_SHORT_PTE_CI; 1946 1947 /* 1948 * If the physical address being mapped is managed by the PV 1949 * system then link the pte into the list of pages mapped to that 1950 * address. 1951 */ 1952 if (insert && managed) { 1953 pv = pa2pv(pa); 1954 nidx = pteidx(c_pte); 1955 1956 pvebase[nidx].pve_next = pv->pv_idx; 1957 pv->pv_idx = nidx; 1958 } 1959 1960 /* Move any allocated tables back into the active pool. */ 1961 1962 switch (llevel) { 1963 case NEWA: 1964 TAILQ_INSERT_TAIL(&a_pool, a_tbl, at_link); 1965 /* FALLTHROUGH */ 1966 case NEWB: 1967 TAILQ_INSERT_TAIL(&b_pool, b_tbl, bt_link); 1968 /* FALLTHROUGH */ 1969 case NEWC: 1970 TAILQ_INSERT_TAIL(&c_pool, c_tbl, ct_link); 1971 /* FALLTHROUGH */ 1972 default: 1973 break; 1974 } 1975 1976 return 0; 1977 } 1978 1979 /* pmap_enter_kernel INTERNAL 1980 ** 1981 * Map the given virtual address to the given physical address within the 1982 * kernel address space. This function exists because the kernel map does 1983 * not do dynamic table allocation. It consists of a contiguous array of ptes 1984 * and can be edited directly without the need to walk through any tables. 1985 * 1986 * XXX: "Danger, Will Robinson!" 1987 * Note that the kernel should never take a fault on any page 1988 * between [ KERNBASE .. virtual_avail ] and this is checked in 1989 * trap.c for kernel-mode MMU faults. This means that mappings 1990 * created in that range must be implicily wired. -gwr 1991 */ 1992 void 1993 pmap_enter_kernel(va, pa, prot) 1994 vaddr_t va; 1995 paddr_t pa; 1996 vm_prot_t prot; 1997 { 1998 boolean_t was_valid, insert; 1999 u_short pte_idx; 2000 int flags; 2001 mmu_short_pte_t *pte; 2002 pv_t *pv; 2003 paddr_t old_pa; 2004 2005 flags = (pa & ~MMU_PAGE_MASK); 2006 pa &= MMU_PAGE_MASK; 2007 2008 if (is_managed(pa)) 2009 insert = TRUE; 2010 else 2011 insert = FALSE; 2012 2013 /* 2014 * Calculate the index of the PTE being modified. 2015 */ 2016 pte_idx = (u_long) m68k_btop(va - KERNBASE); 2017 2018 /* This array is traditionally named "Sysmap" */ 2019 pte = &kernCbase[pte_idx]; 2020 2021 if (MMU_VALID_DT(*pte)) { 2022 was_valid = TRUE; 2023 /* 2024 * If the PTE already maps a different 2025 * physical address, umap and pv_unlink. 2026 */ 2027 old_pa = MMU_PTE_PA(*pte); 2028 if (pa != old_pa) 2029 pmap_remove_pte(pte); 2030 else { 2031 /* 2032 * Old PA and new PA are the same. No need to 2033 * relink the mapping within the PV list. 2034 */ 2035 insert = FALSE; 2036 2037 /* 2038 * Save any mod/ref bits on the PTE. 2039 */ 2040 pte->attr.raw &= (MMU_SHORT_PTE_USED|MMU_SHORT_PTE_M); 2041 } 2042 } else { 2043 pte->attr.raw = MMU_DT_INVALID; 2044 was_valid = FALSE; 2045 } 2046 2047 /* 2048 * Map the page. Being careful to preserve modified/referenced bits 2049 * on the PTE. 2050 */ 2051 pte->attr.raw |= (pa | MMU_DT_PAGE); 2052 2053 if (!(prot & VM_PROT_WRITE)) /* If access should be read-only */ 2054 pte->attr.raw |= MMU_SHORT_PTE_WP; 2055 if (flags & PMAP_NC) 2056 pte->attr.raw |= MMU_SHORT_PTE_CI; 2057 if (was_valid) 2058 TBIS(va); 2059 2060 /* 2061 * Insert the PTE into the PV system, if need be. 2062 */ 2063 if (insert) { 2064 pv = pa2pv(pa); 2065 pvebase[pte_idx].pve_next = pv->pv_idx; 2066 pv->pv_idx = pte_idx; 2067 } 2068 } 2069 2070 void 2071 pmap_kenter_pa(va, pa, prot) 2072 vaddr_t va; 2073 paddr_t pa; 2074 vm_prot_t prot; 2075 { 2076 mmu_short_pte_t *pte; 2077 2078 /* This array is traditionally named "Sysmap" */ 2079 pte = &kernCbase[(u_long)m68k_btop(va - KERNBASE)]; 2080 2081 KASSERT(!MMU_VALID_DT(*pte)); 2082 pte->attr.raw = MMU_DT_INVALID | MMU_DT_PAGE | (pa & MMU_PAGE_MASK); 2083 if (!(prot & VM_PROT_WRITE)) 2084 pte->attr.raw |= MMU_SHORT_PTE_WP; 2085 } 2086 2087 void 2088 pmap_kremove(va, len) 2089 vaddr_t va; 2090 vsize_t len; 2091 { 2092 int idx, eidx; 2093 2094 #ifdef PMAP_DEBUG 2095 if ((sva & PGOFSET) || (eva & PGOFSET)) 2096 panic("pmap_kremove: alignment"); 2097 #endif 2098 2099 idx = m68k_btop(va - KERNBASE); 2100 eidx = m68k_btop(va + len - KERNBASE); 2101 2102 while (idx < eidx) { 2103 kernCbase[idx++].attr.raw = MMU_DT_INVALID; 2104 TBIS(va); 2105 va += NBPG; 2106 } 2107 } 2108 2109 /* pmap_map INTERNAL 2110 ** 2111 * Map a contiguous range of physical memory into a contiguous range of 2112 * the kernel virtual address space. 2113 * 2114 * Used for device mappings and early mapping of the kernel text/data/bss. 2115 * Returns the first virtual address beyond the end of the range. 2116 */ 2117 vaddr_t 2118 pmap_map(va, pa, endpa, prot) 2119 vaddr_t va; 2120 paddr_t pa; 2121 paddr_t endpa; 2122 int prot; 2123 { 2124 int sz; 2125 2126 sz = endpa - pa; 2127 do { 2128 pmap_enter_kernel(va, pa, prot); 2129 va += NBPG; 2130 pa += NBPG; 2131 sz -= NBPG; 2132 } while (sz > 0); 2133 pmap_update(pmap_kernel()); 2134 return(va); 2135 } 2136 2137 /* pmap_protect INTERFACE 2138 ** 2139 * Apply the given protection to the given virtual address range within 2140 * the given map. 2141 * 2142 * It is ok for the protection applied to be stronger than what is 2143 * specified. We use this to our advantage when the given map has no 2144 * mapping for the virtual address. By skipping a page when this 2145 * is discovered, we are effectively applying a protection of VM_PROT_NONE, 2146 * and therefore do not need to map the page just to apply a protection 2147 * code. Only pmap_enter() needs to create new mappings if they do not exist. 2148 * 2149 * XXX - This function could be speeded up by using pmap_stroll() for inital 2150 * setup, and then manual scrolling in the for() loop. 2151 */ 2152 void 2153 pmap_protect(pmap, startva, endva, prot) 2154 pmap_t pmap; 2155 vaddr_t startva, endva; 2156 vm_prot_t prot; 2157 { 2158 boolean_t iscurpmap; 2159 int a_idx, b_idx, c_idx; 2160 a_tmgr_t *a_tbl; 2161 b_tmgr_t *b_tbl; 2162 c_tmgr_t *c_tbl; 2163 mmu_short_pte_t *pte; 2164 2165 if (pmap == pmap_kernel()) { 2166 pmap_protect_kernel(startva, endva, prot); 2167 return; 2168 } 2169 2170 /* 2171 * In this particular pmap implementation, there are only three 2172 * types of memory protection: 'all' (read/write/execute), 2173 * 'read-only' (read/execute) and 'none' (no mapping.) 2174 * It is not possible for us to treat 'executable' as a separate 2175 * protection type. Therefore, protection requests that seek to 2176 * remove execute permission while retaining read or write, and those 2177 * that make little sense (write-only for example) are ignored. 2178 */ 2179 switch (prot) { 2180 case VM_PROT_NONE: 2181 /* 2182 * A request to apply the protection code of 2183 * 'VM_PROT_NONE' is a synonym for pmap_remove(). 2184 */ 2185 pmap_remove(pmap, startva, endva); 2186 return; 2187 case VM_PROT_EXECUTE: 2188 case VM_PROT_READ: 2189 case VM_PROT_READ|VM_PROT_EXECUTE: 2190 /* continue */ 2191 break; 2192 case VM_PROT_WRITE: 2193 case VM_PROT_WRITE|VM_PROT_READ: 2194 case VM_PROT_WRITE|VM_PROT_EXECUTE: 2195 case VM_PROT_ALL: 2196 /* None of these should happen in a sane system. */ 2197 return; 2198 } 2199 2200 /* 2201 * If the pmap has no A table, it has no mappings and therefore 2202 * there is nothing to protect. 2203 */ 2204 if ((a_tbl = pmap->pm_a_tmgr) == NULL) 2205 return; 2206 2207 a_idx = MMU_TIA(startva); 2208 b_idx = MMU_TIB(startva); 2209 c_idx = MMU_TIC(startva); 2210 b_tbl = (b_tmgr_t *) c_tbl = NULL; 2211 2212 iscurpmap = (pmap == current_pmap()); 2213 while (startva < endva) { 2214 if (b_tbl || MMU_VALID_DT(a_tbl->at_dtbl[a_idx])) { 2215 if (b_tbl == NULL) { 2216 b_tbl = (b_tmgr_t *) a_tbl->at_dtbl[a_idx].addr.raw; 2217 b_tbl = mmu_ptov((vaddr_t)b_tbl); 2218 b_tbl = mmuB2tmgr((mmu_short_dte_t *)b_tbl); 2219 } 2220 if (c_tbl || MMU_VALID_DT(b_tbl->bt_dtbl[b_idx])) { 2221 if (c_tbl == NULL) { 2222 c_tbl = (c_tmgr_t *) MMU_DTE_PA(b_tbl->bt_dtbl[b_idx]); 2223 c_tbl = mmu_ptov((vaddr_t)c_tbl); 2224 c_tbl = mmuC2tmgr((mmu_short_pte_t *)c_tbl); 2225 } 2226 if (MMU_VALID_DT(c_tbl->ct_dtbl[c_idx])) { 2227 pte = &c_tbl->ct_dtbl[c_idx]; 2228 /* make the mapping read-only */ 2229 pte->attr.raw |= MMU_SHORT_PTE_WP; 2230 /* 2231 * If we just modified the current address space, 2232 * flush any translations for the modified page from 2233 * the translation cache and any data from it in the 2234 * data cache. 2235 */ 2236 if (iscurpmap) 2237 TBIS(startva); 2238 } 2239 startva += NBPG; 2240 2241 if (++c_idx >= MMU_C_TBL_SIZE) { /* exceeded C table? */ 2242 c_tbl = NULL; 2243 c_idx = 0; 2244 if (++b_idx >= MMU_B_TBL_SIZE) { /* exceeded B table? */ 2245 b_tbl = NULL; 2246 b_idx = 0; 2247 } 2248 } 2249 } else { /* C table wasn't valid */ 2250 c_tbl = NULL; 2251 c_idx = 0; 2252 startva += MMU_TIB_RANGE; 2253 if (++b_idx >= MMU_B_TBL_SIZE) { /* exceeded B table? */ 2254 b_tbl = NULL; 2255 b_idx = 0; 2256 } 2257 } /* C table */ 2258 } else { /* B table wasn't valid */ 2259 b_tbl = NULL; 2260 b_idx = 0; 2261 startva += MMU_TIA_RANGE; 2262 a_idx++; 2263 } /* B table */ 2264 } 2265 } 2266 2267 /* pmap_protect_kernel INTERNAL 2268 ** 2269 * Apply the given protection code to a kernel address range. 2270 */ 2271 void 2272 pmap_protect_kernel(startva, endva, prot) 2273 vaddr_t startva, endva; 2274 vm_prot_t prot; 2275 { 2276 vaddr_t va; 2277 mmu_short_pte_t *pte; 2278 2279 pte = &kernCbase[(unsigned long) m68k_btop(startva - KERNBASE)]; 2280 for (va = startva; va < endva; va += NBPG, pte++) { 2281 if (MMU_VALID_DT(*pte)) { 2282 switch (prot) { 2283 case VM_PROT_ALL: 2284 break; 2285 case VM_PROT_EXECUTE: 2286 case VM_PROT_READ: 2287 case VM_PROT_READ|VM_PROT_EXECUTE: 2288 pte->attr.raw |= MMU_SHORT_PTE_WP; 2289 break; 2290 case VM_PROT_NONE: 2291 /* this is an alias for 'pmap_remove_kernel' */ 2292 pmap_remove_pte(pte); 2293 break; 2294 default: 2295 break; 2296 } 2297 /* 2298 * since this is the kernel, immediately flush any cached 2299 * descriptors for this address. 2300 */ 2301 TBIS(va); 2302 } 2303 } 2304 } 2305 2306 /* pmap_unwire INTERFACE 2307 ** 2308 * Clear the wired attribute of the specified page. 2309 * 2310 * This function is called from vm_fault.c to unwire 2311 * a mapping. 2312 */ 2313 void 2314 pmap_unwire(pmap, va) 2315 pmap_t pmap; 2316 vaddr_t va; 2317 { 2318 int a_idx, b_idx, c_idx; 2319 a_tmgr_t *a_tbl; 2320 b_tmgr_t *b_tbl; 2321 c_tmgr_t *c_tbl; 2322 mmu_short_pte_t *pte; 2323 2324 /* Kernel mappings always remain wired. */ 2325 if (pmap == pmap_kernel()) 2326 return; 2327 2328 /* 2329 * Walk through the tables. If the walk terminates without 2330 * a valid PTE then the address wasn't wired in the first place. 2331 * Return immediately. 2332 */ 2333 if (pmap_stroll(pmap, va, &a_tbl, &b_tbl, &c_tbl, &pte, &a_idx, 2334 &b_idx, &c_idx) == FALSE) 2335 return; 2336 2337 2338 /* Is the PTE wired? If not, return. */ 2339 if (!(pte->attr.raw & MMU_SHORT_PTE_WIRED)) 2340 return; 2341 2342 /* Remove the wiring bit. */ 2343 pte->attr.raw &= ~(MMU_SHORT_PTE_WIRED); 2344 2345 /* 2346 * Decrement the wired entry count in the C table. 2347 * If it reaches zero the following things happen: 2348 * 1. The table no longer has any wired entries and is considered 2349 * unwired. 2350 * 2. It is placed on the available queue. 2351 * 3. The parent table's wired entry count is decremented. 2352 * 4. If it reaches zero, this process repeats at step 1 and 2353 * stops at after reaching the A table. 2354 */ 2355 if (--c_tbl->ct_wcnt == 0) { 2356 TAILQ_INSERT_TAIL(&c_pool, c_tbl, ct_link); 2357 if (--b_tbl->bt_wcnt == 0) { 2358 TAILQ_INSERT_TAIL(&b_pool, b_tbl, bt_link); 2359 if (--a_tbl->at_wcnt == 0) { 2360 TAILQ_INSERT_TAIL(&a_pool, a_tbl, at_link); 2361 } 2362 } 2363 } 2364 } 2365 2366 /* pmap_copy INTERFACE 2367 ** 2368 * Copy the mappings of a range of addresses in one pmap, into 2369 * the destination address of another. 2370 * 2371 * This routine is advisory. Should we one day decide that MMU tables 2372 * may be shared by more than one pmap, this function should be used to 2373 * link them together. Until that day however, we do nothing. 2374 */ 2375 void 2376 pmap_copy(pmap_a, pmap_b, dst, len, src) 2377 pmap_t pmap_a, pmap_b; 2378 vaddr_t dst; 2379 vsize_t len; 2380 vaddr_t src; 2381 { 2382 /* not implemented. */ 2383 } 2384 2385 /* pmap_copy_page INTERFACE 2386 ** 2387 * Copy the contents of one physical page into another. 2388 * 2389 * This function makes use of two virtual pages allocated in pmap_bootstrap() 2390 * to map the two specified physical pages into the kernel address space. 2391 * 2392 * Note: We could use the transparent translation registers to make the 2393 * mappings. If we do so, be sure to disable interrupts before using them. 2394 */ 2395 void 2396 pmap_copy_page(srcpa, dstpa) 2397 paddr_t srcpa, dstpa; 2398 { 2399 vaddr_t srcva, dstva; 2400 int s; 2401 2402 srcva = tmp_vpages[0]; 2403 dstva = tmp_vpages[1]; 2404 2405 s = splvm(); 2406 #ifdef DIAGNOSTIC 2407 if (tmp_vpages_inuse++) 2408 panic("pmap_copy_page: temporary vpages are in use."); 2409 #endif 2410 2411 /* Map pages as non-cacheable to avoid cache polution? */ 2412 pmap_kenter_pa(srcva, srcpa, VM_PROT_READ); 2413 pmap_kenter_pa(dstva, dstpa, VM_PROT_READ|VM_PROT_WRITE); 2414 2415 /* Hand-optimized version of bcopy(src, dst, NBPG) */ 2416 copypage((char *) srcva, (char *) dstva); 2417 2418 pmap_kremove(srcva, NBPG); 2419 pmap_kremove(dstva, NBPG); 2420 2421 #ifdef DIAGNOSTIC 2422 --tmp_vpages_inuse; 2423 #endif 2424 splx(s); 2425 } 2426 2427 /* pmap_zero_page INTERFACE 2428 ** 2429 * Zero the contents of the specified physical page. 2430 * 2431 * Uses one of the virtual pages allocated in pmap_boostrap() 2432 * to map the specified page into the kernel address space. 2433 */ 2434 void 2435 pmap_zero_page(dstpa) 2436 paddr_t dstpa; 2437 { 2438 vaddr_t dstva; 2439 int s; 2440 2441 dstva = tmp_vpages[1]; 2442 s = splvm(); 2443 #ifdef DIAGNOSTIC 2444 if (tmp_vpages_inuse++) 2445 panic("pmap_zero_page: temporary vpages are in use."); 2446 #endif 2447 2448 /* The comments in pmap_copy_page() above apply here also. */ 2449 pmap_kenter_pa(dstva, dstpa, VM_PROT_READ|VM_PROT_WRITE); 2450 2451 /* Hand-optimized version of bzero(ptr, NBPG) */ 2452 zeropage((char *) dstva); 2453 2454 pmap_kremove(dstva, NBPG); 2455 #ifdef DIAGNOSTIC 2456 --tmp_vpages_inuse; 2457 #endif 2458 splx(s); 2459 } 2460 2461 /* pmap_collect INTERFACE 2462 ** 2463 * Called from the VM system when we are about to swap out 2464 * the process using this pmap. This should give up any 2465 * resources held here, including all its MMU tables. 2466 */ 2467 void 2468 pmap_collect(pmap) 2469 pmap_t pmap; 2470 { 2471 /* XXX - todo... */ 2472 } 2473 2474 /* pmap_create INTERFACE 2475 ** 2476 * Create and return a pmap structure. 2477 */ 2478 pmap_t 2479 pmap_create() 2480 { 2481 pmap_t pmap; 2482 2483 pmap = pool_get(&pmap_pmap_pool, PR_WAITOK); 2484 pmap_pinit(pmap); 2485 return pmap; 2486 } 2487 2488 /* pmap_pinit INTERNAL 2489 ** 2490 * Initialize a pmap structure. 2491 */ 2492 void 2493 pmap_pinit(pmap) 2494 pmap_t pmap; 2495 { 2496 memset(pmap, 0, sizeof(struct pmap)); 2497 pmap->pm_a_tmgr = NULL; 2498 pmap->pm_a_phys = kernAphys; 2499 pmap->pm_refcount = 1; 2500 simple_lock_init(&pmap->pm_lock); 2501 } 2502 2503 /* pmap_release INTERFACE 2504 ** 2505 * Release any resources held by the given pmap. 2506 * 2507 * This is the reverse analog to pmap_pinit. It does not 2508 * necessarily mean for the pmap structure to be deallocated, 2509 * as in pmap_destroy. 2510 */ 2511 void 2512 pmap_release(pmap) 2513 pmap_t pmap; 2514 { 2515 /* 2516 * As long as the pmap contains no mappings, 2517 * which always should be the case whenever 2518 * this function is called, there really should 2519 * be nothing to do. 2520 */ 2521 #ifdef PMAP_DEBUG 2522 if (pmap == pmap_kernel()) 2523 panic("pmap_release: kernel pmap"); 2524 #endif 2525 /* 2526 * XXX - If this pmap has an A table, give it back. 2527 * The pmap SHOULD be empty by now, and pmap_remove 2528 * should have already given back the A table... 2529 * However, I see: pmap->pm_a_tmgr->at_ecnt == 1 2530 * at this point, which means some mapping was not 2531 * removed when it should have been. -gwr 2532 */ 2533 if (pmap->pm_a_tmgr != NULL) { 2534 /* First make sure we are not using it! */ 2535 if (kernel_crp.rp_addr == pmap->pm_a_phys) { 2536 kernel_crp.rp_addr = kernAphys; 2537 loadcrp(&kernel_crp); 2538 } 2539 #ifdef PMAP_DEBUG /* XXX - todo! */ 2540 /* XXX - Now complain... */ 2541 printf("pmap_release: still have table\n"); 2542 Debugger(); 2543 #endif 2544 free_a_table(pmap->pm_a_tmgr, TRUE); 2545 pmap->pm_a_tmgr = NULL; 2546 pmap->pm_a_phys = kernAphys; 2547 } 2548 } 2549 2550 /* pmap_reference INTERFACE 2551 ** 2552 * Increment the reference count of a pmap. 2553 */ 2554 void 2555 pmap_reference(pmap) 2556 pmap_t pmap; 2557 { 2558 pmap_lock(pmap); 2559 pmap_add_ref(pmap); 2560 pmap_unlock(pmap); 2561 } 2562 2563 /* pmap_dereference INTERNAL 2564 ** 2565 * Decrease the reference count on the given pmap 2566 * by one and return the current count. 2567 */ 2568 int 2569 pmap_dereference(pmap) 2570 pmap_t pmap; 2571 { 2572 int rtn; 2573 2574 pmap_lock(pmap); 2575 rtn = pmap_del_ref(pmap); 2576 pmap_unlock(pmap); 2577 2578 return rtn; 2579 } 2580 2581 /* pmap_destroy INTERFACE 2582 ** 2583 * Decrement a pmap's reference count and delete 2584 * the pmap if it becomes zero. Will be called 2585 * only after all mappings have been removed. 2586 */ 2587 void 2588 pmap_destroy(pmap) 2589 pmap_t pmap; 2590 { 2591 if (pmap_dereference(pmap) == 0) { 2592 pmap_release(pmap); 2593 pool_put(&pmap_pmap_pool, pmap); 2594 } 2595 } 2596 2597 /* pmap_is_referenced INTERFACE 2598 ** 2599 * Determine if the given physical page has been 2600 * referenced (read from [or written to.]) 2601 */ 2602 boolean_t 2603 pmap_is_referenced(pg) 2604 struct vm_page *pg; 2605 { 2606 paddr_t pa = VM_PAGE_TO_PHYS(pg); 2607 pv_t *pv; 2608 int idx; 2609 2610 /* 2611 * Check the flags on the pv head. If they are set, 2612 * return immediately. Otherwise a search must be done. 2613 */ 2614 2615 pv = pa2pv(pa); 2616 if (pv->pv_flags & PV_FLAGS_USED) 2617 return TRUE; 2618 2619 /* 2620 * Search through all pv elements pointing 2621 * to this page and query their reference bits 2622 */ 2623 2624 for (idx = pv->pv_idx; idx != PVE_EOL; idx = pvebase[idx].pve_next) { 2625 if (MMU_PTE_USED(kernCbase[idx])) { 2626 return TRUE; 2627 } 2628 } 2629 return FALSE; 2630 } 2631 2632 /* pmap_is_modified INTERFACE 2633 ** 2634 * Determine if the given physical page has been 2635 * modified (written to.) 2636 */ 2637 boolean_t 2638 pmap_is_modified(pg) 2639 struct vm_page *pg; 2640 { 2641 paddr_t pa = VM_PAGE_TO_PHYS(pg); 2642 pv_t *pv; 2643 int idx; 2644 2645 /* see comments in pmap_is_referenced() */ 2646 pv = pa2pv(pa); 2647 if (pv->pv_flags & PV_FLAGS_MDFY) 2648 return TRUE; 2649 2650 for (idx = pv->pv_idx; 2651 idx != PVE_EOL; 2652 idx = pvebase[idx].pve_next) { 2653 2654 if (MMU_PTE_MODIFIED(kernCbase[idx])) { 2655 return TRUE; 2656 } 2657 } 2658 2659 return FALSE; 2660 } 2661 2662 /* pmap_page_protect INTERFACE 2663 ** 2664 * Applies the given protection to all mappings to the given 2665 * physical page. 2666 */ 2667 void 2668 pmap_page_protect(pg, prot) 2669 struct vm_page *pg; 2670 vm_prot_t prot; 2671 { 2672 paddr_t pa = VM_PAGE_TO_PHYS(pg); 2673 pv_t *pv; 2674 int idx; 2675 vaddr_t va; 2676 struct mmu_short_pte_struct *pte; 2677 c_tmgr_t *c_tbl; 2678 pmap_t pmap, curpmap; 2679 2680 curpmap = current_pmap(); 2681 pv = pa2pv(pa); 2682 2683 for (idx = pv->pv_idx; idx != PVE_EOL; idx = pvebase[idx].pve_next) { 2684 pte = &kernCbase[idx]; 2685 switch (prot) { 2686 case VM_PROT_ALL: 2687 /* do nothing */ 2688 break; 2689 case VM_PROT_EXECUTE: 2690 case VM_PROT_READ: 2691 case VM_PROT_READ|VM_PROT_EXECUTE: 2692 /* 2693 * Determine the virtual address mapped by 2694 * the PTE and flush ATC entries if necessary. 2695 */ 2696 va = pmap_get_pteinfo(idx, &pmap, &c_tbl); 2697 pte->attr.raw |= MMU_SHORT_PTE_WP; 2698 if (pmap == curpmap || pmap == pmap_kernel()) 2699 TBIS(va); 2700 break; 2701 case VM_PROT_NONE: 2702 /* Save the mod/ref bits. */ 2703 pv->pv_flags |= pte->attr.raw; 2704 /* Invalidate the PTE. */ 2705 pte->attr.raw = MMU_DT_INVALID; 2706 2707 /* 2708 * Update table counts. And flush ATC entries 2709 * if necessary. 2710 */ 2711 va = pmap_get_pteinfo(idx, &pmap, &c_tbl); 2712 2713 /* 2714 * If the PTE belongs to the kernel map, 2715 * be sure to flush the page it maps. 2716 */ 2717 if (pmap == pmap_kernel()) { 2718 TBIS(va); 2719 } else { 2720 /* 2721 * The PTE belongs to a user map. 2722 * update the entry count in the C 2723 * table to which it belongs and flush 2724 * the ATC if the mapping belongs to 2725 * the current pmap. 2726 */ 2727 c_tbl->ct_ecnt--; 2728 if (pmap == curpmap) 2729 TBIS(va); 2730 } 2731 break; 2732 default: 2733 break; 2734 } 2735 } 2736 2737 /* 2738 * If the protection code indicates that all mappings to the page 2739 * be removed, truncate the PV list to zero entries. 2740 */ 2741 if (prot == VM_PROT_NONE) 2742 pv->pv_idx = PVE_EOL; 2743 } 2744 2745 /* pmap_get_pteinfo INTERNAL 2746 ** 2747 * Called internally to find the pmap and virtual address within that 2748 * map to which the pte at the given index maps. Also includes the PTE's C 2749 * table manager. 2750 * 2751 * Returns the pmap in the argument provided, and the virtual address 2752 * by return value. 2753 */ 2754 vaddr_t 2755 pmap_get_pteinfo(idx, pmap, tbl) 2756 u_int idx; 2757 pmap_t *pmap; 2758 c_tmgr_t **tbl; 2759 { 2760 vaddr_t va = 0; 2761 2762 /* 2763 * Determine if the PTE is a kernel PTE or a user PTE. 2764 */ 2765 if (idx >= NUM_KERN_PTES) { 2766 /* 2767 * The PTE belongs to a user mapping. 2768 */ 2769 /* XXX: Would like an inline for this to validate idx... */ 2770 *tbl = &Ctmgrbase[(idx - NUM_KERN_PTES) / MMU_C_TBL_SIZE]; 2771 2772 *pmap = (*tbl)->ct_pmap; 2773 /* 2774 * To find the va to which the PTE maps, we first take 2775 * the table's base virtual address mapping which is stored 2776 * in ct_va. We then increment this address by a page for 2777 * every slot skipped until we reach the PTE. 2778 */ 2779 va = (*tbl)->ct_va; 2780 va += m68k_ptob(idx % MMU_C_TBL_SIZE); 2781 } else { 2782 /* 2783 * The PTE belongs to the kernel map. 2784 */ 2785 *pmap = pmap_kernel(); 2786 2787 va = m68k_ptob(idx); 2788 va += KERNBASE; 2789 } 2790 2791 return va; 2792 } 2793 2794 /* pmap_clear_modify INTERFACE 2795 ** 2796 * Clear the modification bit on the page at the specified 2797 * physical address. 2798 * 2799 */ 2800 boolean_t 2801 pmap_clear_modify(pg) 2802 struct vm_page *pg; 2803 { 2804 paddr_t pa = VM_PAGE_TO_PHYS(pg); 2805 boolean_t rv; 2806 2807 rv = pmap_is_modified(pg); 2808 pmap_clear_pv(pa, PV_FLAGS_MDFY); 2809 return rv; 2810 } 2811 2812 /* pmap_clear_reference INTERFACE 2813 ** 2814 * Clear the referenced bit on the page at the specified 2815 * physical address. 2816 */ 2817 boolean_t 2818 pmap_clear_reference(pg) 2819 struct vm_page *pg; 2820 { 2821 paddr_t pa = VM_PAGE_TO_PHYS(pg); 2822 boolean_t rv; 2823 2824 rv = pmap_is_referenced(pg); 2825 pmap_clear_pv(pa, PV_FLAGS_USED); 2826 return rv; 2827 } 2828 2829 /* pmap_clear_pv INTERNAL 2830 ** 2831 * Clears the specified flag from the specified physical address. 2832 * (Used by pmap_clear_modify() and pmap_clear_reference().) 2833 * 2834 * Flag is one of: 2835 * PV_FLAGS_MDFY - Page modified bit. 2836 * PV_FLAGS_USED - Page used (referenced) bit. 2837 * 2838 * This routine must not only clear the flag on the pv list 2839 * head. It must also clear the bit on every pte in the pv 2840 * list associated with the address. 2841 */ 2842 void 2843 pmap_clear_pv(pa, flag) 2844 paddr_t pa; 2845 int flag; 2846 { 2847 pv_t *pv; 2848 int idx; 2849 vaddr_t va; 2850 pmap_t pmap; 2851 mmu_short_pte_t *pte; 2852 c_tmgr_t *c_tbl; 2853 2854 pv = pa2pv(pa); 2855 pv->pv_flags &= ~(flag); 2856 for (idx = pv->pv_idx; idx != PVE_EOL; idx = pvebase[idx].pve_next) { 2857 pte = &kernCbase[idx]; 2858 pte->attr.raw &= ~(flag); 2859 2860 /* 2861 * The MC68030 MMU will not set the modified or 2862 * referenced bits on any MMU tables for which it has 2863 * a cached descriptor with its modify bit set. To insure 2864 * that it will modify these bits on the PTE during the next 2865 * time it is written to or read from, we must flush it from 2866 * the ATC. 2867 * 2868 * Ordinarily it is only necessary to flush the descriptor 2869 * if it is used in the current address space. But since I 2870 * am not sure that there will always be a notion of 2871 * 'the current address space' when this function is called, 2872 * I will skip the test and always flush the address. It 2873 * does no harm. 2874 */ 2875 2876 va = pmap_get_pteinfo(idx, &pmap, &c_tbl); 2877 TBIS(va); 2878 } 2879 } 2880 2881 /* pmap_extract INTERFACE 2882 ** 2883 * Return the physical address mapped by the virtual address 2884 * in the specified pmap. 2885 * 2886 * Note: this function should also apply an exclusive lock 2887 * on the pmap system during its duration. 2888 */ 2889 boolean_t 2890 pmap_extract(pmap, va, pap) 2891 pmap_t pmap; 2892 vaddr_t va; 2893 paddr_t *pap; 2894 { 2895 int a_idx, b_idx, pte_idx; 2896 a_tmgr_t *a_tbl; 2897 b_tmgr_t *b_tbl; 2898 c_tmgr_t *c_tbl; 2899 mmu_short_pte_t *c_pte; 2900 2901 if (pmap == pmap_kernel()) 2902 return pmap_extract_kernel(va, pap); 2903 2904 if (pmap_stroll(pmap, va, &a_tbl, &b_tbl, &c_tbl, 2905 &c_pte, &a_idx, &b_idx, &pte_idx) == FALSE) 2906 return FALSE; 2907 2908 if (!MMU_VALID_DT(*c_pte)) 2909 return FALSE; 2910 2911 if (pap != NULL) 2912 *pap = MMU_PTE_PA(*c_pte); 2913 return (TRUE); 2914 } 2915 2916 /* pmap_extract_kernel INTERNAL 2917 ** 2918 * Extract a translation from the kernel address space. 2919 */ 2920 boolean_t 2921 pmap_extract_kernel(va, pap) 2922 vaddr_t va; 2923 paddr_t *pap; 2924 { 2925 mmu_short_pte_t *pte; 2926 2927 pte = &kernCbase[(u_int) m68k_btop(va - KERNBASE)]; 2928 if (!MMU_VALID_DT(*pte)) 2929 return (FALSE); 2930 if (pap != NULL) 2931 *pap = MMU_PTE_PA(*pte); 2932 return (TRUE); 2933 } 2934 2935 /* pmap_remove_kernel INTERNAL 2936 ** 2937 * Remove the mapping of a range of virtual addresses from the kernel map. 2938 * The arguments are already page-aligned. 2939 */ 2940 void 2941 pmap_remove_kernel(sva, eva) 2942 vaddr_t sva; 2943 vaddr_t eva; 2944 { 2945 int idx, eidx; 2946 2947 #ifdef PMAP_DEBUG 2948 if ((sva & PGOFSET) || (eva & PGOFSET)) 2949 panic("pmap_remove_kernel: alignment"); 2950 #endif 2951 2952 idx = m68k_btop(sva - KERNBASE); 2953 eidx = m68k_btop(eva - KERNBASE); 2954 2955 while (idx < eidx) { 2956 pmap_remove_pte(&kernCbase[idx++]); 2957 TBIS(sva); 2958 sva += NBPG; 2959 } 2960 } 2961 2962 /* pmap_remove INTERFACE 2963 ** 2964 * Remove the mapping of a range of virtual addresses from the given pmap. 2965 * 2966 * If the range contains any wired entries, this function will probably create 2967 * disaster. 2968 */ 2969 void 2970 pmap_remove(pmap, start, end) 2971 pmap_t pmap; 2972 vaddr_t start; 2973 vaddr_t end; 2974 { 2975 2976 if (pmap == pmap_kernel()) { 2977 pmap_remove_kernel(start, end); 2978 return; 2979 } 2980 2981 /* 2982 * If the pmap doesn't have an A table of its own, it has no mappings 2983 * that can be removed. 2984 */ 2985 if (pmap->pm_a_tmgr == NULL) 2986 return; 2987 2988 /* 2989 * Remove the specified range from the pmap. If the function 2990 * returns true, the operation removed all the valid mappings 2991 * in the pmap and freed its A table. If this happened to the 2992 * currently loaded pmap, the MMU root pointer must be reloaded 2993 * with the default 'kernel' map. 2994 */ 2995 if (pmap_remove_a(pmap->pm_a_tmgr, start, end)) { 2996 if (kernel_crp.rp_addr == pmap->pm_a_phys) { 2997 kernel_crp.rp_addr = kernAphys; 2998 loadcrp(&kernel_crp); 2999 /* will do TLB flush below */ 3000 } 3001 pmap->pm_a_tmgr = NULL; 3002 pmap->pm_a_phys = kernAphys; 3003 } 3004 3005 /* 3006 * If we just modified the current address space, 3007 * make sure to flush the MMU cache. 3008 * 3009 * XXX - this could be an unecessarily large flush. 3010 * XXX - Could decide, based on the size of the VA range 3011 * to be removed, whether to flush "by pages" or "all". 3012 */ 3013 if (pmap == current_pmap()) 3014 TBIAU(); 3015 } 3016 3017 /* pmap_remove_a INTERNAL 3018 ** 3019 * This is function number one in a set of three that removes a range 3020 * of memory in the most efficient manner by removing the highest possible 3021 * tables from the memory space. This particular function attempts to remove 3022 * as many B tables as it can, delegating the remaining fragmented ranges to 3023 * pmap_remove_b(). 3024 * 3025 * If the removal operation results in an empty A table, the function returns 3026 * TRUE. 3027 * 3028 * It's ugly but will do for now. 3029 */ 3030 boolean_t 3031 pmap_remove_a(a_tbl, start, end) 3032 a_tmgr_t *a_tbl; 3033 vaddr_t start; 3034 vaddr_t end; 3035 { 3036 boolean_t empty; 3037 int idx; 3038 vaddr_t nstart, nend; 3039 b_tmgr_t *b_tbl; 3040 mmu_long_dte_t *a_dte; 3041 mmu_short_dte_t *b_dte; 3042 3043 /* 3044 * The following code works with what I call a 'granularity 3045 * reduction algorithim'. A range of addresses will always have 3046 * the following properties, which are classified according to 3047 * how the range relates to the size of the current granularity 3048 * - an A table entry: 3049 * 3050 * 1 2 3 4 3051 * -+---+---+---+---+---+---+---+- 3052 * -+---+---+---+---+---+---+---+- 3053 * 3054 * A range will always start on a granularity boundary, illustrated 3055 * by '+' signs in the table above, or it will start at some point 3056 * inbetween a granularity boundary, as illustrated by point 1. 3057 * The first step in removing a range of addresses is to remove the 3058 * range between 1 and 2, the nearest granularity boundary. This 3059 * job is handled by the section of code governed by the 3060 * 'if (start < nstart)' statement. 3061 * 3062 * A range will always encompass zero or more intergral granules, 3063 * illustrated by points 2 and 3. Integral granules are easy to 3064 * remove. The removal of these granules is the second step, and 3065 * is handled by the code block 'if (nstart < nend)'. 3066 * 3067 * Lastly, a range will always end on a granularity boundary, 3068 * ill. by point 3, or it will fall just beyond one, ill. by point 3069 * 4. The last step involves removing this range and is handled by 3070 * the code block 'if (nend < end)'. 3071 */ 3072 nstart = MMU_ROUND_UP_A(start); 3073 nend = MMU_ROUND_A(end); 3074 3075 if (start < nstart) { 3076 /* 3077 * This block is executed if the range starts between 3078 * a granularity boundary. 3079 * 3080 * First find the DTE which is responsible for mapping 3081 * the start of the range. 3082 */ 3083 idx = MMU_TIA(start); 3084 a_dte = &a_tbl->at_dtbl[idx]; 3085 3086 /* 3087 * If the DTE is valid then delegate the removal of the sub 3088 * range to pmap_remove_b(), which can remove addresses at 3089 * a finer granularity. 3090 */ 3091 if (MMU_VALID_DT(*a_dte)) { 3092 b_dte = mmu_ptov(a_dte->addr.raw); 3093 b_tbl = mmuB2tmgr(b_dte); 3094 3095 /* 3096 * The sub range to be removed starts at the start 3097 * of the full range we were asked to remove, and ends 3098 * at the greater of: 3099 * 1. The end of the full range, -or- 3100 * 2. The end of the full range, rounded down to the 3101 * nearest granularity boundary. 3102 */ 3103 if (end < nstart) 3104 empty = pmap_remove_b(b_tbl, start, end); 3105 else 3106 empty = pmap_remove_b(b_tbl, start, nstart); 3107 3108 /* 3109 * If the removal resulted in an empty B table, 3110 * invalidate the DTE that points to it and decrement 3111 * the valid entry count of the A table. 3112 */ 3113 if (empty) { 3114 a_dte->attr.raw = MMU_DT_INVALID; 3115 a_tbl->at_ecnt--; 3116 } 3117 } 3118 /* 3119 * If the DTE is invalid, the address range is already non- 3120 * existent and can simply be skipped. 3121 */ 3122 } 3123 if (nstart < nend) { 3124 /* 3125 * This block is executed if the range spans a whole number 3126 * multiple of granules (A table entries.) 3127 * 3128 * First find the DTE which is responsible for mapping 3129 * the start of the first granule involved. 3130 */ 3131 idx = MMU_TIA(nstart); 3132 a_dte = &a_tbl->at_dtbl[idx]; 3133 3134 /* 3135 * Remove entire sub-granules (B tables) one at a time, 3136 * until reaching the end of the range. 3137 */ 3138 for (; nstart < nend; a_dte++, nstart += MMU_TIA_RANGE) 3139 if (MMU_VALID_DT(*a_dte)) { 3140 /* 3141 * Find the B table manager for the 3142 * entry and free it. 3143 */ 3144 b_dte = mmu_ptov(a_dte->addr.raw); 3145 b_tbl = mmuB2tmgr(b_dte); 3146 free_b_table(b_tbl, TRUE); 3147 3148 /* 3149 * Invalidate the DTE that points to the 3150 * B table and decrement the valid entry 3151 * count of the A table. 3152 */ 3153 a_dte->attr.raw = MMU_DT_INVALID; 3154 a_tbl->at_ecnt--; 3155 } 3156 } 3157 if (nend < end) { 3158 /* 3159 * This block is executed if the range ends beyond a 3160 * granularity boundary. 3161 * 3162 * First find the DTE which is responsible for mapping 3163 * the start of the nearest (rounded down) granularity 3164 * boundary. 3165 */ 3166 idx = MMU_TIA(nend); 3167 a_dte = &a_tbl->at_dtbl[idx]; 3168 3169 /* 3170 * If the DTE is valid then delegate the removal of the sub 3171 * range to pmap_remove_b(), which can remove addresses at 3172 * a finer granularity. 3173 */ 3174 if (MMU_VALID_DT(*a_dte)) { 3175 /* 3176 * Find the B table manager for the entry 3177 * and hand it to pmap_remove_b() along with 3178 * the sub range. 3179 */ 3180 b_dte = mmu_ptov(a_dte->addr.raw); 3181 b_tbl = mmuB2tmgr(b_dte); 3182 3183 empty = pmap_remove_b(b_tbl, nend, end); 3184 3185 /* 3186 * If the removal resulted in an empty B table, 3187 * invalidate the DTE that points to it and decrement 3188 * the valid entry count of the A table. 3189 */ 3190 if (empty) { 3191 a_dte->attr.raw = MMU_DT_INVALID; 3192 a_tbl->at_ecnt--; 3193 } 3194 } 3195 } 3196 3197 /* 3198 * If there are no more entries in the A table, release it 3199 * back to the available pool and return TRUE. 3200 */ 3201 if (a_tbl->at_ecnt == 0) { 3202 a_tbl->at_parent = NULL; 3203 TAILQ_REMOVE(&a_pool, a_tbl, at_link); 3204 TAILQ_INSERT_HEAD(&a_pool, a_tbl, at_link); 3205 empty = TRUE; 3206 } else { 3207 empty = FALSE; 3208 } 3209 3210 return empty; 3211 } 3212 3213 /* pmap_remove_b INTERNAL 3214 ** 3215 * Remove a range of addresses from an address space, trying to remove entire 3216 * C tables if possible. 3217 * 3218 * If the operation results in an empty B table, the function returns TRUE. 3219 */ 3220 boolean_t 3221 pmap_remove_b(b_tbl, start, end) 3222 b_tmgr_t *b_tbl; 3223 vaddr_t start; 3224 vaddr_t end; 3225 { 3226 boolean_t empty; 3227 int idx; 3228 vaddr_t nstart, nend, rstart; 3229 c_tmgr_t *c_tbl; 3230 mmu_short_dte_t *b_dte; 3231 mmu_short_pte_t *c_dte; 3232 3233 3234 nstart = MMU_ROUND_UP_B(start); 3235 nend = MMU_ROUND_B(end); 3236 3237 if (start < nstart) { 3238 idx = MMU_TIB(start); 3239 b_dte = &b_tbl->bt_dtbl[idx]; 3240 if (MMU_VALID_DT(*b_dte)) { 3241 c_dte = mmu_ptov(MMU_DTE_PA(*b_dte)); 3242 c_tbl = mmuC2tmgr(c_dte); 3243 if (end < nstart) 3244 empty = pmap_remove_c(c_tbl, start, end); 3245 else 3246 empty = pmap_remove_c(c_tbl, start, nstart); 3247 if (empty) { 3248 b_dte->attr.raw = MMU_DT_INVALID; 3249 b_tbl->bt_ecnt--; 3250 } 3251 } 3252 } 3253 if (nstart < nend) { 3254 idx = MMU_TIB(nstart); 3255 b_dte = &b_tbl->bt_dtbl[idx]; 3256 rstart = nstart; 3257 while (rstart < nend) { 3258 if (MMU_VALID_DT(*b_dte)) { 3259 c_dte = mmu_ptov(MMU_DTE_PA(*b_dte)); 3260 c_tbl = mmuC2tmgr(c_dte); 3261 free_c_table(c_tbl, TRUE); 3262 b_dte->attr.raw = MMU_DT_INVALID; 3263 b_tbl->bt_ecnt--; 3264 } 3265 b_dte++; 3266 rstart += MMU_TIB_RANGE; 3267 } 3268 } 3269 if (nend < end) { 3270 idx = MMU_TIB(nend); 3271 b_dte = &b_tbl->bt_dtbl[idx]; 3272 if (MMU_VALID_DT(*b_dte)) { 3273 c_dte = mmu_ptov(MMU_DTE_PA(*b_dte)); 3274 c_tbl = mmuC2tmgr(c_dte); 3275 empty = pmap_remove_c(c_tbl, nend, end); 3276 if (empty) { 3277 b_dte->attr.raw = MMU_DT_INVALID; 3278 b_tbl->bt_ecnt--; 3279 } 3280 } 3281 } 3282 3283 if (b_tbl->bt_ecnt == 0) { 3284 b_tbl->bt_parent = NULL; 3285 TAILQ_REMOVE(&b_pool, b_tbl, bt_link); 3286 TAILQ_INSERT_HEAD(&b_pool, b_tbl, bt_link); 3287 empty = TRUE; 3288 } else { 3289 empty = FALSE; 3290 } 3291 3292 return empty; 3293 } 3294 3295 /* pmap_remove_c INTERNAL 3296 ** 3297 * Remove a range of addresses from the given C table. 3298 */ 3299 boolean_t 3300 pmap_remove_c(c_tbl, start, end) 3301 c_tmgr_t *c_tbl; 3302 vaddr_t start; 3303 vaddr_t end; 3304 { 3305 boolean_t empty; 3306 int idx; 3307 mmu_short_pte_t *c_pte; 3308 3309 idx = MMU_TIC(start); 3310 c_pte = &c_tbl->ct_dtbl[idx]; 3311 for (;start < end; start += MMU_PAGE_SIZE, c_pte++) { 3312 if (MMU_VALID_DT(*c_pte)) { 3313 pmap_remove_pte(c_pte); 3314 c_tbl->ct_ecnt--; 3315 } 3316 } 3317 3318 if (c_tbl->ct_ecnt == 0) { 3319 c_tbl->ct_parent = NULL; 3320 TAILQ_REMOVE(&c_pool, c_tbl, ct_link); 3321 TAILQ_INSERT_HEAD(&c_pool, c_tbl, ct_link); 3322 empty = TRUE; 3323 } else { 3324 empty = FALSE; 3325 } 3326 3327 return empty; 3328 } 3329 3330 /* is_managed INTERNAL 3331 ** 3332 * Determine if the given physical address is managed by the PV system. 3333 * Note that this logic assumes that no one will ask for the status of 3334 * addresses which lie in-between the memory banks on the 3/80. If they 3335 * do so, it will falsely report that it is managed. 3336 * 3337 * Note: A "managed" address is one that was reported to the VM system as 3338 * a "usable page" during system startup. As such, the VM system expects the 3339 * pmap module to keep an accurate track of the useage of those pages. 3340 * Any page not given to the VM system at startup does not exist (as far as 3341 * the VM system is concerned) and is therefore "unmanaged." Examples are 3342 * those pages which belong to the ROM monitor and the memory allocated before 3343 * the VM system was started. 3344 */ 3345 boolean_t 3346 is_managed(pa) 3347 paddr_t pa; 3348 { 3349 if (pa >= avail_start && pa < avail_end) 3350 return TRUE; 3351 else 3352 return FALSE; 3353 } 3354 3355 /* pmap_bootstrap_alloc INTERNAL 3356 ** 3357 * Used internally for memory allocation at startup when malloc is not 3358 * available. This code will fail once it crosses the first memory 3359 * bank boundary on the 3/80. Hopefully by then however, the VM system 3360 * will be in charge of allocation. 3361 */ 3362 void * 3363 pmap_bootstrap_alloc(size) 3364 int size; 3365 { 3366 void *rtn; 3367 3368 #ifdef PMAP_DEBUG 3369 if (bootstrap_alloc_enabled == FALSE) { 3370 mon_printf("pmap_bootstrap_alloc: disabled\n"); 3371 sunmon_abort(); 3372 } 3373 #endif 3374 3375 rtn = (void *) virtual_avail; 3376 virtual_avail += size; 3377 3378 #ifdef PMAP_DEBUG 3379 if (virtual_avail > virtual_contig_end) { 3380 mon_printf("pmap_bootstrap_alloc: out of mem\n"); 3381 sunmon_abort(); 3382 } 3383 #endif 3384 3385 return rtn; 3386 } 3387 3388 /* pmap_bootstap_aalign INTERNAL 3389 ** 3390 * Used to insure that the next call to pmap_bootstrap_alloc() will 3391 * return a chunk of memory aligned to the specified size. 3392 * 3393 * Note: This function will only support alignment sizes that are powers 3394 * of two. 3395 */ 3396 void 3397 pmap_bootstrap_aalign(size) 3398 int size; 3399 { 3400 int off; 3401 3402 off = virtual_avail & (size - 1); 3403 if (off) { 3404 (void) pmap_bootstrap_alloc(size - off); 3405 } 3406 } 3407 3408 /* pmap_pa_exists 3409 ** 3410 * Used by the /dev/mem driver to see if a given PA is memory 3411 * that can be mapped. (The PA is not in a hole.) 3412 */ 3413 int 3414 pmap_pa_exists(pa) 3415 paddr_t pa; 3416 { 3417 int i; 3418 3419 for (i = 0; i < SUN3X_NPHYS_RAM_SEGS; i++) { 3420 if ((pa >= avail_mem[i].pmem_start) && 3421 (pa < avail_mem[i].pmem_end)) 3422 return (1); 3423 if (avail_mem[i].pmem_next == NULL) 3424 break; 3425 } 3426 return (0); 3427 } 3428 3429 /* Called only from locore.s and pmap.c */ 3430 void _pmap_switch __P((pmap_t pmap)); 3431 3432 /* 3433 * _pmap_switch INTERNAL 3434 * 3435 * This is called by locore.s:cpu_switch() when it is 3436 * switching to a new process. Load new translations. 3437 * Note: done in-line by locore.s unless PMAP_DEBUG 3438 * 3439 * Note that we do NOT allocate a context here, but 3440 * share the "kernel only" context until we really 3441 * need our own context for user-space mappings in 3442 * pmap_enter_user(). [ s/context/mmu A table/ ] 3443 */ 3444 void 3445 _pmap_switch(pmap) 3446 pmap_t pmap; 3447 { 3448 u_long rootpa; 3449 3450 /* 3451 * Only do reload/flush if we have to. 3452 * Note that if the old and new process 3453 * were BOTH using the "null" context, 3454 * then this will NOT flush the TLB. 3455 */ 3456 rootpa = pmap->pm_a_phys; 3457 if (kernel_crp.rp_addr != rootpa) { 3458 DPRINT(("pmap_activate(%p)\n", pmap)); 3459 kernel_crp.rp_addr = rootpa; 3460 loadcrp(&kernel_crp); 3461 TBIAU(); 3462 } 3463 } 3464 3465 /* 3466 * Exported version of pmap_activate(). This is called from the 3467 * machine-independent VM code when a process is given a new pmap. 3468 * If (p == curproc) do like cpu_switch would do; otherwise just 3469 * take this as notification that the process has a new pmap. 3470 */ 3471 void 3472 pmap_activate(p) 3473 struct proc *p; 3474 { 3475 if (p == curproc) { 3476 _pmap_switch(p->p_vmspace->vm_map.pmap); 3477 } 3478 } 3479 3480 /* 3481 * pmap_deactivate INTERFACE 3482 ** 3483 * This is called to deactivate the specified process's address space. 3484 */ 3485 void 3486 pmap_deactivate(p) 3487 struct proc *p; 3488 { 3489 /* Nothing to do. */ 3490 } 3491 3492 /* 3493 * Fill in the sun3x-specific part of the kernel core header 3494 * for dumpsys(). (See machdep.c for the rest.) 3495 */ 3496 void 3497 pmap_kcore_hdr(sh) 3498 struct sun3x_kcore_hdr *sh; 3499 { 3500 u_long spa, len; 3501 int i; 3502 3503 sh->pg_frame = MMU_SHORT_PTE_BASEADDR; 3504 sh->pg_valid = MMU_DT_PAGE; 3505 sh->contig_end = virtual_contig_end; 3506 sh->kernCbase = (u_long)kernCbase; 3507 for (i = 0; i < SUN3X_NPHYS_RAM_SEGS; i++) { 3508 spa = avail_mem[i].pmem_start; 3509 spa = m68k_trunc_page(spa); 3510 len = avail_mem[i].pmem_end - spa; 3511 len = m68k_round_page(len); 3512 sh->ram_segs[i].start = spa; 3513 sh->ram_segs[i].size = len; 3514 } 3515 } 3516 3517 3518 /* pmap_virtual_space INTERFACE 3519 ** 3520 * Return the current available range of virtual addresses in the 3521 * arguuments provided. Only really called once. 3522 */ 3523 void 3524 pmap_virtual_space(vstart, vend) 3525 vaddr_t *vstart, *vend; 3526 { 3527 *vstart = virtual_avail; 3528 *vend = virtual_end; 3529 } 3530 3531 /* 3532 * Provide memory to the VM system. 3533 * 3534 * Assume avail_start is always in the 3535 * first segment as pmap_bootstrap does. 3536 */ 3537 static void 3538 pmap_page_upload() 3539 { 3540 paddr_t a, b; /* memory range */ 3541 int i; 3542 3543 /* Supply the memory in segments. */ 3544 for (i = 0; i < SUN3X_NPHYS_RAM_SEGS; i++) { 3545 a = atop(avail_mem[i].pmem_start); 3546 b = atop(avail_mem[i].pmem_end); 3547 if (i == 0) 3548 a = atop(avail_start); 3549 if (avail_mem[i].pmem_end > avail_end) 3550 b = atop(avail_end); 3551 3552 uvm_page_physload(a, b, a, b, VM_FREELIST_DEFAULT); 3553 3554 if (avail_mem[i].pmem_next == NULL) 3555 break; 3556 } 3557 } 3558 3559 /* pmap_count INTERFACE 3560 ** 3561 * Return the number of resident (valid) pages in the given pmap. 3562 * 3563 * Note: If this function is handed the kernel map, it will report 3564 * that it has no mappings. Hopefully the VM system won't ask for kernel 3565 * map statistics. 3566 */ 3567 segsz_t 3568 pmap_count(pmap, type) 3569 pmap_t pmap; 3570 int type; 3571 { 3572 u_int count; 3573 int a_idx, b_idx; 3574 a_tmgr_t *a_tbl; 3575 b_tmgr_t *b_tbl; 3576 c_tmgr_t *c_tbl; 3577 3578 /* 3579 * If the pmap does not have its own A table manager, it has no 3580 * valid entires. 3581 */ 3582 if (pmap->pm_a_tmgr == NULL) 3583 return 0; 3584 3585 a_tbl = pmap->pm_a_tmgr; 3586 3587 count = 0; 3588 for (a_idx = 0; a_idx < MMU_TIA(KERNBASE); a_idx++) { 3589 if (MMU_VALID_DT(a_tbl->at_dtbl[a_idx])) { 3590 b_tbl = mmuB2tmgr(mmu_ptov(a_tbl->at_dtbl[a_idx].addr.raw)); 3591 for (b_idx = 0; b_idx < MMU_B_TBL_SIZE; b_idx++) { 3592 if (MMU_VALID_DT(b_tbl->bt_dtbl[b_idx])) { 3593 c_tbl = mmuC2tmgr( 3594 mmu_ptov(MMU_DTE_PA(b_tbl->bt_dtbl[b_idx]))); 3595 if (type == 0) 3596 /* 3597 * A resident entry count has been requested. 3598 */ 3599 count += c_tbl->ct_ecnt; 3600 else 3601 /* 3602 * A wired entry count has been requested. 3603 */ 3604 count += c_tbl->ct_wcnt; 3605 } 3606 } 3607 } 3608 } 3609 3610 return count; 3611 } 3612 3613 /************************ SUN3 COMPATIBILITY ROUTINES ******************** 3614 * The following routines are only used by DDB for tricky kernel text * 3615 * text operations in db_memrw.c. They are provided for sun3 * 3616 * compatibility. * 3617 *************************************************************************/ 3618 /* get_pte INTERNAL 3619 ** 3620 * Return the page descriptor the describes the kernel mapping 3621 * of the given virtual address. 3622 */ 3623 extern u_long ptest_addr __P((u_long)); /* XXX: locore.s */ 3624 u_int 3625 get_pte(va) 3626 vaddr_t va; 3627 { 3628 u_long pte_pa; 3629 mmu_short_pte_t *pte; 3630 3631 /* Get the physical address of the PTE */ 3632 pte_pa = ptest_addr(va & ~PGOFSET); 3633 3634 /* Convert to a virtual address... */ 3635 pte = (mmu_short_pte_t *) (KERNBASE + pte_pa); 3636 3637 /* Make sure it is in our level-C tables... */ 3638 if ((pte < kernCbase) || 3639 (pte >= &mmuCbase[NUM_USER_PTES])) 3640 return 0; 3641 3642 /* ... and just return its contents. */ 3643 return (pte->attr.raw); 3644 } 3645 3646 3647 /* set_pte INTERNAL 3648 ** 3649 * Set the page descriptor that describes the kernel mapping 3650 * of the given virtual address. 3651 */ 3652 void 3653 set_pte(va, pte) 3654 vaddr_t va; 3655 u_int pte; 3656 { 3657 u_long idx; 3658 3659 if (va < KERNBASE) 3660 return; 3661 3662 idx = (unsigned long) m68k_btop(va - KERNBASE); 3663 kernCbase[idx].attr.raw = pte; 3664 TBIS(va); 3665 } 3666 3667 /* 3668 * Routine: pmap_procwr 3669 * 3670 * Function: 3671 * Synchronize caches corresponding to [addr, addr+len) in p. 3672 */ 3673 void 3674 pmap_procwr(p, va, len) 3675 struct proc *p; 3676 vaddr_t va; 3677 size_t len; 3678 { 3679 (void)cachectl1(0x80000004, va, len, p); 3680 } 3681 3682 3683 #ifdef PMAP_DEBUG 3684 /************************** DEBUGGING ROUTINES ************************** 3685 * The following routines are meant to be an aid to debugging the pmap * 3686 * system. They are callable from the DDB command line and should be * 3687 * prepared to be handed unstable or incomplete states of the system. * 3688 ************************************************************************/ 3689 3690 /* pv_list 3691 ** 3692 * List all pages found on the pv list for the given physical page. 3693 * To avoid endless loops, the listing will stop at the end of the list 3694 * or after 'n' entries - whichever comes first. 3695 */ 3696 void 3697 pv_list(pa, n) 3698 paddr_t pa; 3699 int n; 3700 { 3701 int idx; 3702 vaddr_t va; 3703 pv_t *pv; 3704 c_tmgr_t *c_tbl; 3705 pmap_t pmap; 3706 3707 pv = pa2pv(pa); 3708 idx = pv->pv_idx; 3709 for (; idx != PVE_EOL && n > 0; idx = pvebase[idx].pve_next, n--) { 3710 va = pmap_get_pteinfo(idx, &pmap, &c_tbl); 3711 printf("idx %d, pmap 0x%x, va 0x%x, c_tbl %x\n", 3712 idx, (u_int) pmap, (u_int) va, (u_int) c_tbl); 3713 } 3714 } 3715 #endif /* PMAP_DEBUG */ 3716 3717 #ifdef NOT_YET 3718 /* and maybe not ever */ 3719 /************************** LOW-LEVEL ROUTINES ************************** 3720 * These routines will eventualy be re-written into assembly and placed * 3721 * in locore.s. They are here now as stubs so that the pmap module can * 3722 * be linked as a standalone user program for testing. * 3723 ************************************************************************/ 3724 /* flush_atc_crp INTERNAL 3725 ** 3726 * Flush all page descriptors derived from the given CPU Root Pointer 3727 * (CRP), or 'A' table as it is known here, from the 68851's automatic 3728 * cache. 3729 */ 3730 void 3731 flush_atc_crp(a_tbl) 3732 { 3733 mmu_long_rp_t rp; 3734 3735 /* Create a temporary root table pointer that points to the 3736 * given A table. 3737 */ 3738 rp.attr.raw = ~MMU_LONG_RP_LU; 3739 rp.addr.raw = (unsigned int) a_tbl; 3740 3741 mmu_pflushr(&rp); 3742 /* mmu_pflushr: 3743 * movel sp(4)@,a0 3744 * pflushr a0@ 3745 * rts 3746 */ 3747 } 3748 #endif /* NOT_YET */ 3749