1 /* $NetBSD: intr.h,v 1.13 2001/06/04 15:34:57 ragge Exp $ */ 2 3 /* 4 * Copyright (c) 1998 Matt Thomas. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the company nor the name of the author may be used to 16 * endorse or promote products derived from this software without specific 17 * prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 20 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 #ifndef _VAX_INTR_H_ 33 #define _VAX_INTR_H_ 34 35 #include <sys/queue.h> 36 37 /* Define the various Interrupt Priority Levels */ 38 39 /* Interrupt Priority Levels are not mutually exclusive. */ 40 41 /* Hardware interrupt levels are 16 (0x10) thru 31 (0x1f) 42 */ 43 #define IPL_HIGH 0x1f /* high -- blocks all interrupts */ 44 #define IPL_CLOCK 0x18 /* clock */ 45 #define IPL_UBA 0x17 /* unibus adapters */ 46 #define IPL_IMP 0x17 /* memory allocation */ 47 #define IPL_NET 0x16 /* network */ 48 #define IPL_BIO 0x15 /* block I/O */ 49 #define IPL_TTY 0x15 /* terminal */ 50 #define IPL_AUDIO 0x15 /* audio */ 51 #define IPL_IPI 0x14 /* interprocessor interrupt */ 52 #define IPL_CONSMEDIA 0x14 /* console media */ 53 54 /* Software interrupt level s are 0 (0x00) thru 15 (0x0f) 55 */ 56 #define IPL_SOFTDDB 0x0f /* used by DDB on VAX */ 57 #define IPL_SOFTSERIAL 0x0d /* soft serial */ 58 #define IPL_SOFTNET 0x0c /* soft network */ 59 #define IPL_SOFTCLOCK 0x08 60 #define IPL_NONE 0x00 61 62 #define IPL_LEVELS 32 63 64 #define IST_UNUSABLE -1 /* interrupt cannot be used */ 65 #define IST_NONE 0 /* none (dummy) */ 66 #define IST_PULSE 1 /* pulsed */ 67 #define IST_EDGE 2 /* edge-triggered */ 68 #define IST_LEVEL 3 /* level-triggered */ 69 70 71 #ifdef _KERNEL 72 #ifndef lint 73 #define splx(reg) \ 74 ({ \ 75 register int val; \ 76 __asm __volatile ("mfpr $0x12,%0;mtpr %1,$0x12" \ 77 : "=&g" (val) \ 78 : "g" (reg)); \ 79 val; \ 80 }) 81 82 #define _splset(reg) \ 83 ((void)({ \ 84 __asm __volatile ("mtpr %0,$0x12" \ 85 : \ 86 : "g" (reg)); \ 87 })) 88 89 #define _splraise(reg) \ 90 ({ \ 91 register int val; \ 92 __asm __volatile ("mfpr $0x12,%0" \ 93 : "=&g" (val) \ 94 : ); \ 95 if ((reg) > val) { \ 96 _splset(reg); \ 97 } \ 98 val; \ 99 }) 100 101 #define _setsirr(reg) \ 102 do { \ 103 __asm __volatile ("mtpr %0,$0x14" \ 104 : \ 105 : "g" (reg)); \ 106 } while (0) 107 #endif 108 109 #define spl0() _splset(IPL_NONE) /* IPL00 */ 110 #define spllowersoftclock() _splset(IPL_SOFTCLOCK) /* IPL08 */ 111 #define splsoftclock() _splraise(IPL_SOFTCLOCK) /* IPL08 */ 112 #define splsoftnet() _splraise(IPL_SOFTNET) /* IPL0C */ 113 #define splsoftserial() _splraise(IPL_SOFTSERIAL) /* IPL0D */ 114 #define splddb() _splraise(IPL_SOFTDDB) /* IPL0F */ 115 #define splconsmedia() _splraise(IPL_CONSMEDIA) /* IPL14 */ 116 #define splipi() _splraise(IPL_IPI) /* IPL14 */ 117 #define splbio() _splraise(IPL_BIO) /* IPL15 */ 118 #define spltty() _splraise(IPL_TTY) /* IPL15 */ 119 #define splnet() _splraise(IPL_NET) /* IPL16 */ 120 #define splvm() _splraise(IPL_IMP) /* IPL17 */ 121 #define splclock() _splraise(IPL_CLOCK) /* IPL18 */ 122 #define splhigh() _splraise(IPL_HIGH) /* IPL1F */ 123 #define splstatclock() splclock() 124 125 #define splsched() splhigh() 126 #define spllock() splhigh() 127 128 /* These are better to use when playing with VAX buses */ 129 #define spluba() _splraise(IPL_UBA) /* IPL17 */ 130 #define spl4() splx(0x14) 131 #define spl5() splx(0x15) 132 #define spl6() splx(0x16) 133 #define spl7() splx(0x17) 134 135 /* schedule software interrupts 136 */ 137 #define setsoftddb() _setsirr(IPL_SOFTDDB) 138 #define setsoftserial() _setsirr(IPL_SOFTSERIAL) 139 #define setsoftnet() _setsirr(IPL_SOFTNET) 140 141 #if !defined(_LOCORE) 142 LIST_HEAD(sh_head, softintr_handler); 143 144 struct softintr_head { 145 int shd_ipl; 146 struct sh_head shd_intrs; 147 }; 148 149 struct softintr_handler { 150 struct softintr_head *sh_head; 151 LIST_ENTRY(softintr_handler) sh_link; 152 void (*sh_func)(void *); 153 void *sh_arg; 154 int sh_pending; 155 }; 156 157 extern void *softintr_establish(int, void (*)(void *), void *); 158 extern void softintr_disestablish(void *); 159 160 static __inline void 161 softintr_schedule(void *arg) 162 { 163 struct softintr_handler * const sh = arg; 164 sh->sh_pending = 1; 165 _setsirr(sh->sh_head->shd_ipl); 166 } 167 #endif /* _LOCORE */ 168 #endif /* _KERNEL */ 169 #endif /* _VAX_INTR_H */ 170