1 /* $NetBSD: ka650.h,v 1.9 2002/12/01 21:21:45 matt Exp $ */ 2 /* 3 * Copyright (c) 1988 The Regents of the University of California. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to Berkeley by 7 * Mt. Xinu. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the University of 20 * California, Berkeley and its contributors. 21 * 4. Neither the name of the University nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * @(#)ka650.h 7.5 (Berkeley) 6/28/90 38 */ 39 40 #ifndef _VAX_KA650_H_ 41 #define _VAX_KA650_H_ 42 43 /* 44 * 45 * Definitions specific to the ka650 (uVAX 3600/3602) cpu card. 46 */ 47 48 /* 49 * CAER: Memory System Error Register (IPR 39) 50 */ 51 #define CAER_DAL 0x00000040 /* CDAL or level 2 cache data parity */ 52 #define CAER_MCD 0x00000020 /* mcheck due to DAL parity error */ 53 #define CAER_MCC 0x00000010 /* mcheck due to 1st lev cache parity */ 54 #define CAER_DAT 0x00000002 /* data parity in 1st level cache */ 55 #define CAER_TAG 0x00000001 /* tag parity in 1st level cache */ 56 57 /* 58 * CADR: Cache Disable Register (IPR 37) 59 */ 60 #define CADR_STMASK 0x000000f0 /* 1st level cache state mask */ 61 #define CADR_SEN2 0x00000080 /* 1st level cache set 2 enabled */ 62 #define CADR_SEN1 0x00000040 /* 1st level cache set 1 enabled */ 63 #define CADR_CENI 0x00000020 /* 1st level I-stream caching enabled */ 64 #define CADR_CEND 0x00000010 /* 1st level D-stream caching enabled */ 65 66 /* 67 * Internal State Info 2: (for mcheck recovery) 68 */ 69 #define IS2_VCR 0x00008000 /* VAX Can't Restart flag */ 70 71 /* 72 * DMA System Error Register (merr_dser) 73 */ 74 #define DSER_QNXM 0x00000080 /* Q-22 Bus NXM */ 75 #define DSER_QPE 0x00000020 /* Q-22 Bus parity Error */ 76 #define DSER_MEM 0x00000010 /* Main mem err due to ext dev DMA */ 77 #define DSER_LOST 0x00000008 /* Lost error: DSER <7,5,4,0> set */ 78 #define DSER_NOGRANT 0x00000004 /* No Grant timeout on cpu demand R/W */ 79 #define DSER_DNXM 0x00000001 /* DMA NXM */ 80 #define DSER_CLEAR (DSER_QNXM | DSER_QPE | DSER_MEM | \ 81 DSER_LOST | DSER_NOGRANT | DSER_DNXM) 82 #define DMASER_BITS \ 83 "\20\20BHALT\17DCNEG\10QBNXM\6QBPE\5MEMERR\4LOSTERR\3NOGRANT\1DMANXM" 84 85 #ifndef _LOCORE 86 /* 87 * Local registers (in I/O space) 88 * This is done in disjoint sections. Map names are set in locore.s 89 * and they are mapped in routine configcpu() 90 */ 91 92 /* 93 * memory error & configuration registers 94 */ 95 struct ka650_merr { 96 u_long merr_scr; /* System Config Register */ 97 u_long merr_dser; /* DMA System Error Register */ 98 u_long merr_qbear; /* QBus Error Address Register */ 99 u_long merr_dear; /* DMA Error Address Register */ 100 u_long merr_qbmbr; /* Q Bus Map Base address Register */ 101 u_long pad[59]; 102 u_long merr_csr[16]; /* Main Memory Config Regs (16 banks) */ 103 u_long merr_errstat; /* Main Memory Error Status */ 104 u_long merr_cont; /* Main Memory Control */ 105 }; 106 #define KA650_MERR 0x20080000 107 108 /* 109 * Main Memory Error Status Register (merr_errstat) 110 */ 111 #define MEM_EMASK 0xe0000180 /* mask of all err bits */ 112 #define MEM_RDS 0x80000000 /* uncorrectable main memory */ 113 #define MEM_RDSHIGH 0x40000000 /* high rate RDS errors */ 114 #define MEM_CRD 0x20000000 /* correctable main memory */ 115 #define MEM_DMA 0x00000100 /* DMA read or write error */ 116 #define MEM_CDAL 0x00000080 /* CDAL Parity error on write */ 117 #define MEM_PAGE 0x1ffffe00 /* Offending Page Number */ 118 #define MEM_PAGESHFT 9 /* Shift to normalize page number */ 119 120 /* 121 * Main Memory Control & Diag Status Reg (merr_cont) 122 */ 123 #define MEM_CRDINT 0x00001000 /* CRD interrupts enabled */ 124 #define MEM_REFRESH 0x00000800 /* Forced memory refresh */ 125 #define MEM_ERRDIS 0x00000400 /* error detect disable */ 126 #define MEM_DIAG 0x00000080 /* Diagnostics mode */ 127 #define MEM_CHECK 0x0000007f /* check bits for diagnostic mode */ 128 129 /* 130 * Main Memory Config Regs (merr_csr[0-15]) 131 */ 132 #define MEM_BNKENBLE 0x80000000 /* Bank Enable */ 133 #define MEM_BNKNUM 0x03c00000 /* Physical map Bank number */ 134 #define MEM_BNKUSAGE 0x00000003 /* Bank Usage */ 135 136 /* 137 * Cache Control & Boot/Diag registers 138 */ 139 struct ka650_cbd { 140 u_char cbd_cacr; /* Low byte: Cache Enable & Parity Err detect */ 141 u_char cbd_cdf1; /* Cache diagnostic field (unused) */ 142 u_char cbd_cdf2; /* Cache diagnostic field (unused) */ 143 u_char pad; 144 u_long cbd_bdr; /* Boot & Diagnostic Register (unused) */ 145 }; 146 #define KA650_CBD 0x20084000 147 148 /* 149 * CACR: Cache Control Register (2nd level cache) (cbd_cacr) 150 */ 151 #define CACR_CEN 0x00000010 /* Cache enable */ 152 #define CACR_CPE 0x00000020 /* Cache Parity Error */ 153 154 /* 155 * System Support Chip (SSC) registers 156 */ 157 struct ka650_ssc { 158 u_long ssc_sscbr; /* SSC Base Addr Register */ 159 u_long pad1[3]; 160 u_long ssc_ssccr; /* SSC Configuration Register */ 161 u_long pad2[3]; 162 u_long ssc_cbtcr; /* CDAL Bus Timeout Control Register */ 163 u_long pad3[55]; 164 u_long ssc_tcr0; /* timer control reg 0 */ 165 u_long ssc_tir0; /* timer interval reg 0 */ 166 u_long ssc_tnir0; /* timer next interval reg 0 */ 167 u_long ssc_tivr0; /* timer interrupt vector reg 0 */ 168 u_long ssc_tcr1; /* timer control reg 1 */ 169 u_long ssc_tir1; /* timer interval reg 1 */ 170 u_long ssc_tnir1; /* timer next interval reg 1 */ 171 u_long ssc_tivr1; /* timer interrupt vector reg 1 */ 172 u_long pad4[184]; 173 u_char ssc_cpmbx; /* Console Program Mail Box: Lang & Hact */ 174 u_char ssc_terminfo; /* TTY info: Video Dev, MCS, CRT & ROM flags */ 175 u_char ssc_keyboard; /* Keyboard code */ 176 }; 177 #define KA650_SSC 0x20140000 178 179 /* 180 * CBTCR: CDAL Bus Timeout Control Register (ssc_cbtcr) 181 */ 182 #define CBTCR_BTO 0x80000000 /* r/w unimp IPR or unack intr */ 183 #define CBTCR_RWT 0x40000000 /* CDAL Bus Timeout on CPU or DMA */ 184 185 /* 186 * TCR0/TCR1: Programable Timer Control Registers (ssc_tcr[01]) 187 * (The rest of the bits are the same as in the standard VAX 188 * Interval timer and are defined in clock.h) 189 */ 190 #define TCR_STP 0x00000004 /* Stop after time-out */ 191 192 /* 193 * Flags for Console Program Mail Box 194 */ 195 #define CPMB650_HALTACT 0x03 /* Field for halt action */ 196 #define CPMB650_RESTART 0x01 /* Restart */ 197 #define CPMB650_REBOOT 0x02 /* Reboot */ 198 #define CPMB650_HALT 0x03 /* Halt */ 199 #define CPMB650_BIP 0x04 /* Bootstrap in progress */ 200 #define CPMB650_RIP 0x08 /* Restart in progress */ 201 #define CPMB650_DOTHIS 0x30 /* Execute sommand */ 202 #define CPMB650_LANG 0xf0 /* Language field */ 203 204 /* 205 * Inter Processor Communication Register 206 * To determine if memory error was from QBUS device DMA (as opposed to cpu). 207 */ 208 struct ka650_ipcr { 209 u_long pad[80]; 210 u_short ipcr0; /* InterProcessor Comm Reg for arbiter */ 211 }; 212 #define KA650_IPCR 0x20001e00 213 214 #endif /* _LOCORE */ 215 216 /* 217 * Physical start address of the Qbus memory. 218 * The q-bus memory size is 4 meg. 219 * Physical start address of the I/O space (where the 8Kbyte I/O page is). 220 */ 221 #define KA650_QMEM 0x30000000 222 #define KA650_QMEMSIZE (512*8192) 223 #define KA650_QDEVADDR 0x20000000 224 225 /* 226 * Mapping info for Cache Entries, including 227 * Size (in bytes) of 2nd Level Cache for cache flush operation 228 */ 229 #define KA650_CACHE 0x10000000 230 #define KA650_CACHESIZE (64*1024) 231 232 /* 233 * Useful ROM addresses 234 */ 235 #define KA650ROM_SIDEX 0x20060004 /* system ID extension */ 236 #define KA650ROM_GETC 0x20060008 /* (jsb) get character from console */ 237 #define KA650ROM_PUTS 0x2006000c /* (jsb) put string to console */ 238 #define KA650ROM_GETS 0x20060010 /* (jsb) read string with prompt */ 239 #define KA650_CONSTYPE 0x20140401 /* byte at which console type resides */ 240 241 /* 242 * Some useful macros 243 */ 244 #define GETCPUTYPE(x) ((x >> 24) & 0xff) 245 #define GETSYSSUBT(x) ((x >> 8) & 0xff) 246 #define GETFRMREV(x) ((x >> 16) & 0xff) 247 #define GETCODREV(x) (x & 0xff) 248 249 #endif /* _VAX_KA650_H_ */ 250