1 /* $NetBSD: ka820.h,v 1.4 2001/06/03 15:10:34 ragge Exp $ */ 2 /* 3 * Copyright (c) 1988 Regents of the University of California. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to Berkeley by 7 * Chris Torek. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the University of 20 * California, Berkeley and its contributors. 21 * 4. Neither the name of the University nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * @(#)ka820.h 7.3 (Berkeley) 6/28/90 38 */ 39 40 /* 41 * Definitions specific to the ka820 cpu. 42 */ 43 44 /* 45 * Device addresses. 46 */ 47 #define KA820_PORTADDR 0x20088000 /* port controller */ 48 #define KA820_BRAMADDR 0x20090000 /* boot ram */ 49 #define KA820_EEPROMADDR 0x20098000 /* eeprom */ 50 #define KA820_RX50ADDR 0x200b0000 /* rcx50 */ 51 #define KA820_CLOCKADDR 0x200b8000 /* watch chip */ 52 53 /* 54 * Sizes. The port controller, RCX50, and watch chip are all one page. 55 */ 56 #define KA820_BRPAGES 16 /* 8K */ 57 #define KA820_EEPAGES 64 /* 32K */ 58 59 /* port controller CSR bit values */ 60 #define KA820PORT_RSTHALT 0x80000000 /* restart halt */ 61 #define KA820PORT_LCONS 0x40000000 /* logical console */ 62 #define KA820PORT_LCONSEN 0x20000000 /* logical console enable */ 63 #define KA820PORT_BIRESET 0x10000000 /* BI reset */ 64 #define KA820PORT_BISTF 0x08000000 /* ??? */ 65 #define KA820PORT_ENBAPT 0x04000000 /* ??? */ 66 #define KA820PORT_STPASS 0x02000000 /* self test pass */ 67 #define KA820PORT_RUN 0x01000000 /* run */ 68 #define KA820PORT_WWPE 0x00800000 /* ??? parity even? */ 69 #define KA820PORT_EVLCK 0x00400000 /* event lock */ 70 #define KA820PORT_WMEM 0x00200000 /* write mem */ 71 #define KA820PORT_EV4 0x00100000 /* event 4 */ 72 #define KA820PORT_EV3 0x00080000 /* event 3 */ 73 #define KA820PORT_EV2 0x00040000 /* event 2 */ 74 #define KA820PORT_EV1 0x00020000 /* event 1 */ 75 #define KA820PORT_EV0 0x00010000 /* event 0 */ 76 #define KA820PORT_WWPO 0x00008000 /* ??? parity odd? */ 77 #define KA820PORT_PERH 0x00004000 /* parity error H */ 78 #define KA820PORT_ENBPIPE 0x00002000 /* enable? pipe */ 79 #define KA820PORT_TIMEOUT 0x00001000 /* timeout */ 80 #define KA820PORT_RSVD 0x00000800 /* reserved */ 81 #define KA820PORT_CONSEN 0x00000400 /* console interrupt enable */ 82 #define KA820PORT_CONSCLR 0x00000200 /* clear console interrupt */ 83 #define KA820PORT_CONSINTR 0x00000100 /* console interrupt req */ 84 #define KA820PORT_RXIE 0x00000080 /* RX50 interrupt enable */ 85 #define KA820PORT_RXCLR 0x00000040 /* clear RX50 interrupt */ 86 #define KA820PORT_RXIRQ 0x00000020 /* RX50 interrupt request */ 87 #define KA820PORT_IPCLR 0x00000010 /* clear IP interrupt */ 88 #define KA820PORT_IPINTR 0x00000008 /* IP interrupt request */ 89 #define KA820PORT_CRDEN 0x00000004 /* enable CRD interrupts */ 90 #define KA820PORT_CRDCLR 0x00000002 /* clear CRD interrupt */ 91 #define KA820PORT_CRDINTR 0x00000001 /* CRD interrupt request */ 92 93 /* interrupt vectors unique for this CPU */ 94 #define KA820_INT_RXCD 0x58 95 #define KA820_INT_IPINTR 0x80 96 97 /* what the heck */ 98 #define KA820PORT_BITS \ 99 "\20\40RSTHALT\37LCONS\36LCONSEN\35BIRESET\34BISTF\33ENBAPT\32STPASS\31RUN\ 100 \30WWPE\27EVLCK\26WMEM\25EV4\24EV3\23EV2\22EV1\21EV\20WWPO\17PERH\16ENBPIPE\ 101 \15TIMEOUT\13CONSEN\12CONSCLR\11CONSINTR\10RXIE\7RXCLR\6RXIRQ\5IPCLR\4IPINTR\ 102 \3CRDEN\2CLRCLR\1CRDINTR" 103 104 /* clock CSR bit values, per csr */ 105 #define KA820CLK_0_BUSY 0x01 /* busy (time changing) */ 106 #define KA820CLK_1_GO 0x0c /* run */ 107 #define KA820CLK_1_SET 0x0d /* set the time */ 108 #define KA820CLK_3_VALID 0x01 /* clock is valid */ 109 110 #ifndef LOCORE 111 struct ka820port { 112 u_long csr; 113 /* that seems to be all.... */ 114 }; 115 116 struct ka820clock { 117 u_char sec; 118 u_char pad0; 119 u_char secalrm; 120 u_char pad1; 121 u_char min; 122 u_char pad2; 123 u_char minalrm; 124 u_char pad3; 125 u_char hr; 126 u_char pad4; 127 u_char hralrm; 128 u_char pad5; 129 u_char dayofwk; 130 u_char pad6; 131 u_char day; 132 u_char pad7; 133 u_char mon; 134 u_char pad8; 135 u_char yr; 136 u_char pad9; 137 u_short csr0; 138 u_short csr1; 139 u_short csr2; 140 u_short csr3; 141 }; 142 143 void crxintr __P((void *arg)); 144 #endif 145