1*61158d87Sriastradh /* $NetBSD: qvaux.c,v 1.5 2022/10/27 00:00:25 riastradh Exp $ */
2707b9604Smatt
3707b9604Smatt /*-
4707b9604Smatt * Copyright (c) 2015 The NetBSD Foundation, Inc.
5707b9604Smatt * All rights reserved.
6707b9604Smatt *
7707b9604Smatt * This code is derived from software contributed to The NetBSD Foundation
8707b9604Smatt * by Charles H. Dickman
9707b9604Smatt *
10707b9604Smatt * Redistribution and use in source and binary forms, with or without
11707b9604Smatt * modification, are permitted provided that the following conditions
12707b9604Smatt * are met:
13707b9604Smatt * 1. Redistributions of source code must retain the above copyright
14707b9604Smatt * notice, this list of conditions and the following disclaimer.
15707b9604Smatt * 2. Redistributions in binary form must reproduce the above copyright
16707b9604Smatt * notice, this list of conditions and the following disclaimer in the
17707b9604Smatt * documentation and/or other materials provided with the distribution.
18707b9604Smatt *
19707b9604Smatt * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20707b9604Smatt * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21707b9604Smatt * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22707b9604Smatt * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23707b9604Smatt * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24707b9604Smatt * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25707b9604Smatt * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26707b9604Smatt * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27707b9604Smatt * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28707b9604Smatt * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29707b9604Smatt * POSSIBILITY OF SUCH DAMAGE.
30707b9604Smatt */
31707b9604Smatt
32707b9604Smatt /*
33707b9604Smatt * Copyright (c) 1992, 1993
34707b9604Smatt * The Regents of the University of California. All rights reserved.
35707b9604Smatt *
36707b9604Smatt * This code is derived from software contributed to Berkeley by
37707b9604Smatt * Ralph Campbell and Rick Macklem.
38707b9604Smatt *
39707b9604Smatt * Redistribution and use in source and binary forms, with or without
40707b9604Smatt * modification, are permitted provided that the following conditions
41707b9604Smatt * are met:
42707b9604Smatt * 1. Redistributions of source code must retain the above copyright
43707b9604Smatt * notice, this list of conditions and the following disclaimer.
44707b9604Smatt * 2. Redistributions in binary form must reproduce the above copyright
45707b9604Smatt * notice, this list of conditions and the following disclaimer in the
46707b9604Smatt * documentation and/or other materials provided with the distribution.
47707b9604Smatt * 3. Neither the name of the University nor the names of its contributors
48707b9604Smatt * may be used to endorse or promote products derived from this software
49707b9604Smatt * without specific prior written permission.
50707b9604Smatt *
51707b9604Smatt * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
52707b9604Smatt * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
53707b9604Smatt * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
54707b9604Smatt * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
55707b9604Smatt * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
56707b9604Smatt * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
57707b9604Smatt * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
58707b9604Smatt * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
59707b9604Smatt * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
60707b9604Smatt * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
61707b9604Smatt * SUCH DAMAGE.
62707b9604Smatt */
63707b9604Smatt
64707b9604Smatt /*
65707b9604Smatt * Copyright (c) 1996 Ken C. Wellsch. All rights reserved.
66707b9604Smatt *
67707b9604Smatt * This code is derived from software contributed to Berkeley by
68707b9604Smatt * Ralph Campbell and Rick Macklem.
69707b9604Smatt *
70707b9604Smatt * Redistribution and use in source and binary forms, with or without
71707b9604Smatt * modification, are permitted provided that the following conditions
72707b9604Smatt * are met:
73707b9604Smatt * 1. Redistributions of source code must retain the above copyright
74707b9604Smatt * notice, this list of conditions and the following disclaimer.
75707b9604Smatt * 2. Redistributions in binary form must reproduce the above copyright
76707b9604Smatt * notice, this list of conditions and the following disclaimer in the
77707b9604Smatt * documentation and/or other materials provided with the distribution.
78707b9604Smatt * 3. All advertising materials mentioning features or use of this software
79707b9604Smatt * must display the following acknowledgement:
80707b9604Smatt * This product includes software developed by the University of
81707b9604Smatt * California, Berkeley and its contributors.
82707b9604Smatt * 4. Neither the name of the University nor the names of its contributors
83707b9604Smatt * may be used to endorse or promote products derived from this software
84707b9604Smatt * without specific prior written permission.
85707b9604Smatt *
86707b9604Smatt * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
87707b9604Smatt * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
88707b9604Smatt * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
89707b9604Smatt * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
90707b9604Smatt * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
91707b9604Smatt * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
92707b9604Smatt * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
93707b9604Smatt * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
94707b9604Smatt * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
95707b9604Smatt * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
96707b9604Smatt * SUCH DAMAGE.
97707b9604Smatt */
98707b9604Smatt
99707b9604Smatt #include <sys/cdefs.h>
100707b9604Smatt __KERNEL_RCSID(0, "$$");
101707b9604Smatt
102707b9604Smatt #include <sys/param.h>
103707b9604Smatt #include <sys/systm.h>
104707b9604Smatt #include <sys/callout.h>
105707b9604Smatt #include <sys/ioctl.h>
106707b9604Smatt #include <sys/tty.h>
107707b9604Smatt #include <sys/proc.h>
108707b9604Smatt #include <sys/buf.h>
109707b9604Smatt #include <sys/conf.h>
110707b9604Smatt #include <sys/file.h>
111707b9604Smatt #include <sys/uio.h>
112707b9604Smatt #include <sys/kernel.h>
113707b9604Smatt #include <sys/syslog.h>
114707b9604Smatt #include <sys/device.h>
115707b9604Smatt #include <sys/kauth.h>
116707b9604Smatt
117707b9604Smatt #include <sys/bus.h>
118707b9604Smatt #include <dev/qbus/ubavar.h>
119707b9604Smatt
120707b9604Smatt #include <vax/uba/qvareg.h>
121707b9604Smatt #include <vax/uba/qvavar.h>
122707b9604Smatt #include <vax/uba/qvkbdvar.h>
123707b9604Smatt
124707b9604Smatt #include <dev/cons.h>
125707b9604Smatt #include "qv.h"
126707b9604Smatt #include "qvkbd.h"
127707b9604Smatt #include "qvms.h"
128707b9604Smatt #include "qv_ic.h"
129707b9604Smatt
130707b9604Smatt #define QVAUX_DELAY(x) /* nothing */
131707b9604Smatt #define control inline
132707b9604Smatt
133707b9604Smatt static control uint
qvaux_read1(struct qvaux_softc * sc,u_int off)134707b9604Smatt qvaux_read1(struct qvaux_softc *sc, u_int off)
135707b9604Smatt {
136707b9604Smatt u_int rv;
137707b9604Smatt
138707b9604Smatt rv = bus_space_read_1(sc->sc_iot, sc->sc_ioh, off);
139707b9604Smatt QVAUX_DELAY(1);
140707b9604Smatt return rv;
141707b9604Smatt }
142707b9604Smatt
143707b9604Smatt static control u_int
qvaux_read2(struct qvaux_softc * sc,u_int off)144707b9604Smatt qvaux_read2(struct qvaux_softc *sc, u_int off)
145707b9604Smatt {
146707b9604Smatt u_int rv;
147707b9604Smatt
148707b9604Smatt rv = bus_space_read_2(sc->sc_iot, sc->sc_ioh, off);
149707b9604Smatt QVAUX_DELAY(1);
150707b9604Smatt return rv;
151707b9604Smatt }
152707b9604Smatt
153707b9604Smatt static control void
qvaux_write1(struct qvaux_softc * sc,u_int off,u_int val)154707b9604Smatt qvaux_write1(struct qvaux_softc *sc, u_int off, u_int val)
155707b9604Smatt {
156707b9604Smatt
157707b9604Smatt bus_space_write_1(sc->sc_iot, sc->sc_ioh, off, val);
158707b9604Smatt bus_space_barrier(sc->sc_iot, sc->sc_ioh, sc->sc_qr.qr_firstreg,
159707b9604Smatt sc->sc_qr.qr_winsize, BUS_SPACE_BARRIER_WRITE |
160707b9604Smatt BUS_SPACE_BARRIER_READ);
161707b9604Smatt QVAUX_DELAY(10);
162707b9604Smatt }
163707b9604Smatt
164707b9604Smatt static control void
qvaux_write2(struct qvaux_softc * sc,u_int off,u_int val)165707b9604Smatt qvaux_write2(struct qvaux_softc *sc, u_int off, u_int val)
166707b9604Smatt {
167707b9604Smatt
168707b9604Smatt bus_space_write_2(sc->sc_iot, sc->sc_ioh, off, val);
169707b9604Smatt bus_space_barrier(sc->sc_iot, sc->sc_ioh, sc->sc_qr.qr_firstreg,
170707b9604Smatt sc->sc_qr.qr_winsize, BUS_SPACE_BARRIER_WRITE |
171707b9604Smatt BUS_SPACE_BARRIER_READ);
172707b9604Smatt QVAUX_DELAY(10);
173707b9604Smatt }
174707b9604Smatt
175707b9604Smatt #include "ioconf.h"
176707b9604Smatt
177707b9604Smatt /* Flags used to monitor modem bits, make them understood outside driver */
178707b9604Smatt
179707b9604Smatt #define DML_DTR TIOCM_DTR
180707b9604Smatt #define DML_DCD TIOCM_CD
181707b9604Smatt #define DML_RI TIOCM_RI
182707b9604Smatt #define DML_BRK 0100000 /* no equivalent, we will mask */
183707b9604Smatt
184707b9604Smatt static const struct speedtab qvauxspeedtab[] =
185707b9604Smatt {
186707b9604Smatt { 0, 0 },
187707b9604Smatt { 75, CSR_B75 },
188707b9604Smatt { 110, CSR_B110 },
189707b9604Smatt { 134, CSR_B134 },
190707b9604Smatt { 150, CSR_B150 },
191707b9604Smatt { 300, CSR_B300 },
192707b9604Smatt { 600, CSR_B600 },
193707b9604Smatt { 1200, CSR_B1200 },
194707b9604Smatt { 2000, CSR_B2000 },
195707b9604Smatt { 2400, CSR_B2400 },
196707b9604Smatt { 4800, CSR_B4800 },
197707b9604Smatt { 7200, CSR_B7200 },
198707b9604Smatt { 9600, CSR_B9600 },
199707b9604Smatt { 19200, CSR_B19200 },
200707b9604Smatt { -1, -1 }
201707b9604Smatt };
202707b9604Smatt
203707b9604Smatt int qvaux_match(device_t, cfdata_t, void *);
204707b9604Smatt static void qvaux_attach(device_t , device_t , void *);
205707b9604Smatt static void qvauxstart(struct tty *);
206707b9604Smatt static int qvauxparam(struct tty *, struct termios *);
207707b9604Smatt static unsigned qvauxmctl(struct qvaux_softc *, int, int, int);
208707b9604Smatt //static void qvauxscan(void *);
209707b9604Smatt int qvauxgetc(struct qvaux_linestate *);
210707b9604Smatt void qvauxputc(struct qvaux_linestate *, int);
211707b9604Smatt
212707b9604Smatt static dev_type_open(qvauxopen);
213707b9604Smatt static dev_type_close(qvauxclose);
214707b9604Smatt static dev_type_read(qvauxread);
215707b9604Smatt static dev_type_write(qvauxwrite);
216707b9604Smatt static dev_type_ioctl(qvauxioctl);
217707b9604Smatt static dev_type_stop(qvauxstop);
218707b9604Smatt static dev_type_tty(qvauxtty);
219707b9604Smatt static dev_type_poll(qvauxpoll);
220707b9604Smatt
221707b9604Smatt const struct cdevsw qvaux_cdevsw = {
222707b9604Smatt qvauxopen, qvauxclose, qvauxread, qvauxwrite, qvauxioctl,
223707b9604Smatt qvauxstop, qvauxtty, qvauxpoll, nommap, ttykqfilter, nodiscard, D_TTY
224707b9604Smatt };
225707b9604Smatt
226707b9604Smatt int qvaux_timer; /* true if timer started */
227707b9604Smatt struct callout qvauxscan_ch;
228707b9604Smatt static struct cnm_state qvaux_cnm_state;
229707b9604Smatt
230707b9604Smatt CFATTACH_DECL_NEW(qvaux, sizeof(struct qvaux_softc),
231707b9604Smatt qvaux_match, qvaux_attach, NULL, NULL);
232707b9604Smatt
233707b9604Smatt #if NQVKBD > 0 || NQVMS > 0
234707b9604Smatt static int
qvaux_print(void * aux,const char * name)235707b9604Smatt qvaux_print(void *aux, const char *name)
236707b9604Smatt {
237707b9604Smatt struct qvauxkm_attach_args *daa = aux;
238707b9604Smatt if (name == NULL) {
239707b9604Smatt aprint_normal(" line %d", daa->daa_line);
240707b9604Smatt }
241707b9604Smatt
242707b9604Smatt return QUIET;
243707b9604Smatt }
244707b9604Smatt #endif
245707b9604Smatt
246707b9604Smatt int
qvaux_match(device_t parent,cfdata_t match,void * aux)247707b9604Smatt qvaux_match(device_t parent, cfdata_t match, void *aux)
248707b9604Smatt {
249707b9604Smatt /* always match since we are physically part of parent */
250707b9604Smatt return 1;
251707b9604Smatt }
252707b9604Smatt
253707b9604Smatt /*ARGSUSED*/
254707b9604Smatt static void
qvaux_attach(device_t parent,device_t self,void * aux)255707b9604Smatt qvaux_attach(device_t parent, device_t self, void *aux)
256707b9604Smatt {
257707b9604Smatt struct qvaux_softc *sc = device_private(self);
258707b9604Smatt struct uba_attach_args *ua = aux;
259707b9604Smatt #if NQVKBD > 0 || NQVMS > 0
260707b9604Smatt struct qvauxkm_attach_args daa;
261707b9604Smatt #endif
262707b9604Smatt
263707b9604Smatt /* set floating DUART vector and enable interrupts */
264707b9604Smatt qv_ic_setvec(ua, QVA_QVIC, QV_DUART_VEC, ua->ua_cvec);
265707b9604Smatt qv_ic_arm(ua, QVA_QVIC, QV_IC_ENA);
266707b9604Smatt bus_space_write_2(ua->ua_iot, ua->ua_ioh, QVA_QVCSR,
267707b9604Smatt bus_space_read_2(ua->ua_iot, ua->ua_ioh, QVA_QVCSR) | (1 << 6));
268707b9604Smatt
269707b9604Smatt sc->sc_dev = self;
270707b9604Smatt sc->sc_iot = ua->ua_iot;
271707b9604Smatt sc->sc_ioh = ua->ua_ioh;
272707b9604Smatt
273707b9604Smatt /* device register access structure */
274707b9604Smatt sc->sc_qr.qr_ipcr = DU_IPCR;
275707b9604Smatt sc->sc_qr.qr_acr = DU_ACR;
276707b9604Smatt sc->sc_qr.qr_isr = DU_ISR;
277707b9604Smatt sc->sc_qr. qr_imr = DU_IMR;
278707b9604Smatt sc->sc_qr.qr_ctur = DU_CTUR;
279707b9604Smatt sc->sc_qr.qr_ctlr = DU_CTLR;
280707b9604Smatt sc->sc_qr.qr_ip = DU_IP;
281707b9604Smatt sc->sc_qr.qr_opcr = DU_OPCR;
282707b9604Smatt sc->sc_qr.qr_cstrt = DU_IMR;
283707b9604Smatt sc->sc_qr.qr_opset = DU_OPSET;
284707b9604Smatt sc->sc_qr.qr_cstop = DU_CSTOP;
285707b9604Smatt sc->sc_qr.qr_opclr = DU_OPCLR;
286707b9604Smatt sc->sc_qr.qr_ch_regs[0].qr_mr = CH_MR(0);
287707b9604Smatt sc->sc_qr.qr_ch_regs[0].qr_sr = CH_SR(0);
288707b9604Smatt sc->sc_qr.qr_ch_regs[0].qr_csr = CH_CSR(0);
289707b9604Smatt sc->sc_qr.qr_ch_regs[0].qr_cr = CH_CR(0);
290707b9604Smatt sc->sc_qr.qr_ch_regs[0].qr_dat = CH_DAT(0);
291707b9604Smatt sc->sc_qr.qr_ch_regs[1].qr_mr = CH_MR(1);
292707b9604Smatt sc->sc_qr.qr_ch_regs[1].qr_sr = CH_SR(1);
293707b9604Smatt sc->sc_qr.qr_ch_regs[1].qr_csr = CH_CSR(1);
294707b9604Smatt sc->sc_qr.qr_ch_regs[1].qr_cr = CH_CR(1);
295707b9604Smatt sc->sc_qr.qr_ch_regs[1].qr_dat = CH_DAT(1);
296707b9604Smatt
297707b9604Smatt sc->sc_qr.qr_firstreg = QVA_FIRSTREG;
298707b9604Smatt sc->sc_qr.qr_winsize = QVA_WINSIZE;
299707b9604Smatt
300707b9604Smatt /* register DUART interrupt handler */
301707b9604Smatt uba_intr_establish(ua->ua_icookie, ua->ua_cvec,
302707b9604Smatt qvauxint, sc, &sc->sc_tintrcnt);
303707b9604Smatt qv_ic_enable(ua, QVA_QVIC, QV_DUART_VEC, QV_IC_ENA);
304707b9604Smatt
305707b9604Smatt qvauxattach(sc, ua->ua_evcnt, -1);
306707b9604Smatt
307707b9604Smatt #if NQVKBD > 0
308707b9604Smatt /* XXX set line parameters */
309707b9604Smatt qvaux_write2(sc, sc->sc_qr.qr_ch_regs[0].qr_csr,
310707b9604Smatt (CSR_B4800 << 4) | CSR_B4800);
311707b9604Smatt qvaux_write2(sc, sc->sc_qr.qr_ch_regs[0].qr_cr, CR_CMD_MR1 | CR_ENA_RX);
312707b9604Smatt qvaux_write2(sc, sc->sc_qr.qr_ch_regs[0].qr_mr, MR1_CS8 | MR1_PNONE);
313707b9604Smatt qvaux_write2(sc, sc->sc_qr.qr_ch_regs[0].qr_mr, MR2_STOP1);
314707b9604Smatt
315707b9604Smatt daa.daa_line = 0;
316707b9604Smatt daa.daa_flags = 0;
317beecddb6Sthorpej config_found(self, &daa, qvaux_print, CFARGS_NONE);
318707b9604Smatt #endif
319707b9604Smatt #if NQVMS > 0
320707b9604Smatt /* XXX set line parameters */
321707b9604Smatt qvaux_write2(sc, sc->sc_qr.qr_ch_regs[1].qr_csr,
322707b9604Smatt (CSR_B4800 << 4) | CSR_B4800);
323707b9604Smatt qvaux_write2(sc, sc->sc_qr.qr_ch_regs[1].qr_cr, CR_CMD_MR1 | CR_ENA_RX);
324707b9604Smatt qvaux_write2(sc, sc->sc_qr.qr_ch_regs[1].qr_mr, MR1_CS8 | MR1_PODD);
325707b9604Smatt qvaux_write2(sc, sc->sc_qr.qr_ch_regs[1].qr_mr, MR2_STOP1);
326707b9604Smatt
327707b9604Smatt daa.daa_line = 1;
328707b9604Smatt daa.daa_flags = 0;
329beecddb6Sthorpej config_found(self, &daa, qvaux_print, CFARGS_NONE);
330707b9604Smatt #endif
331707b9604Smatt
332707b9604Smatt }
333707b9604Smatt
334707b9604Smatt void
qvauxattach(struct qvaux_softc * sc,struct evcnt * parent_evcnt,int consline)335707b9604Smatt qvauxattach(struct qvaux_softc *sc, struct evcnt *parent_evcnt, int consline)
336707b9604Smatt {
337707b9604Smatt int n;
338707b9604Smatt dev_t dev;
339707b9604Smatt
340707b9604Smatt /* Initialize our softc structure. */
341707b9604Smatt for (n = 0; n < NQVAUXLINE; n++) {
342707b9604Smatt sc->sc_qvaux[n].qvaux_sc = sc;
343707b9604Smatt sc->sc_qvaux[n].qvaux_line = n;
344707b9604Smatt sc->sc_qvaux[n].qvaux_tty = tty_alloc();
345707b9604Smatt dev = sc->sc_qvaux[n].qvaux_tty->t_dev;
346707b9604Smatt sc->sc_qvaux[n].qvaux_tty->t_dev = makedev(major(dev),n);
347707b9604Smatt }
348707b9604Smatt
349707b9604Smatt evcnt_attach_dynamic(&sc->sc_rintrcnt, EVCNT_TYPE_INTR, parent_evcnt,
350707b9604Smatt device_xname(sc->sc_dev), "rintr");
351707b9604Smatt evcnt_attach_dynamic(&sc->sc_tintrcnt, EVCNT_TYPE_INTR, parent_evcnt,
352707b9604Smatt device_xname(sc->sc_dev), "tintr");
353707b9604Smatt
354707b9604Smatt /* Console magic keys */
355707b9604Smatt cn_init_magic(&qvaux_cnm_state);
356707b9604Smatt cn_set_magic("\047\001"); /* default magic is BREAK */
357707b9604Smatt /* VAX will change it in MD code */
358707b9604Smatt
359707b9604Smatt sc->sc_rxint = sc->sc_brk = 0;
360707b9604Smatt sc->sc_consline = consline;
361707b9604Smatt
362707b9604Smatt sc->sc_imr = INT_RXA | INT_RXB;
363707b9604Smatt qvaux_write2(sc, sc->sc_qr.qr_imr, sc->sc_imr);
364707b9604Smatt qvaux_write2(sc, sc->sc_qr.qr_ch_regs[0].qr_cr, CR_ENA_TX | CR_ENA_RX);
365707b9604Smatt qvaux_write2(sc, sc->sc_qr.qr_ch_regs[1].qr_cr, CR_ENA_TX | CR_ENA_RX);
366707b9604Smatt
367707b9604Smatt DELAY(10000);
368707b9604Smatt
369707b9604Smatt printf("\n");
370707b9604Smatt }
371707b9604Smatt
372707b9604Smatt /* DUART Interrupt entry */
373707b9604Smatt
374707b9604Smatt void
qvauxint(void * arg)375707b9604Smatt qvauxint(void *arg)
376707b9604Smatt {
377707b9604Smatt struct qvaux_softc *sc = arg;
378707b9604Smatt int isr;
379707b9604Smatt
380707b9604Smatt isr = qvaux_read2(sc, sc->sc_qr.qr_isr);
381707b9604Smatt
382707b9604Smatt if (isr & (INT_RXA | INT_RXB | INT_BRKA | INT_BRKB))
383707b9604Smatt qvauxrint(arg);
384707b9604Smatt
385707b9604Smatt isr = qvaux_read2(sc, sc->sc_qr.qr_isr);
386707b9604Smatt
387707b9604Smatt if (isr & (INT_TXA | INT_TXB) & sc->sc_imr)
388707b9604Smatt qvauxxint(arg);
389707b9604Smatt }
390707b9604Smatt
391707b9604Smatt /* Receiver Interrupt */
392707b9604Smatt
393707b9604Smatt void
qvauxrint(void * arg)394707b9604Smatt qvauxrint(void *arg)
395707b9604Smatt {
396707b9604Smatt struct qvaux_softc *sc = arg;
397707b9604Smatt struct tty *tp;
398707b9604Smatt int cc, mcc, line;
399707b9604Smatt unsigned stat[2];
400707b9604Smatt int overrun = 0;
401707b9604Smatt
402707b9604Smatt //printf(" qvauxrint ");
403707b9604Smatt
404707b9604Smatt sc->sc_rxint++;
405707b9604Smatt
406707b9604Smatt // determine source and loop until all are no longer active
407707b9604Smatt for (;;) {
408707b9604Smatt stat[0] = qvaux_read2(sc, sc->sc_qr.qr_ch_regs[0].qr_sr);
409707b9604Smatt stat[1] = qvaux_read2(sc, sc->sc_qr.qr_ch_regs[1].qr_sr);
410707b9604Smatt if ((stat[0] & SR_RX_RDY) == 0) {
411707b9604Smatt if ((stat[1] & SR_RX_RDY) == 0)
412707b9604Smatt break;
413707b9604Smatt else
414707b9604Smatt line = 1;
415707b9604Smatt }
416707b9604Smatt else
417707b9604Smatt line = 0;
418707b9604Smatt cc = qvaux_read2(sc, sc->sc_qr.qr_ch_regs[line].qr_dat) & 0xFF;
419707b9604Smatt tp = sc->sc_qvaux[line].qvaux_tty;
420707b9604Smatt
421707b9604Smatt /* Must be caught early */
422707b9604Smatt if (sc->sc_qvaux[line].qvaux_catch &&
423707b9604Smatt (*sc->sc_qvaux[line].qvaux_catch)(sc->sc_qvaux[line]
424707b9604Smatt .qvaux_private, cc)) {
425707b9604Smatt continue;
426707b9604Smatt }
427707b9604Smatt
428707b9604Smatt if (stat[line] & SR_BREAK) // do SR error bits need to be
429707b9604Smatt // cleared by an error reset?
430707b9604Smatt mcc = CNC_BREAK;
431707b9604Smatt else
432707b9604Smatt mcc = cc;
433707b9604Smatt
434707b9604Smatt cn_check_magic(tp->t_dev, mcc, qvaux_cnm_state);
435707b9604Smatt
436707b9604Smatt if (!(tp->t_state & TS_ISOPEN)) {
437707b9604Smatt cv_broadcast(&tp->t_rawcv);
438707b9604Smatt continue;
439707b9604Smatt }
440707b9604Smatt
441707b9604Smatt if ((stat[line] & SR_OVERRUN) && overrun == 0) { // ?
442707b9604Smatt log(LOG_WARNING, "%s: silo overflow, line %d\n",
443707b9604Smatt device_xname(sc->sc_dev), line);
444707b9604Smatt overrun = 1;
445707b9604Smatt }
446707b9604Smatt
447707b9604Smatt if (stat[line] & SR_FRAME) // ?
448707b9604Smatt cc |= TTY_FE;
449707b9604Smatt if (stat[line] & SR_PARITY) // ?
450707b9604Smatt cc |= TTY_PE;
451707b9604Smatt
452707b9604Smatt (*tp->t_linesw->l_rint)(cc, tp);
453707b9604Smatt }
454707b9604Smatt }
455707b9604Smatt
456707b9604Smatt /* Transmitter Interrupt */
457707b9604Smatt
458707b9604Smatt void
qvauxxint(void * arg)459707b9604Smatt qvauxxint(void *arg)
460707b9604Smatt {
461707b9604Smatt struct qvaux_softc *sc = arg;
462707b9604Smatt struct tty *tp;
463707b9604Smatt struct clist *cl;
464707b9604Smatt int line, ch, stat[2];
465707b9604Smatt
466707b9604Smatt for (;;) {
467707b9604Smatt stat[0] = qvaux_read2(sc, sc->sc_qr.qr_ch_regs[0].qr_sr);
468707b9604Smatt stat[1] = qvaux_read2(sc, sc->sc_qr.qr_ch_regs[1].qr_sr);
469707b9604Smatt if (((stat[0] & SR_TX_RDY) == 0)
470707b9604Smatt || ((sc->sc_imr & INT_TXA) == 0)) {
471707b9604Smatt if (((stat[1] & SR_TX_RDY) == 0)
472707b9604Smatt || ((sc->sc_imr & INT_TXB) == 0))
473707b9604Smatt break;
474707b9604Smatt else
475707b9604Smatt line = 1;
476707b9604Smatt }
477707b9604Smatt else
478707b9604Smatt line = 0;
479707b9604Smatt tp = sc->sc_qvaux[line].qvaux_tty;
480707b9604Smatt cl = &tp->t_outq;
481707b9604Smatt tp->t_state &= ~TS_BUSY;
482707b9604Smatt
483707b9604Smatt /* Just send out a char if we have one */
484707b9604Smatt /* As long as we can fill the chip buffer, we just loop here */
485707b9604Smatt // no fifo, just holding register
486707b9604Smatt if (cl->c_cc) {
487707b9604Smatt tp->t_state |= TS_BUSY;
488707b9604Smatt ch = getc(cl);
489707b9604Smatt qvaux_write1(sc, sc->sc_qr.qr_ch_regs[line].qr_dat, ch);
490707b9604Smatt continue;
491707b9604Smatt }
492707b9604Smatt /* Nothing to send, clear the tx flags */
493707b9604Smatt sc->sc_imr &= ~((line) ? (INT_TXB) : (INT_TXA));
494707b9604Smatt qvaux_write2(sc, sc->sc_qr.qr_imr, sc->sc_imr);
495707b9604Smatt
496707b9604Smatt if (sc->sc_qvaux[line].qvaux_catch)
497707b9604Smatt continue;
498707b9604Smatt
499707b9604Smatt if (tp->t_state & TS_FLUSH)
500707b9604Smatt tp->t_state &= ~TS_FLUSH;
501707b9604Smatt else
502707b9604Smatt ndflush (&tp->t_outq, cl->c_cc);
503707b9604Smatt
504707b9604Smatt (*tp->t_linesw->l_start)(tp);
505707b9604Smatt }
506707b9604Smatt }
507707b9604Smatt
508707b9604Smatt int
qvauxopen(dev_t dev,int flag,int mode,struct lwp * l)509707b9604Smatt qvauxopen(dev_t dev, int flag, int mode, struct lwp *l)
510707b9604Smatt {
511707b9604Smatt const int line = QVA_PORT(minor(dev));
512707b9604Smatt struct qvaux_softc *sc = device_lookup_private(&qvaux_cd,
513707b9604Smatt QVA_I2C(minor(dev))); // only one controller
514707b9604Smatt struct tty *tp;
515707b9604Smatt int error = 0;
516707b9604Smatt
517707b9604Smatt if (sc == NULL || line >= NQVAUXLINE)
518707b9604Smatt return ENXIO;
519707b9604Smatt
520707b9604Smatt /* if some other device is using the line, it's busy */
521707b9604Smatt if (sc->sc_qvaux[line].qvaux_catch)
522707b9604Smatt return EBUSY;
523707b9604Smatt
524707b9604Smatt tp = sc->sc_qvaux[line].qvaux_tty;
525707b9604Smatt if (tp == NULL)
526707b9604Smatt return (ENODEV);
527707b9604Smatt
528707b9604Smatt tp->t_oproc = qvauxstart;
529707b9604Smatt tp->t_param = qvauxparam;
530707b9604Smatt tp->t_dev = dev;
531707b9604Smatt
532707b9604Smatt if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp))
533707b9604Smatt return (EBUSY);
534707b9604Smatt
535707b9604Smatt if ((tp->t_state & TS_ISOPEN) == 0) {
536707b9604Smatt ttychars(tp);
537707b9604Smatt if (tp->t_ispeed == 0) {
538707b9604Smatt tp->t_iflag = TTYDEF_IFLAG;
539707b9604Smatt tp->t_oflag = TTYDEF_OFLAG;
540707b9604Smatt tp->t_cflag = TTYDEF_CFLAG;
541707b9604Smatt tp->t_lflag = TTYDEF_LFLAG;
542707b9604Smatt tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED;
543707b9604Smatt }
544707b9604Smatt (void) qvauxparam(tp, &tp->t_termios);
545707b9604Smatt ttsetwater(tp);
546707b9604Smatt }
547707b9604Smatt
548707b9604Smatt /* Use DMBIS and *not* DMSET or else we clobber incoming bits */
549707b9604Smatt if (qvauxmctl(sc, line, DML_DTR, DMBIS) & DML_DCD)
550707b9604Smatt tp->t_state |= TS_CARR_ON;
551*61158d87Sriastradh ttylock(tp);
552707b9604Smatt while (!(flag & O_NONBLOCK) && !(tp->t_cflag & CLOCAL) &&
553707b9604Smatt !(tp->t_state & TS_CARR_ON)) {
554707b9604Smatt tp->t_wopen++;
555707b9604Smatt error = ttysleep(tp, &tp->t_rawcv, true, 0);
556707b9604Smatt tp->t_wopen--;
557707b9604Smatt if (error)
558707b9604Smatt break;
559707b9604Smatt }
560*61158d87Sriastradh ttyunlock(tp);
561707b9604Smatt if (error)
562707b9604Smatt return (error);
563707b9604Smatt return ((*tp->t_linesw->l_open)(dev, tp));
564707b9604Smatt }
565707b9604Smatt
566707b9604Smatt /*ARGSUSED*/
567707b9604Smatt int
qvauxclose(dev_t dev,int flag,int mode,struct lwp * l)568707b9604Smatt qvauxclose(dev_t dev, int flag, int mode, struct lwp *l)
569707b9604Smatt {
570707b9604Smatt const int line = QVA_PORT(minor(dev));
571707b9604Smatt struct qvaux_softc *sc = device_lookup_private(&qvaux_cd,
572707b9604Smatt QVA_I2C(minor(dev))); // only one controller
573707b9604Smatt struct tty *tp = sc->sc_qvaux[line].qvaux_tty;
574707b9604Smatt
575707b9604Smatt (*tp->t_linesw->l_close)(tp, flag);
576707b9604Smatt
577707b9604Smatt /* Make sure a BREAK state is not left enabled. */
578707b9604Smatt (void) qvauxmctl(sc, line, DML_BRK, DMBIC);
579707b9604Smatt
580707b9604Smatt /* Do a hangup if so required. */
581707b9604Smatt if ((tp->t_cflag & HUPCL) || tp->t_wopen || !(tp->t_state & TS_ISOPEN))
582707b9604Smatt (void) qvauxmctl(sc, line, 0, DMSET);
583707b9604Smatt
584707b9604Smatt return ttyclose(tp);
585707b9604Smatt }
586707b9604Smatt
587707b9604Smatt int
qvauxread(dev_t dev,struct uio * uio,int flag)588707b9604Smatt qvauxread(dev_t dev, struct uio *uio, int flag)
589707b9604Smatt {
590707b9604Smatt struct qvaux_softc *sc = device_lookup_private(&qvaux_cd,
591707b9604Smatt QVA_I2C(minor(dev))); // only one controller
592707b9604Smatt struct tty *tp = sc->sc_qvaux[QVA_PORT(minor(dev))].qvaux_tty;
593707b9604Smatt
594707b9604Smatt return ((*tp->t_linesw->l_read)(tp, uio, flag));
595707b9604Smatt }
596707b9604Smatt
597707b9604Smatt int
qvauxwrite(dev_t dev,struct uio * uio,int flag)598707b9604Smatt qvauxwrite(dev_t dev, struct uio *uio, int flag)
599707b9604Smatt {
600707b9604Smatt struct qvaux_softc *sc = device_lookup_private(&qvaux_cd,
601707b9604Smatt QVA_I2C(minor(dev))); // only one controller
602707b9604Smatt struct tty *tp = sc->sc_qvaux[QVA_PORT(minor(dev))].qvaux_tty;
603707b9604Smatt
604707b9604Smatt return ((*tp->t_linesw->l_write)(tp, uio, flag));
605707b9604Smatt }
606707b9604Smatt
607707b9604Smatt int
qvauxpoll(dev_t dev,int events,struct lwp * l)608707b9604Smatt qvauxpoll(dev_t dev, int events, struct lwp *l)
609707b9604Smatt {
610707b9604Smatt struct qvaux_softc *sc = device_lookup_private(&qvaux_cd,
611707b9604Smatt QVA_I2C(minor(dev))); // only one controller
612707b9604Smatt struct tty *tp = sc->sc_qvaux[QVA_PORT(minor(dev))].qvaux_tty;
613707b9604Smatt
614707b9604Smatt return ((*tp->t_linesw->l_poll)(tp, events, l));
615707b9604Smatt }
616707b9604Smatt
617707b9604Smatt /*ARGSUSED*/
618707b9604Smatt int
qvauxioctl(dev_t dev,u_long cmd,void * data,int flag,struct lwp * l)619707b9604Smatt qvauxioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l)
620707b9604Smatt {
621707b9604Smatt struct qvaux_softc *sc = device_lookup_private(&qvaux_cd,
622707b9604Smatt QVA_I2C(minor(dev))); // only one controller
623707b9604Smatt const int line = QVA_PORT(minor(dev));
624707b9604Smatt struct tty *tp = sc->sc_qvaux[line].qvaux_tty;
625707b9604Smatt int error;
626707b9604Smatt
627707b9604Smatt error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l);
628707b9604Smatt if (error >= 0)
629707b9604Smatt return (error);
630707b9604Smatt
631707b9604Smatt error = ttioctl(tp, cmd, data, flag, l);
632707b9604Smatt if (error >= 0)
633707b9604Smatt return (error);
634707b9604Smatt
635707b9604Smatt switch (cmd) {
636707b9604Smatt case TIOCSBRK:
637707b9604Smatt (void) qvauxmctl(sc, line, DML_BRK, DMBIS);
638707b9604Smatt break;
639707b9604Smatt
640707b9604Smatt case TIOCCBRK:
641707b9604Smatt (void) qvauxmctl(sc, line, DML_BRK, DMBIC);
642707b9604Smatt break;
643707b9604Smatt
644707b9604Smatt case TIOCSDTR:
645707b9604Smatt (void) qvauxmctl(sc, line, DML_DTR, DMBIS);
646707b9604Smatt break;
647707b9604Smatt
648707b9604Smatt case TIOCCDTR:
649707b9604Smatt (void) qvauxmctl(sc, line, DML_DTR, DMBIC);
650707b9604Smatt break;
651707b9604Smatt
652707b9604Smatt case TIOCMSET:
653707b9604Smatt (void) qvauxmctl(sc, line, *(int *)data, DMSET);
654707b9604Smatt break;
655707b9604Smatt
656707b9604Smatt case TIOCMBIS:
657707b9604Smatt (void) qvauxmctl(sc, line, *(int *)data, DMBIS);
658707b9604Smatt break;
659707b9604Smatt
660707b9604Smatt case TIOCMBIC:
661707b9604Smatt (void) qvauxmctl(sc, line, *(int *)data, DMBIC);
662707b9604Smatt break;
663707b9604Smatt
664707b9604Smatt case TIOCMGET:
665707b9604Smatt *(int *)data = (qvauxmctl(sc, line, 0, DMGET) & ~DML_BRK);
666707b9604Smatt break;
667707b9604Smatt
668707b9604Smatt default:
669707b9604Smatt return (EPASSTHROUGH);
670707b9604Smatt }
671707b9604Smatt return (0);
672707b9604Smatt }
673707b9604Smatt
674707b9604Smatt struct tty *
qvauxtty(dev_t dev)675707b9604Smatt qvauxtty(dev_t dev)
676707b9604Smatt {
677707b9604Smatt struct qvaux_softc *sc = device_lookup_private(&qvaux_cd,
678707b9604Smatt QVA_I2C(minor(dev)));
679707b9604Smatt
680707b9604Smatt return sc->sc_qvaux[QVA_PORT(minor(dev))].qvaux_tty;
681707b9604Smatt }
682707b9604Smatt
683707b9604Smatt /*ARGSUSED*/
684707b9604Smatt void
qvauxstop(struct tty * tp,int flag)685707b9604Smatt qvauxstop(struct tty *tp, int flag)
686707b9604Smatt {
687707b9604Smatt if ((tp->t_state & (TS_BUSY | TS_TTSTOP)) == TS_BUSY)
688707b9604Smatt tp->t_state |= TS_FLUSH;
689707b9604Smatt }
690707b9604Smatt
691707b9604Smatt void
qvauxstart(struct tty * tp)692707b9604Smatt qvauxstart(struct tty *tp)
693707b9604Smatt {
694707b9604Smatt struct qvaux_softc *sc;
695707b9604Smatt int line;
696707b9604Smatt int s;
697707b9604Smatt
698707b9604Smatt s = spltty();
699707b9604Smatt if (tp->t_state & (TS_TIMEOUT|TS_BUSY|TS_TTSTOP)) {
700707b9604Smatt splx(s);
701707b9604Smatt return;
702707b9604Smatt }
703707b9604Smatt if (!ttypull(tp)) {
704707b9604Smatt splx(s);
705707b9604Smatt return;
706707b9604Smatt }
707707b9604Smatt
708707b9604Smatt line = QVA_PORT(minor(tp->t_dev));
709707b9604Smatt sc = device_lookup_private(&qvaux_cd, QVA_I2C(minor(tp->t_dev)));
710707b9604Smatt
711707b9604Smatt tp->t_state |= TS_BUSY;
712707b9604Smatt sc->sc_imr |= ((line) ? (INT_TXB) : (INT_TXA));
713707b9604Smatt qvaux_write2(sc, sc->sc_qr.qr_imr, sc->sc_imr);
714707b9604Smatt qvauxxint(sc);
715707b9604Smatt splx(s);
716707b9604Smatt }
717707b9604Smatt
718707b9604Smatt static int
qvauxparam(struct tty * tp,struct termios * t)719707b9604Smatt qvauxparam(struct tty *tp, struct termios *t)
720707b9604Smatt {
721707b9604Smatt struct qvaux_softc *sc = device_lookup_private(&qvaux_cd,
722707b9604Smatt QVA_I2C(minor(tp->t_dev)));
723707b9604Smatt const int line = QVA_PORT(minor(tp->t_dev));
724707b9604Smatt int cflag = t->c_cflag;
725707b9604Smatt int ispeed = ttspeedtab(t->c_ispeed, qvauxspeedtab);
726707b9604Smatt int ospeed = ttspeedtab(t->c_ospeed, qvauxspeedtab);
727707b9604Smatt unsigned mr1, mr2;
728707b9604Smatt int s;
729707b9604Smatt
730707b9604Smatt
731707b9604Smatt /* check requested parameters */
732707b9604Smatt if (ospeed < 0 || ispeed < 0)
733707b9604Smatt return (EINVAL);
734707b9604Smatt
735707b9604Smatt tp->t_ispeed = t->c_ispeed;
736707b9604Smatt tp->t_ospeed = t->c_ospeed;
737707b9604Smatt tp->t_cflag = cflag;
738707b9604Smatt
739707b9604Smatt if (ospeed == 0) {
740707b9604Smatt (void) qvauxmctl(sc, line, 0, DMSET); /* hang up line */
741707b9604Smatt return (0);
742707b9604Smatt }
743707b9604Smatt
744707b9604Smatt s = spltty();
745707b9604Smatt
746707b9604Smatt /* XXX This is wrong. Flush output or the chip gets very confused. */
747707b9604Smatt //ttywait(tp);
748707b9604Smatt
749707b9604Smatt //lpr = DZ_LPR_RX_ENABLE | ((ispeed&0xF)<<8) | line;
750707b9604Smatt
751707b9604Smatt qvaux_write2(sc, sc->sc_qr.qr_acr, ACR_BRG);
752707b9604Smatt qvaux_write2(sc, sc->sc_qr.qr_ch_regs[line].qr_csr,
753707b9604Smatt (ispeed << 4) | ospeed);
754707b9604Smatt
755707b9604Smatt mr1 = mr2 = 0;
756707b9604Smatt
757707b9604Smatt switch (cflag & CSIZE)
758707b9604Smatt {
759707b9604Smatt case CS5:
760707b9604Smatt mr1 |= MR1_CS5;
761707b9604Smatt break;
762707b9604Smatt case CS6:
763707b9604Smatt mr1 |= MR1_CS6;
764707b9604Smatt break;
765707b9604Smatt case CS7:
766707b9604Smatt mr1 |= MR1_CS7;
767707b9604Smatt break;
768707b9604Smatt default:
769707b9604Smatt mr1 |= MR1_CS8;
770707b9604Smatt break;
771707b9604Smatt }
772707b9604Smatt if (cflag & PARENB) {
773707b9604Smatt if (cflag & PARODD)
774707b9604Smatt mr1 |= MR1_PODD;
775707b9604Smatt else
776707b9604Smatt mr1 |= MR1_PEVEN;
777707b9604Smatt }
778707b9604Smatt else
779707b9604Smatt mr1 |= MR1_PNONE;
780707b9604Smatt if (cflag & CSTOPB)
781707b9604Smatt mr2 |= MR2_STOP2;
782707b9604Smatt else
783707b9604Smatt mr2 |= MR2_STOP1;
784707b9604Smatt
785707b9604Smatt qvaux_write2(sc, sc->sc_qr.qr_ch_regs[line].qr_cr,
786707b9604Smatt CR_CMD_MR1 | CR_ENA_RX); // reset to mr1
787707b9604Smatt qvaux_write2(sc, sc->sc_qr.qr_ch_regs[line].qr_mr, mr1);
788707b9604Smatt qvaux_write2(sc, sc->sc_qr.qr_ch_regs[line].qr_mr, mr2);
789707b9604Smatt qvaux_write2(sc, sc->sc_qr.qr_acr, ACR_BRG);
790707b9604Smatt (void) splx(s);
791707b9604Smatt DELAY(10000);
792707b9604Smatt
793707b9604Smatt return (0);
794707b9604Smatt }
795707b9604Smatt
796707b9604Smatt // QVSS has no modem control signals
797707b9604Smatt static unsigned
qvauxmctl(struct qvaux_softc * sc,int line,int bits,int how)798707b9604Smatt qvauxmctl(struct qvaux_softc *sc, int line, int bits, int how)
799707b9604Smatt {
800707b9604Smatt /* unsigned status; */
801707b9604Smatt unsigned mbits;
802707b9604Smatt unsigned bit;
803707b9604Smatt int s;
804707b9604Smatt
805707b9604Smatt s = spltty();
806707b9604Smatt mbits = 0;
807707b9604Smatt bit = (1 << line);
808707b9604Smatt #if 0
809707b9604Smatt
810707b9604Smatt /* external signals as seen from the port */
811707b9604Smatt status = qvaux_read1(sc, sc->sc_dr.dr_dcd) | sc->sc_dsr;
812707b9604Smatt if (status & bit)
813707b9604Smatt mbits |= DML_DCD;
814707b9604Smatt status = qvaux_read1(sc, sc->sc_dr.dr_ring);
815707b9604Smatt if (status & bit)
816707b9604Smatt mbits |= DML_RI;
817707b9604Smatt
818707b9604Smatt /* internal signals/state delivered to port */
819707b9604Smatt status = qvaux_read1(sc, sc->sc_dr.dr_dtr);
820707b9604Smatt if (status & bit)
821707b9604Smatt mbits |= DML_DTR;
822707b9604Smatt #endif
823707b9604Smatt if (sc->sc_brk & bit)
824707b9604Smatt mbits |= DML_BRK;
825707b9604Smatt
826707b9604Smatt switch (how)
827707b9604Smatt {
828707b9604Smatt case DMSET:
829707b9604Smatt mbits = bits;
830707b9604Smatt break;
831707b9604Smatt
832707b9604Smatt case DMBIS:
833707b9604Smatt mbits |= bits;
834707b9604Smatt break;
835707b9604Smatt
836707b9604Smatt case DMBIC:
837707b9604Smatt mbits &= ~bits;
838707b9604Smatt break;
839707b9604Smatt
840707b9604Smatt case DMGET:
841707b9604Smatt (void) splx(s);
842707b9604Smatt return (mbits);
843707b9604Smatt }
844707b9604Smatt #if 0
845707b9604Smatt if (mbits & DML_DTR) {
846707b9604Smatt qvaux_write1(sc, sc->sc_dr.dr_dtr,
847707b9604Smatt qvaux_read1(sc, sc->sc_dr.dr_dtr) | bit);
848707b9604Smatt } else {
849707b9604Smatt qvaux_write1(sc, sc->sc_dr.dr_dtr,
850707b9604Smatt qvaux_read1(sc, sc->sc_dr.dr_dtr) & ~bit);
851707b9604Smatt }
852707b9604Smatt #endif
853707b9604Smatt if (mbits & DML_BRK) {
854707b9604Smatt sc->sc_brk |= bit;
855707b9604Smatt qvaux_write1(sc, sc->sc_qr.qr_ch_regs[line].qr_cr,
856707b9604Smatt CR_CMD_START_BRK);
857707b9604Smatt } else {
858707b9604Smatt sc->sc_brk &= ~bit;
859707b9604Smatt qvaux_write1(sc, sc->sc_qr.qr_ch_regs[line].qr_cr,
860707b9604Smatt CR_CMD_STOP_BRK);
861707b9604Smatt }
862707b9604Smatt
863707b9604Smatt (void) splx(s);
864707b9604Smatt
865707b9604Smatt return (mbits);
866707b9604Smatt }
867707b9604Smatt
868707b9604Smatt /*
869707b9604Smatt * Called after an ubareset. The QVSS card is reset, but the only thing
870707b9604Smatt * that must be done is to start the receiver and transmitter again.
871707b9604Smatt * No DMA setup to care about.
872707b9604Smatt */
873707b9604Smatt void
qvauxreset(device_t dev)874707b9604Smatt qvauxreset(device_t dev)
875707b9604Smatt {
876707b9604Smatt struct qvaux_softc *sc = device_private(dev);
877707b9604Smatt struct tty *tp;
878707b9604Smatt int i;
879707b9604Smatt
880707b9604Smatt for (i = 0; i < NQVAUXLINE; i++) {
881707b9604Smatt tp = sc->sc_qvaux[i].qvaux_tty;
882707b9604Smatt
883707b9604Smatt if (((tp->t_state & TS_ISOPEN) == 0) || (tp->t_wopen == 0))
884707b9604Smatt continue;
885707b9604Smatt
886707b9604Smatt qvauxparam(tp, &tp->t_termios);
887707b9604Smatt qvauxmctl(sc, i, DML_DTR, DMSET);
888707b9604Smatt tp->t_state &= ~TS_BUSY;
889707b9604Smatt qvauxstart(tp); /* Kick off transmitter again */
890707b9604Smatt }
891707b9604Smatt }
892707b9604Smatt
893707b9604Smatt #if NQVKBD > 0 || NQVMS > 0
894707b9604Smatt int
qvauxgetc(struct qvaux_linestate * ls)895707b9604Smatt qvauxgetc(struct qvaux_linestate *ls)
896707b9604Smatt {
897707b9604Smatt #if 0
898707b9604Smatt int line = ls->qvaux_line;
899707b9604Smatt int s;
900707b9604Smatt u_short rbuf;
901707b9604Smatt
902707b9604Smatt s = spltty();
903707b9604Smatt for (;;) {
904707b9604Smatt for(; (dz->csr & DZ_CSR_RX_DONE) == 0;);
905707b9604Smatt rbuf = dz->rbuf;
906707b9604Smatt if (((rbuf >> 8) & 3) == line) {
907707b9604Smatt splx(s);
908707b9604Smatt return (rbuf & 0xff);
909707b9604Smatt }
910707b9604Smatt }
911707b9604Smatt #endif
912707b9604Smatt return 0;
913707b9604Smatt }
914707b9604Smatt
915707b9604Smatt void
qvauxputc(struct qvaux_linestate * ls,int ch)916707b9604Smatt qvauxputc(struct qvaux_linestate *ls, int ch)
917707b9604Smatt {
918707b9604Smatt //int line;
919707b9604Smatt int s;
920707b9604Smatt
921707b9604Smatt /* if the qvaux has already been attached, the MI
922707b9604Smatt driver will do the transmitting: */
923707b9604Smatt if (ls && ls->qvaux_sc) {
924707b9604Smatt s = spltty();
925707b9604Smatt // line = ls->qvaux_line;
926707b9604Smatt putc(ch, &ls->qvaux_tty->t_outq);
927707b9604Smatt qvauxstart(ls->qvaux_tty);
928707b9604Smatt splx(s);
929707b9604Smatt return;
930707b9604Smatt }
931707b9604Smatt
932707b9604Smatt /* use qvauxcnputc to do the transmitting: */
933707b9604Smatt //qvauxcnputc(makedev(cdevsw_lookup_major(&qvaux_cdevsw), 0), ch);
934707b9604Smatt }
935707b9604Smatt #endif /* NQVKBD > 0 || NQVMS > 0 */
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