1 /* 2 * Copyright (c) 1999 Ludd, University of Lule}, Sweden. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed at Ludd, University of 16 * Lule}, Sweden and its contributors. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/param.h> 33 #include <sys/device.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 37 #include <machine/clock.h> 38 #include <machine/cpu.h> 39 #include <machine/scb.h> 40 41 #define KA49_CPMBX 0x38 42 #define KA49_HLT_HALT 0xcf 43 #define KA49_HLT_BOOT 0x8b 44 45 static void ka49_conf(void); 46 static void ka49_memerr(void); 47 static int ka49_mchk(caddr_t); 48 static void ka49_halt(void); 49 static void ka49_reboot(int); 50 static void ka49_softmem(void *); 51 static void ka49_hardmem(void *); 52 static void ka49_steal_pages(void); 53 static void ka49_cache_enable(void); 54 static void ka49_halt(void); 55 56 /* 57 * Declaration of 49-specific calls. 58 */ 59 struct cpu_dep ka49_calls = { 60 ka49_steal_pages, 61 ka49_mchk, 62 ka49_memerr, 63 ka49_conf, 64 chip_clkread, 65 chip_clkwrite, 66 32, /* ~VUPS */ 67 2, /* SCB pages */ 68 ka49_halt, 69 ka49_reboot, 70 NULL, 71 NULL, 72 CPU_RAISEIPL, 73 }; 74 75 76 void 77 ka49_conf() 78 { 79 printf("cpu0: KA49\n"); 80 81 /* Why??? */ 82 { volatile int *hej = (void *)mfpr(PR_ISP); *hej = *hej; hej[-1] = hej[-1];} 83 84 /* 85 * Setup parameters necessary to read time from clock chip. 86 */ 87 clk_adrshift = 1; /* Addressed at long's... */ 88 clk_tweak = 2; /* ...and shift two */ 89 clk_page = (short *)vax_map_physmem(0x25400000, 1); 90 } 91 92 /* 93 * Why may we get memory errors during startup??? 94 */ 95 void 96 ka49_hardmem(void *arg) 97 { 98 if (cold == 0) 99 printf("Hard memory error\n"); 100 splhigh(); 101 } 102 103 void 104 ka49_softmem(void *arg) 105 { 106 if (cold == 0) 107 printf("Soft memory error\n"); 108 splhigh(); 109 } 110 111 /* 112 * KA49-specific IPRs. KA49 has the funny habit to control all caches 113 * via IPRs. 114 */ 115 #define PR_CCTL 0xa0 116 #define CCTL_ENABLE 0x00000001 117 #define CCTL_SSIZE 0x00000002 118 #define CCTL_VSIZE 0x00000004 119 #define CCTL_SW_ETM 0x40000000 120 #define CCTL_HW_ETM 0x80000000 121 122 #define PR_BCETSTS 0xa3 123 #define PR_BCEDSTS 0xa6 124 #define PR_NESTS 0xae 125 126 #define PR_VMAR 0xd0 127 #define PR_VTAG 0xd1 128 #define PR_ICSR 0xd3 129 #define ICSR_ENABLE 0x01 130 131 #define PR_PCCTL 0xf8 132 #define PCCTL_P_EN 0x10 133 #define PCCTL_I_EN 0x02 134 #define PCCTL_D_EN 0x01 135 136 void 137 ka49_cache_enable() 138 { 139 int start, slut; 140 141 /* 142 * Turn caches off. 143 */ 144 mtpr(0, PR_ICSR); 145 mtpr(0, PR_PCCTL); 146 mtpr(mfpr(PR_CCTL) | CCTL_SW_ETM, PR_CCTL); 147 148 /* 149 * Invalidate caches. 150 */ 151 mtpr(mfpr(PR_CCTL) | 0x10, PR_CCTL); /* Set cache size */ 152 mtpr(mfpr(PR_BCETSTS), PR_BCETSTS); /* Clear error bits */ 153 mtpr(mfpr(PR_BCEDSTS), PR_BCEDSTS); /* Clear error bits */ 154 mtpr(mfpr(PR_NESTS), PR_NESTS); /* Clear error bits */ 155 156 157 start = 0x01400000; 158 slut = 0x01440000; 159 160 /* Flush cache lines */ 161 for (; start < slut; start += 0x20) 162 mtpr(0, start); 163 164 mtpr((mfpr(PR_CCTL) & ~(CCTL_SW_ETM|CCTL_ENABLE)) | CCTL_HW_ETM, 165 PR_CCTL); 166 167 start = 0x01000000; 168 slut = 0x01040000; 169 170 /* clear tag and valid */ 171 for (; start < slut; start += 0x20) 172 mtpr(0, start); 173 174 mtpr(mfpr(PR_CCTL) | 0x10 | CCTL_ENABLE, PR_CCTL); /* enab. bcache */ 175 176 start = 0x01800000; 177 slut = 0x01802000; 178 179 /* Clear primary cache */ 180 for (; start < slut; start += 0x20) 181 mtpr(0, start); 182 183 /* Flush the pipes (via REI) */ 184 asm("movpsl -(%sp); movab 1f,-(%sp); rei; 1:;"); 185 186 /* Enable primary cache */ 187 mtpr(PCCTL_P_EN|PCCTL_I_EN|PCCTL_D_EN, PR_PCCTL); 188 189 /* Enable the VIC */ 190 start = 0; 191 slut = 0x800; 192 for (; start < slut; start += 0x20) { 193 mtpr(start, PR_VMAR); 194 mtpr(0, PR_VTAG); 195 } 196 mtpr(ICSR_ENABLE, PR_ICSR); 197 } 198 199 void 200 ka49_memerr() 201 { 202 printf("Memory err!\n"); 203 } 204 205 int 206 ka49_mchk(caddr_t addr) 207 { 208 panic("Machine check"); 209 return 0; 210 } 211 212 void 213 ka49_steal_pages() 214 { 215 /* 216 * Get the soft and hard memory error vectors now. 217 */ 218 scb_vecalloc(0x54, ka49_softmem, NULL, 0, NULL); 219 scb_vecalloc(0x60, ka49_hardmem, NULL, 0, NULL); 220 221 /* Turn on caches (to speed up execution a bit) */ 222 ka49_cache_enable(); 223 224 } 225 226 static void 227 ka49_halt() 228 { 229 ((u_int8_t *) clk_page)[KA49_CPMBX] = KA49_HLT_HALT; 230 asm("halt"); 231 } 232 233 static void 234 ka49_reboot(int arg) 235 { 236 ((u_int8_t *) clk_page)[KA49_CPMBX] = KA49_HLT_BOOT; 237 asm("halt"); 238 } 239