1 /* $NetBSD: cpu.h,v 1.26 2010/12/22 04:15:01 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 1990 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * William Jolitz. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * @(#)cpu.h 5.4 (Berkeley) 5/9/91 35 */ 36 37 #ifndef _X86_CPU_H_ 38 #define _X86_CPU_H_ 39 40 #if defined(_KERNEL) || defined(_KMEMUSER) 41 #if defined(_KERNEL_OPT) 42 #include "opt_xen.h" 43 #ifdef i386 44 #include "opt_user_ldt.h" 45 #include "opt_vm86.h" 46 #endif 47 #endif 48 49 /* 50 * Definitions unique to x86 cpu support. 51 */ 52 #include <machine/frame.h> 53 #include <machine/pte.h> 54 #include <machine/segments.h> 55 #include <machine/tss.h> 56 #include <machine/intrdefs.h> 57 58 #include <x86/cacheinfo.h> 59 #include <x86/via_padlock.h> 60 61 #include <sys/cpu_data.h> 62 #include <sys/evcnt.h> 63 #include <sys/device_if.h> /* for device_t */ 64 65 struct intrsource; 66 struct pmap; 67 struct device; 68 69 #ifdef __x86_64__ 70 #define i386tss x86_64_tss 71 #endif 72 73 #define NIOPORTS 1024 /* # of ports we allow to be mapped */ 74 #define IOMAPSIZE (NIOPORTS / 8) /* I/O bitmap size in bytes */ 75 76 /* 77 * a bunch of this belongs in cpuvar.h; move it later.. 78 */ 79 80 struct cpu_info { 81 struct cpu_data ci_data; /* MI per-cpu data */ 82 device_t ci_dev; /* pointer to our device */ 83 struct cpu_info *ci_self; /* self-pointer */ 84 volatile struct vcpu_info *ci_vcpu; /* for XEN */ 85 void *ci_tlog_base; /* Trap log base */ 86 int32_t ci_tlog_offset; /* Trap log current offset */ 87 88 /* 89 * Will be accessed by other CPUs. 90 */ 91 struct cpu_info *ci_next; /* next cpu */ 92 struct lwp *ci_curlwp; /* current owner of the processor */ 93 struct pmap_cpu *ci_pmap_cpu; /* per-CPU pmap data */ 94 struct lwp *ci_fpcurlwp; /* current owner of the FPU */ 95 int ci_fpsaving; /* save in progress */ 96 int ci_fpused; /* XEN: FPU was used by curlwp */ 97 cpuid_t ci_cpuid; /* our CPU ID */ 98 int ci_cpumask; /* (1 << CPU ID) */ 99 uint32_t ci_acpiid; /* our ACPI/MADT ID */ 100 uint32_t ci_initapicid; /* our intitial APIC ID */ 101 102 /* 103 * Private members. 104 */ 105 struct evcnt ci_tlb_evcnt; /* tlb shootdown counter */ 106 struct pmap *ci_pmap; /* current pmap */ 107 int ci_need_tlbwait; /* need to wait for TLB invalidations */ 108 int ci_want_pmapload; /* pmap_load() is needed */ 109 volatile int ci_tlbstate; /* one of TLBSTATE_ states. see below */ 110 #define TLBSTATE_VALID 0 /* all user tlbs are valid */ 111 #define TLBSTATE_LAZY 1 /* tlbs are valid but won't be kept uptodate */ 112 #define TLBSTATE_STALE 2 /* we might have stale user tlbs */ 113 int ci_curldt; /* current LDT descriptor */ 114 int ci_nintrhand; /* number of H/W interrupt handlers */ 115 uint64_t ci_scratch; 116 117 #ifdef XEN 118 struct iplsource *ci_isources[NIPL]; 119 #else 120 struct intrsource *ci_isources[MAX_INTR_SOURCES]; 121 #endif 122 volatile int ci_mtx_count; /* Negative count of spin mutexes */ 123 volatile int ci_mtx_oldspl; /* Old SPL at this ci_idepth */ 124 125 /* The following must be aligned for cmpxchg8b. */ 126 struct { 127 uint32_t ipending; 128 int ilevel; 129 } ci_istate __aligned(8); 130 #define ci_ipending ci_istate.ipending 131 #define ci_ilevel ci_istate.ilevel 132 133 int ci_idepth; 134 void * ci_intrstack; 135 uint32_t ci_imask[NIPL]; 136 uint32_t ci_iunmask[NIPL]; 137 138 uint32_t ci_flags; /* flags; see below */ 139 uint32_t ci_ipis; /* interprocessor interrupts pending */ 140 uint32_t sc_apic_version; /* local APIC version */ 141 142 uint32_t ci_signature; /* X86 cpuid type */ 143 uint32_t ci_vendor[4]; /* vendor string */ 144 uint32_t ci_cpu_serial[3]; /* PIII serial number */ 145 volatile uint32_t ci_lapic_counter; 146 147 uint32_t ci_feat_val[5]; /* X86 CPUID feature bits 148 * [0] basic features %edx 149 * [1] basic features %ecx 150 * [2] extended features %edx 151 * [3] extended features %ecx 152 * [4] VIA padlock features 153 */ 154 155 const struct cpu_functions *ci_func; /* start/stop functions */ 156 struct trapframe *ci_ddb_regs; 157 158 u_int ci_cflush_lsize; /* CFLUSH insn line size */ 159 struct x86_cache_info ci_cinfo[CAI_COUNT]; 160 161 union descriptor *ci_gdt; 162 163 #ifdef i386 164 struct i386tss ci_doubleflt_tss; 165 struct i386tss ci_ddbipi_tss; 166 #endif 167 168 #ifdef PAE 169 uint32_t ci_pae_l3_pdirpa; /* PA of L3 PD */ 170 pd_entry_t * ci_pae_l3_pdir; /* VA pointer to L3 PD */ 171 #endif 172 173 #if defined(XEN) && defined(__x86_64__) 174 /* Currently active user PGD (can't use rcr3() with Xen) */ 175 paddr_t ci_xen_current_user_pgd; 176 #endif 177 178 char *ci_doubleflt_stack; 179 char *ci_ddbipi_stack; 180 181 struct evcnt ci_ipi_events[X86_NIPI]; 182 183 struct via_padlock ci_vp; /* VIA PadLock private storage */ 184 185 struct i386tss ci_tss; /* Per-cpu TSS; shared among LWPs */ 186 char ci_iomap[IOMAPSIZE]; /* I/O Bitmap */ 187 int ci_tss_sel; /* TSS selector of this cpu */ 188 189 /* 190 * The following two are actually region_descriptors, 191 * but that would pollute the namespace. 192 */ 193 uintptr_t ci_suspend_gdt; 194 uint16_t ci_suspend_gdt_padding; 195 uintptr_t ci_suspend_idt; 196 uint16_t ci_suspend_idt_padding; 197 198 uint16_t ci_suspend_tr; 199 uint16_t ci_suspend_ldt; 200 uintptr_t ci_suspend_fs; 201 uintptr_t ci_suspend_gs; 202 uintptr_t ci_suspend_kgs; 203 uintptr_t ci_suspend_efer; 204 uintptr_t ci_suspend_reg[12]; 205 uintptr_t ci_suspend_cr0; 206 uintptr_t ci_suspend_cr2; 207 uintptr_t ci_suspend_cr3; 208 uintptr_t ci_suspend_cr4; 209 uintptr_t ci_suspend_cr8; 210 211 /* The following must be in a single cache line. */ 212 int ci_want_resched __aligned(64); 213 int ci_padout __aligned(64); 214 }; 215 216 /* 217 * Macros to handle (some) trapframe registers for common x86 code. 218 */ 219 #ifdef __x86_64__ 220 #define X86_TF_RAX(tf) tf->tf_rax 221 #define X86_TF_RDX(tf) tf->tf_rdx 222 #define X86_TF_RSP(tf) tf->tf_rsp 223 #define X86_TF_RIP(tf) tf->tf_rip 224 #define X86_TF_RFLAGS(tf) tf->tf_rflags 225 #else 226 #define X86_TF_RAX(tf) tf->tf_eax 227 #define X86_TF_RDX(tf) tf->tf_edx 228 #define X86_TF_RSP(tf) tf->tf_esp 229 #define X86_TF_RIP(tf) tf->tf_eip 230 #define X86_TF_RFLAGS(tf) tf->tf_eflags 231 #endif 232 233 /* 234 * Processor flag notes: The "primary" CPU has certain MI-defined 235 * roles (mostly relating to hardclock handling); we distinguish 236 * betwen the processor which booted us, and the processor currently 237 * holding the "primary" role just to give us the flexibility later to 238 * change primaries should we be sufficiently twisted. 239 */ 240 241 #define CPUF_BSP 0x0001 /* CPU is the original BSP */ 242 #define CPUF_AP 0x0002 /* CPU is an AP */ 243 #define CPUF_SP 0x0004 /* CPU is only processor */ 244 #define CPUF_PRIMARY 0x0008 /* CPU is active primary processor */ 245 246 #define CPUF_SYNCTSC 0x0800 /* Synchronize TSC */ 247 #define CPUF_PRESENT 0x1000 /* CPU is present */ 248 #define CPUF_RUNNING 0x2000 /* CPU is running */ 249 #define CPUF_PAUSE 0x4000 /* CPU is paused in DDB */ 250 #define CPUF_GO 0x8000 /* CPU should start running */ 251 252 /* 253 * We statically allocate the CPU info for the primary CPU (or, 254 * the only CPU on uniprocessors), and the primary CPU is the 255 * first CPU on the CPU info list. 256 */ 257 extern struct cpu_info cpu_info_primary; 258 extern struct cpu_info *cpu_info_list; 259 260 #define CPU_INFO_ITERATOR int 261 #define CPU_INFO_FOREACH(cii, ci) cii = 0, ci = cpu_info_list; \ 262 ci != NULL; ci = ci->ci_next 263 264 #define CPU_STARTUP(_ci, _target) ((_ci)->ci_func->start(_ci, _target)) 265 #define CPU_STOP(_ci) ((_ci)->ci_func->stop(_ci)) 266 #define CPU_START_CLEANUP(_ci) ((_ci)->ci_func->cleanup(_ci)) 267 268 #if !defined(__GNUC__) || defined(_MODULE) 269 /* For non-GCC and modules */ 270 struct cpu_info *x86_curcpu(void); 271 void cpu_set_curpri(int); 272 # ifdef __GNUC__ 273 lwp_t *x86_curlwp(void) __attribute__ ((const)); 274 # else 275 lwp_t *x86_curlwp(void); 276 # endif 277 #endif 278 279 #define cpu_number() (cpu_index(curcpu())) 280 281 #define CPU_IS_PRIMARY(ci) ((ci)->ci_flags & CPUF_PRIMARY) 282 283 #define X86_AST_GENERIC 0x01 284 #define X86_AST_PREEMPT 0x02 285 286 #define aston(l, why) ((l)->l_md.md_astpending |= (why)) 287 #define cpu_did_resched(l) ((l)->l_md.md_astpending &= ~X86_AST_PREEMPT) 288 289 void cpu_boot_secondary_processors(void); 290 void cpu_init_idle_lwps(void); 291 void cpu_init_msrs(struct cpu_info *, bool); 292 void cpu_load_pmap(struct pmap *); 293 294 extern uint32_t cpus_attached; 295 #ifndef XEN 296 #define curcpu() x86_curcpu() 297 #define curlwp x86_curlwp() 298 #else 299 /* XXX initgdt() calls pmap_kenter_pa() which calls splvm() before %fs is set */ 300 #define curcpu() (&cpu_info_primary) 301 #define curlwp curcpu()->ci_curlwp 302 #endif 303 #define curpcb ((struct pcb *)lwp_getpcb(curlwp)) 304 305 /* 306 * Arguments to hardclock, softclock and statclock 307 * encapsulate the previous machine state in an opaque 308 * clockframe; for now, use generic intrframe. 309 */ 310 struct clockframe { 311 struct intrframe cf_if; 312 }; 313 314 /* 315 * Give a profiling tick to the current process when the user profiling 316 * buffer pages are invalid. On the i386, request an ast to send us 317 * through trap(), marking the proc as needing a profiling tick. 318 */ 319 extern void cpu_need_proftick(struct lwp *l); 320 321 /* 322 * Notify the LWP l that it has a signal pending, process as soon as 323 * possible. 324 */ 325 extern void cpu_signotify(struct lwp *); 326 327 /* 328 * We need a machine-independent name for this. 329 */ 330 extern void (*delay_func)(unsigned int); 331 struct timeval; 332 333 #define DELAY(x) (*delay_func)(x) 334 #define delay(x) (*delay_func)(x) 335 336 extern int biosbasemem; 337 extern int biosextmem; 338 extern int cpu; 339 extern int cpuid_level; 340 extern int cpu_class; 341 extern char cpu_brand_string[]; 342 343 extern int i386_use_fxsave; 344 extern int i386_use_pae; 345 extern int i386_has_sse; 346 extern int i386_has_sse2; 347 348 extern void (*x86_cpu_idle)(void); 349 #define cpu_idle() (*x86_cpu_idle)() 350 351 /* machdep.c */ 352 void dumpconf(void); 353 void cpu_reset(void); 354 void i386_proc0_tss_ldt_init(void); 355 void dumpconf(void); 356 void cpu_reset(void); 357 void x86_64_proc0_tss_ldt_init(void); 358 void x86_64_init_pcb_tss_ldt(struct cpu_info *); 359 360 /* longrun.c */ 361 u_int tmx86_get_longrun_mode(void); 362 void tmx86_get_longrun_status(u_int *, u_int *, u_int *); 363 void tmx86_init_longrun(void); 364 365 /* identcpu.c */ 366 void cpu_probe(struct cpu_info *); 367 void cpu_identify(struct cpu_info *); 368 369 /* cpu_topology.c */ 370 void x86_cpu_topology(struct cpu_info *); 371 372 /* vm_machdep.c */ 373 void cpu_proc_fork(struct proc *, struct proc *); 374 375 /* locore.s */ 376 struct region_descriptor; 377 void lgdt(struct region_descriptor *); 378 #ifdef XEN 379 void lgdt_finish(void); 380 void i386_switch_context(lwp_t *); 381 #endif 382 383 struct pcb; 384 void savectx(struct pcb *); 385 void lwp_trampoline(void); 386 void child_trampoline(void); 387 #ifdef XEN 388 void startrtclock(void); 389 void xen_delay(unsigned int); 390 void xen_initclocks(void); 391 #else 392 /* clock.c */ 393 void initrtclock(u_long); 394 void startrtclock(void); 395 void i8254_delay(unsigned int); 396 void i8254_microtime(struct timeval *); 397 void i8254_initclocks(void); 398 #endif 399 400 /* cpu.c */ 401 402 void cpu_probe_features(struct cpu_info *); 403 404 /* npx.c */ 405 void npxsave_lwp(struct lwp *, bool); 406 void npxsave_cpu(bool); 407 408 /* vm_machdep.c */ 409 paddr_t kvtop(void *); 410 411 #ifdef USER_LDT 412 /* sys_machdep.h */ 413 int x86_get_ldt(struct lwp *, void *, register_t *); 414 int x86_set_ldt(struct lwp *, void *, register_t *); 415 #endif 416 417 /* isa_machdep.c */ 418 void isa_defaultirq(void); 419 int isa_nmi(void); 420 421 #ifdef VM86 422 /* vm86.c */ 423 void vm86_gpfault(struct lwp *, int); 424 #endif /* VM86 */ 425 426 /* consinit.c */ 427 void kgdb_port_init(void); 428 429 /* bus_machdep.c */ 430 void x86_bus_space_init(void); 431 void x86_bus_space_mallocok(void); 432 433 #include <machine/psl.h> /* Must be after struct cpu_info declaration */ 434 435 #endif /* _KERNEL || __KMEMUSER */ 436 437 #if defined(_KERNEL) || defined(_STANDALONE) 438 #include <sys/types.h> 439 #else 440 #include <stdbool.h> 441 #endif /* _KERNEL || _STANDALONE */ 442 443 /* 444 * CTL_MACHDEP definitions. 445 */ 446 #define CPU_CONSDEV 1 /* dev_t: console terminal device */ 447 #define CPU_BIOSBASEMEM 2 /* int: bios-reported base mem (K) */ 448 #define CPU_BIOSEXTMEM 3 /* int: bios-reported ext. mem (K) */ 449 /* CPU_NKPDE 4 obsolete: int: number of kernel PDEs */ 450 #define CPU_BOOTED_KERNEL 5 /* string: booted kernel name */ 451 #define CPU_DISKINFO 6 /* struct disklist *: 452 * disk geometry information */ 453 #define CPU_FPU_PRESENT 7 /* int: FPU is present */ 454 #define CPU_OSFXSR 8 /* int: OS uses FXSAVE/FXRSTOR */ 455 #define CPU_SSE 9 /* int: OS/CPU supports SSE */ 456 #define CPU_SSE2 10 /* int: OS/CPU supports SSE2 */ 457 #define CPU_TMLR_MODE 11 /* int: longrun mode 458 * 0: minimum frequency 459 * 1: economy 460 * 2: performance 461 * 3: maximum frequency 462 */ 463 #define CPU_TMLR_FREQUENCY 12 /* int: current frequency */ 464 #define CPU_TMLR_VOLTAGE 13 /* int: curret voltage */ 465 #define CPU_TMLR_PERCENTAGE 14 /* int: current clock percentage */ 466 #define CPU_MAXID 15 /* number of valid machdep ids */ 467 468 /* 469 * Structure for CPU_DISKINFO sysctl call. 470 * XXX this should be somewhere else. 471 */ 472 #define MAX_BIOSDISKS 16 473 474 struct disklist { 475 int dl_nbiosdisks; /* number of bios disks */ 476 struct biosdisk_info { 477 int bi_dev; /* BIOS device # (0x80 ..) */ 478 int bi_cyl; /* cylinders on disk */ 479 int bi_head; /* heads per track */ 480 int bi_sec; /* sectors per track */ 481 uint64_t bi_lbasecs; /* total sec. (iff ext13) */ 482 #define BIFLAG_INVALID 0x01 483 #define BIFLAG_EXTINT13 0x02 484 int bi_flags; 485 } dl_biosdisks[MAX_BIOSDISKS]; 486 487 int dl_nnativedisks; /* number of native disks */ 488 struct nativedisk_info { 489 char ni_devname[16]; /* native device name */ 490 int ni_nmatches; /* # of matches w/ BIOS */ 491 int ni_biosmatches[MAX_BIOSDISKS]; /* indices in dl_biosdisks */ 492 } dl_nativedisks[1]; /* actually longer */ 493 }; 494 #endif /* !_X86_CPU_H_ */ 495