1 /* $NetBSD: pci_addr_fixup.c,v 1.5 2010/07/26 22:33:23 jym Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 UCHIYAMA Yasushi. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: pci_addr_fixup.c,v 1.5 2010/07/26 22:33:23 jym Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/malloc.h> 35 #include <sys/kernel.h> 36 #include <sys/device.h> 37 #include <sys/extent.h> 38 39 #include <machine/bus.h> 40 41 #include <dev/pci/pcireg.h> 42 #include <dev/pci/pcivar.h> 43 #include <dev/pci/pcidevs.h> 44 45 #include <x86/pci/pci_addr_fixup.h> 46 47 struct pciaddr pciaddr; 48 49 static int pciaddrverbose = 0; 50 51 void pciaddr_resource_reserve(pci_chipset_tag_t, pcitag_t, void *context); 52 int pciaddr_do_resource_reserve(pci_chipset_tag_t, pcitag_t, int, 53 void *, int, bus_addr_t *, bus_size_t); 54 void pciaddr_resource_allocate(pci_chipset_tag_t, pcitag_t, void *context); 55 int pciaddr_do_resource_allocate(pci_chipset_tag_t, pcitag_t, int, 56 void *, int, bus_addr_t *, bus_size_t); 57 int device_is_agp(pci_chipset_tag_t, pcitag_t); 58 59 int device_is_agp(pci_chipset_tag_t, pcitag_t); 60 61 #define PCIADDR_MEM_START 0x0 62 #define PCIADDR_MEM_END 0xffffffff 63 #define PCIADDR_PORT_START 0x0 64 #define PCIADDR_PORT_END 0xffff 65 66 /* for ISA devices */ 67 #define PCIADDR_ISAPORT_RESERVE 0x5800 /* empirical value */ 68 #define PCIADDR_ISAMEM_RESERVE (16 * 1024 * 1024) 69 70 void 71 pci_addr_fixup(pci_chipset_tag_t pc, int maxbus) 72 { 73 extern paddr_t avail_end; 74 const char *verbose_header = 75 "[%s]-----------------------\n" 76 " device vendor product\n" 77 " register space address size\n" 78 "--------------------------------------------\n"; 79 const char *verbose_footer = 80 "--------------------------[%3d devices bogus]\n"; 81 const struct { 82 bus_addr_t start; 83 bus_size_t size; 84 const char *name; 85 } system_reserve [] = { 86 { 0xfec00000, 0x100000, "I/O APIC" }, 87 { 0xfee00000, 0x100000, "Local APIC" }, 88 { 0xfffe0000, 0x20000, "BIOS PROM" }, 89 { 0, 0, 0 }, /* terminator */ 90 }, *srp; 91 paddr_t start; 92 int error; 93 94 pciaddr.extent_mem = extent_create("PCI I/O memory space", 95 PCIADDR_MEM_START, 96 PCIADDR_MEM_END, 97 M_DEVBUF, 0, 0, EX_NOWAIT); 98 KASSERT(pciaddr.extent_mem); 99 pciaddr.extent_port = extent_create("PCI I/O port space", 100 PCIADDR_PORT_START, 101 PCIADDR_PORT_END, 102 M_DEVBUF, 0, 0, EX_NOWAIT); 103 KASSERT(pciaddr.extent_port); 104 105 /* 106 * 1. check & reserve system BIOS setting. 107 */ 108 aprint_debug(verbose_header, "System BIOS Setting"); 109 pci_device_foreach(pc, maxbus, pciaddr_resource_reserve, NULL); 110 aprint_debug(verbose_footer, pciaddr.nbogus); 111 112 /* 113 * 2. reserve non-PCI area. 114 */ 115 for (srp = system_reserve; srp->size; srp++) { 116 error = extent_alloc_region(pciaddr.extent_mem, srp->start, 117 srp->size, 118 EX_NOWAIT| EX_MALLOCOK); 119 if (error != 0) { 120 aprint_error("WARNING: can't reserve area for %s.\n", 121 srp->name); 122 } 123 } 124 125 /* 126 * 3. determine allocation space 127 */ 128 start = x86_round_page(avail_end + 1); 129 if (start < PCIADDR_ISAMEM_RESERVE) 130 start = PCIADDR_ISAMEM_RESERVE; 131 pciaddr.mem_alloc_start = (start + 0x100000 + 1) & ~(0x100000 - 1); 132 pciaddr.port_alloc_start = PCIADDR_ISAPORT_RESERVE; 133 aprint_debug(" Physical memory end: 0x%08x\n PCI memory mapped I/O " 134 "space start: 0x%08x\n", (unsigned)avail_end, 135 (unsigned)pciaddr.mem_alloc_start); 136 137 if (pciaddr.nbogus == 0) 138 return; /* no need to fixup */ 139 140 /* 141 * 4. do fixup 142 */ 143 aprint_debug(verbose_header, "PCIBIOS fixup stage"); 144 pciaddr.nbogus = 0; 145 pci_device_foreach_min(pc, 0, maxbus, pciaddr_resource_allocate, NULL); 146 aprint_debug(verbose_footer, pciaddr.nbogus); 147 148 } 149 150 void 151 pciaddr_resource_reserve(pci_chipset_tag_t pc, pcitag_t tag, 152 void *context) 153 { 154 if (pciaddrverbose) 155 pciaddr_print_devid(pc, tag); 156 pciaddr_resource_manage(pc, tag, 157 pciaddr_do_resource_reserve, 158 &pciaddr); 159 } 160 161 void 162 pciaddr_resource_allocate(pci_chipset_tag_t pc, pcitag_t tag, 163 void *context) 164 { 165 if (pciaddrverbose) 166 pciaddr_print_devid(pc, tag); 167 pciaddr_resource_manage(pc, tag, 168 pciaddr_do_resource_allocate, 169 &pciaddr); 170 } 171 172 void 173 pciaddr_resource_manage(pci_chipset_tag_t pc, pcitag_t tag, 174 pciaddr_resource_manage_func_t func, void *ctx) 175 { 176 pcireg_t val, mask; 177 bus_addr_t addr; 178 bus_size_t size; 179 int error, useport, usemem, mapreg, type, reg_start, reg_end, width; 180 181 val = pci_conf_read(pc, tag, PCI_BHLC_REG); 182 switch (PCI_HDRTYPE_TYPE(val)) { 183 default: 184 aprint_error("WARNING: unknown PCI device header."); 185 pciaddr.nbogus++; 186 return; 187 case 0: 188 reg_start = PCI_MAPREG_START; 189 reg_end = PCI_MAPREG_END; 190 break; 191 case 1: /* PCI-PCI bridge */ 192 reg_start = PCI_MAPREG_START; 193 reg_end = PCI_MAPREG_PPB_END; 194 break; 195 case 2: /* PCI-CardBus bridge */ 196 reg_start = PCI_MAPREG_START; 197 reg_end = PCI_MAPREG_PCB_END; 198 break; 199 } 200 error = useport = usemem = 0; 201 202 for (mapreg = reg_start; mapreg < reg_end; mapreg += width) { 203 /* inquire PCI device bus space requirement */ 204 val = pci_conf_read(pc, tag, mapreg); 205 pci_conf_write(pc, tag, mapreg, ~0); 206 207 mask = pci_conf_read(pc, tag, mapreg); 208 pci_conf_write(pc, tag, mapreg, val); 209 210 type = PCI_MAPREG_TYPE(val); 211 width = 4; 212 if (type == PCI_MAPREG_TYPE_MEM) { 213 if (PCI_MAPREG_MEM_TYPE(val) == 214 PCI_MAPREG_MEM_TYPE_64BIT) { 215 /* XXX We could examine the upper 32 bits 216 * XXX of the BAR here, but we are totally 217 * XXX unprepared to handle a non-zero value, 218 * XXX either here or anywhere else in 219 * XXX i386-land. 220 * XXX So just arrange to not look at the 221 * XXX upper 32 bits, lest we misinterpret 222 * XXX it as a 32-bit BAR set to zero. 223 */ 224 width = 8; 225 } 226 size = PCI_MAPREG_MEM_SIZE(mask); 227 } else { 228 size = PCI_MAPREG_IO_SIZE(mask); 229 } 230 addr = pciaddr_ioaddr(val); 231 232 if (!size) /* unused register */ 233 continue; 234 235 if (type == PCI_MAPREG_TYPE_MEM) 236 ++usemem; 237 else 238 ++useport; 239 240 /* reservation/allocation phase */ 241 error += (*func) (pc, tag, mapreg, ctx, type, &addr, size); 242 243 aprint_debug("\n\t%02xh %s 0x%08x 0x%08x", 244 mapreg, type ? "port" : "mem ", 245 (unsigned int)addr, (unsigned int)size); 246 } 247 248 /* enable/disable PCI device */ 249 val = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 250 if (error == 0) 251 val |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 252 PCI_COMMAND_MASTER_ENABLE); 253 else 254 val &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 255 PCI_COMMAND_MASTER_ENABLE); 256 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, val); 257 258 if (error) 259 pciaddr.nbogus++; 260 261 aprint_debug("\n\t\t[%s]\n", error ? "NG" : "OK"); 262 } 263 264 int 265 pciaddr_do_resource_allocate(pci_chipset_tag_t pc, pcitag_t tag, 266 int mapreg, void *ctx, int type, bus_addr_t *addr, bus_size_t size) 267 { 268 struct pciaddr *pciaddrmap = (struct pciaddr *)ctx; 269 bus_addr_t start; 270 int error; 271 struct extent *ex; 272 273 if (*addr) /* no need to allocate */ 274 return (0); 275 276 ex = (type == PCI_MAPREG_TYPE_MEM ? 277 pciaddrmap->extent_mem : pciaddrmap->extent_port); 278 279 /* XXX Don't allocate if device is AGP device to avoid conflict. */ 280 if (device_is_agp(pc, tag)) 281 return (0); 282 283 start = (type == PCI_MAPREG_TYPE_MEM ? 284 pciaddrmap->mem_alloc_start : pciaddrmap->port_alloc_start); 285 286 if (start < ex->ex_start || start + size - 1 >= ex->ex_end) { 287 aprint_debug("No available resources. fixup failed\n"); 288 return (1); 289 } 290 error = extent_alloc_subregion(ex, start, ex->ex_end, size, 291 size, 0, 292 EX_FAST|EX_NOWAIT|EX_MALLOCOK, 293 (u_long *)addr); 294 if (error) { 295 aprint_debug("No available resources. fixup failed\n"); 296 return (1); 297 } 298 299 /* write new address to PCI device configuration header */ 300 pci_conf_write(pc, tag, mapreg, *addr); 301 /* check */ 302 if (!pciaddrverbose) 303 { 304 aprint_verbose("pci_addr_fixup: "); 305 pciaddr_print_devid(pc, tag); 306 } 307 if (pciaddr_ioaddr(pci_conf_read(pc, tag, mapreg)) != *addr) { 308 pci_conf_write(pc, tag, mapreg, 0); /* clear */ 309 aprint_error("fixup failed. (new address=%#x)\n", (unsigned)*addr); 310 return (1); 311 } 312 if (!pciaddrverbose) 313 aprint_verbose("new address 0x%08x\n", (unsigned)*addr); 314 315 return (0); 316 } 317 318 int 319 pciaddr_do_resource_reserve(pci_chipset_tag_t pc, pcitag_t tag, 320 int mapreg, void *ctx, int type, bus_addr_t *addr, bus_size_t size) 321 { 322 struct extent *ex; 323 struct pciaddr *pciaddrmap = (struct pciaddr *)ctx; 324 int error; 325 326 if (*addr == 0) 327 return (1); 328 329 ex = (type == PCI_MAPREG_TYPE_MEM ? 330 pciaddrmap->extent_mem : pciaddrmap->extent_port); 331 332 error = extent_alloc_region(ex, *addr, size, EX_NOWAIT| EX_MALLOCOK); 333 if (error) { 334 aprint_debug("Resource conflict.\n"); 335 pci_conf_write(pc, tag, mapreg, 0); /* clear */ 336 return (1); 337 } 338 339 return (0); 340 } 341 342 bus_addr_t 343 pciaddr_ioaddr(uint32_t val) 344 { 345 return ((PCI_MAPREG_TYPE(val) == PCI_MAPREG_TYPE_MEM) 346 ? PCI_MAPREG_MEM_ADDR(val) 347 : PCI_MAPREG_IO_ADDR(val)); 348 } 349 350 void 351 pciaddr_print_devid(pci_chipset_tag_t pc, pcitag_t tag) 352 { 353 int bus, device, function; 354 pcireg_t id; 355 356 id = pci_conf_read(pc, tag, PCI_ID_REG); 357 pci_decompose_tag(pc, tag, &bus, &device, &function); 358 aprint_verbose("%03d:%02d:%d 0x%04x 0x%04x ", bus, device, function, 359 PCI_VENDOR(id), PCI_PRODUCT(id)); 360 } 361 362 int 363 device_is_agp(pci_chipset_tag_t pc, pcitag_t tag) 364 { 365 pcireg_t class, status, rval; 366 int off; 367 368 /* Check AGP device. */ 369 class = pci_conf_read(pc, tag, PCI_CLASS_REG); 370 if (PCI_CLASS(class) == PCI_CLASS_DISPLAY) { 371 status = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 372 if (status & PCI_STATUS_CAPLIST_SUPPORT) { 373 rval = pci_conf_read(pc, tag, PCI_CAPLISTPTR_REG); 374 for (off = PCI_CAPLIST_PTR(rval); 375 off != 0; 376 off = PCI_CAPLIST_NEXT(rval) ) { 377 rval = pci_conf_read(pc, tag, off); 378 if (PCI_CAPLIST_CAP(rval) == PCI_CAP_AGP) 379 return (1); 380 } 381 } 382 } 383 return (0); 384 } 385