1 /* $NetBSD: x86_xpmap.c,v 1.23 2010/12/20 21:18:45 jym Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Mathieu Ropert <mro@adviseo.fr> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * Copyright (c) 2006, 2007 Manuel Bouyer. 21 * 22 * Redistribution and use in source and binary forms, with or without 23 * modification, are permitted provided that the following conditions 24 * are met: 25 * 1. Redistributions of source code must retain the above copyright 26 * notice, this list of conditions and the following disclaimer. 27 * 2. Redistributions in binary form must reproduce the above copyright 28 * notice, this list of conditions and the following disclaimer in the 29 * documentation and/or other materials provided with the distribution. 30 * 31 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 32 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 33 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 34 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 35 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 36 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 40 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 41 * 42 */ 43 44 /* 45 * 46 * Copyright (c) 2004 Christian Limpach. 47 * All rights reserved. 48 * 49 * Redistribution and use in source and binary forms, with or without 50 * modification, are permitted provided that the following conditions 51 * are met: 52 * 1. Redistributions of source code must retain the above copyright 53 * notice, this list of conditions and the following disclaimer. 54 * 2. Redistributions in binary form must reproduce the above copyright 55 * notice, this list of conditions and the following disclaimer in the 56 * documentation and/or other materials provided with the distribution. 57 * 58 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 59 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 60 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 61 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 62 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 63 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 64 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 65 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 66 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 67 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 68 */ 69 70 71 #include <sys/cdefs.h> 72 __KERNEL_RCSID(0, "$NetBSD: x86_xpmap.c,v 1.23 2010/12/20 21:18:45 jym Exp $"); 73 74 #include "opt_xen.h" 75 #include "opt_ddb.h" 76 #include "ksyms.h" 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 81 #include <uvm/uvm.h> 82 83 #include <machine/pmap.h> 84 #include <machine/gdt.h> 85 #include <xen/xenfunc.h> 86 87 #include <dev/isa/isareg.h> 88 #include <machine/isa_machdep.h> 89 90 #undef XENDEBUG 91 /* #define XENDEBUG_SYNC */ 92 /* #define XENDEBUG_LOW */ 93 94 #ifdef XENDEBUG 95 #define XENPRINTF(x) printf x 96 #define XENPRINTK(x) printk x 97 #define XENPRINTK2(x) /* printk x */ 98 99 static char XBUF[256]; 100 #else 101 #define XENPRINTF(x) 102 #define XENPRINTK(x) 103 #define XENPRINTK2(x) 104 #endif 105 #define PRINTF(x) printf x 106 #define PRINTK(x) printk x 107 108 /* on x86_64 kernel runs in ring 3 */ 109 #ifdef __x86_64__ 110 #define PG_k PG_u 111 #else 112 #define PG_k 0 113 #endif 114 115 volatile shared_info_t *HYPERVISOR_shared_info; 116 /* Xen requires the start_info struct to be page aligned */ 117 union start_info_union start_info_union __aligned(PAGE_SIZE); 118 unsigned long *xpmap_phys_to_machine_mapping; 119 120 void xen_failsafe_handler(void); 121 122 #define HYPERVISOR_mmu_update_self(req, count, success_count) \ 123 HYPERVISOR_mmu_update((req), (count), (success_count), DOMID_SELF) 124 125 void 126 xen_failsafe_handler(void) 127 { 128 129 panic("xen_failsafe_handler called!\n"); 130 } 131 132 133 void 134 xen_set_ldt(vaddr_t base, uint32_t entries) 135 { 136 vaddr_t va; 137 vaddr_t end; 138 pt_entry_t *ptp; 139 int s; 140 141 #ifdef __x86_64__ 142 end = base + (entries << 3); 143 #else 144 end = base + entries * sizeof(union descriptor); 145 #endif 146 147 for (va = base; va < end; va += PAGE_SIZE) { 148 KASSERT(va >= VM_MIN_KERNEL_ADDRESS); 149 ptp = kvtopte(va); 150 XENPRINTF(("xen_set_ldt %#" PRIxVADDR " %d %p\n", 151 base, entries, ptp)); 152 pmap_pte_clearbits(ptp, PG_RW); 153 } 154 s = splvm(); 155 xpq_queue_set_ldt(base, entries); 156 splx(s); 157 } 158 159 #ifdef XENDEBUG 160 void xpq_debug_dump(void); 161 #endif 162 163 #define XPQUEUE_SIZE 2048 164 static mmu_update_t xpq_queue[XPQUEUE_SIZE]; 165 static int xpq_idx = 0; 166 167 void 168 xpq_flush_queue(void) 169 { 170 int i, ok, ret; 171 172 XENPRINTK2(("flush queue %p entries %d\n", xpq_queue, xpq_idx)); 173 for (i = 0; i < xpq_idx; i++) 174 XENPRINTK2(("%d: 0x%08" PRIx64 " 0x%08" PRIx64 "\n", i, 175 xpq_queue[i].ptr, xpq_queue[i].val)); 176 177 ret = HYPERVISOR_mmu_update_self(xpq_queue, xpq_idx, &ok); 178 179 if (xpq_idx != 0 && ret < 0) { 180 printf("xpq_flush_queue: %d entries (%d successful)\n", 181 xpq_idx, ok); 182 for (i = 0; i < xpq_idx; i++) 183 printf("0x%016" PRIx64 ": 0x%016" PRIx64 "\n", 184 xpq_queue[i].ptr, xpq_queue[i].val); 185 panic("HYPERVISOR_mmu_update failed, ret: %d\n", ret); 186 } 187 xpq_idx = 0; 188 } 189 190 static inline void 191 xpq_increment_idx(void) 192 { 193 194 xpq_idx++; 195 if (__predict_false(xpq_idx == XPQUEUE_SIZE)) 196 xpq_flush_queue(); 197 } 198 199 void 200 xpq_queue_machphys_update(paddr_t ma, paddr_t pa) 201 { 202 XENPRINTK2(("xpq_queue_machphys_update ma=0x%" PRIx64 " pa=0x%" PRIx64 203 "\n", (int64_t)ma, (int64_t)pa)); 204 xpq_queue[xpq_idx].ptr = ma | MMU_MACHPHYS_UPDATE; 205 xpq_queue[xpq_idx].val = (pa - XPMAP_OFFSET) >> PAGE_SHIFT; 206 xpq_increment_idx(); 207 #ifdef XENDEBUG_SYNC 208 xpq_flush_queue(); 209 #endif 210 } 211 212 void 213 xpq_queue_pte_update(paddr_t ptr, pt_entry_t val) 214 { 215 216 KASSERT((ptr & 3) == 0); 217 xpq_queue[xpq_idx].ptr = (paddr_t)ptr | MMU_NORMAL_PT_UPDATE; 218 xpq_queue[xpq_idx].val = val; 219 xpq_increment_idx(); 220 #ifdef XENDEBUG_SYNC 221 xpq_flush_queue(); 222 #endif 223 } 224 225 void 226 xpq_queue_pt_switch(paddr_t pa) 227 { 228 struct mmuext_op op; 229 xpq_flush_queue(); 230 231 XENPRINTK2(("xpq_queue_pt_switch: 0x%" PRIx64 " 0x%" PRIx64 "\n", 232 (int64_t)pa, (int64_t)pa)); 233 op.cmd = MMUEXT_NEW_BASEPTR; 234 op.arg1.mfn = pa >> PAGE_SHIFT; 235 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 236 panic("xpq_queue_pt_switch"); 237 } 238 239 void 240 xpq_queue_pin_table(paddr_t pa) 241 { 242 struct mmuext_op op; 243 xpq_flush_queue(); 244 245 XENPRINTK2(("xpq_queue_pin_table: 0x%" PRIx64 " 0x%" PRIx64 "\n", 246 (int64_t)pa, (int64_t)pa)); 247 op.arg1.mfn = pa >> PAGE_SHIFT; 248 249 #if defined(__x86_64__) 250 op.cmd = MMUEXT_PIN_L4_TABLE; 251 #else 252 op.cmd = MMUEXT_PIN_L2_TABLE; 253 #endif 254 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 255 panic("xpq_queue_pin_table"); 256 } 257 258 #ifdef PAE 259 static void 260 xpq_queue_pin_l3_table(paddr_t pa) 261 { 262 struct mmuext_op op; 263 xpq_flush_queue(); 264 265 XENPRINTK2(("xpq_queue_pin_l2_table: 0x%" PRIx64 " 0x%" PRIx64 "\n", 266 (int64_t)pa, (int64_t)pa)); 267 op.arg1.mfn = pa >> PAGE_SHIFT; 268 269 op.cmd = MMUEXT_PIN_L3_TABLE; 270 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 271 panic("xpq_queue_pin_table"); 272 } 273 #endif 274 275 void 276 xpq_queue_unpin_table(paddr_t pa) 277 { 278 struct mmuext_op op; 279 xpq_flush_queue(); 280 281 XENPRINTK2(("xpq_queue_unpin_table: 0x%" PRIx64 " 0x%" PRIx64 "\n", 282 (int64_t)pa, (int64_t)pa)); 283 op.arg1.mfn = pa >> PAGE_SHIFT; 284 op.cmd = MMUEXT_UNPIN_TABLE; 285 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 286 panic("xpq_queue_unpin_table"); 287 } 288 289 void 290 xpq_queue_set_ldt(vaddr_t va, uint32_t entries) 291 { 292 struct mmuext_op op; 293 xpq_flush_queue(); 294 295 XENPRINTK2(("xpq_queue_set_ldt\n")); 296 KASSERT(va == (va & ~PAGE_MASK)); 297 op.cmd = MMUEXT_SET_LDT; 298 op.arg1.linear_addr = va; 299 op.arg2.nr_ents = entries; 300 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 301 panic("xpq_queue_set_ldt"); 302 } 303 304 void 305 xpq_queue_tlb_flush(void) 306 { 307 struct mmuext_op op; 308 xpq_flush_queue(); 309 310 XENPRINTK2(("xpq_queue_tlb_flush\n")); 311 op.cmd = MMUEXT_TLB_FLUSH_LOCAL; 312 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 313 panic("xpq_queue_tlb_flush"); 314 } 315 316 void 317 xpq_flush_cache(void) 318 { 319 struct mmuext_op op; 320 int s = splvm(); 321 xpq_flush_queue(); 322 323 XENPRINTK2(("xpq_queue_flush_cache\n")); 324 op.cmd = MMUEXT_FLUSH_CACHE; 325 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 326 panic("xpq_flush_cache"); 327 splx(s); 328 } 329 330 void 331 xpq_queue_invlpg(vaddr_t va) 332 { 333 struct mmuext_op op; 334 xpq_flush_queue(); 335 336 XENPRINTK2(("xpq_queue_invlpg %#" PRIxVADDR "\n", va)); 337 op.cmd = MMUEXT_INVLPG_LOCAL; 338 op.arg1.linear_addr = (va & ~PAGE_MASK); 339 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 340 panic("xpq_queue_invlpg"); 341 } 342 343 int 344 xpq_update_foreign(paddr_t ptr, pt_entry_t val, int dom) 345 { 346 mmu_update_t op; 347 int ok; 348 xpq_flush_queue(); 349 350 op.ptr = ptr; 351 op.val = val; 352 if (HYPERVISOR_mmu_update(&op, 1, &ok, dom) < 0) 353 return EFAULT; 354 return (0); 355 } 356 357 #ifdef XENDEBUG 358 void 359 xpq_debug_dump(void) 360 { 361 int i; 362 363 XENPRINTK2(("idx: %d\n", xpq_idx)); 364 for (i = 0; i < xpq_idx; i++) { 365 snprintf(XBUF, sizeof(XBUF), "%" PRIx64 " %08" PRIx64, 366 xpq_queue[i].ptr, xpq_queue[i].val); 367 if (++i < xpq_idx) 368 snprintf(XBUF + strlen(XBUF), 369 sizeof(XBUF) - strlen(XBUF), 370 "%" PRIx64 " %08" PRIx64, 371 xpq_queue[i].ptr, xpq_queue[i].val); 372 if (++i < xpq_idx) 373 snprintf(XBUF + strlen(XBUF), 374 sizeof(XBUF) - strlen(XBUF), 375 "%" PRIx64 " %08" PRIx64, 376 xpq_queue[i].ptr, xpq_queue[i].val); 377 if (++i < xpq_idx) 378 snprintf(XBUF + strlen(XBUF), 379 sizeof(XBUF) - strlen(XBUF), 380 "%" PRIx64 " %08" PRIx64, 381 xpq_queue[i].ptr, xpq_queue[i].val); 382 XENPRINTK2(("%d: %s\n", xpq_idx, XBUF)); 383 } 384 } 385 #endif 386 387 388 extern volatile struct xencons_interface *xencons_interface; /* XXX */ 389 extern struct xenstore_domain_interface *xenstore_interface; /* XXX */ 390 391 static void xen_bt_set_readonly (vaddr_t); 392 static void xen_bootstrap_tables (vaddr_t, vaddr_t, int, int, int); 393 394 /* How many PDEs ? */ 395 #if L2_SLOT_KERNBASE > 0 396 #define TABLE_L2_ENTRIES (2 * (NKL2_KIMG_ENTRIES + 1)) 397 #else 398 #define TABLE_L2_ENTRIES (NKL2_KIMG_ENTRIES + 1) 399 #endif 400 401 /* 402 * Construct and switch to new pagetables 403 * first_avail is the first vaddr we can use after 404 * we get rid of Xen pagetables 405 */ 406 407 vaddr_t xen_pmap_bootstrap (void); 408 409 /* 410 * Function to get rid of Xen bootstrap tables 411 */ 412 413 /* How many PDP do we need: */ 414 #ifdef PAE 415 /* 416 * For PAE, we consider a single contigous L2 "superpage" of 4 pages, 417 * all of them mapped by the L3 page. We also need a shadow page 418 * for L3[3]. 419 */ 420 static const int l2_4_count = 6; 421 #else 422 static const int l2_4_count = PTP_LEVELS - 1; 423 #endif 424 425 vaddr_t 426 xen_pmap_bootstrap(void) 427 { 428 int count, oldcount; 429 long mapsize; 430 vaddr_t bootstrap_tables, init_tables; 431 432 xpmap_phys_to_machine_mapping = 433 (unsigned long *)xen_start_info.mfn_list; 434 init_tables = xen_start_info.pt_base; 435 __PRINTK(("xen_arch_pmap_bootstrap init_tables=0x%lx\n", init_tables)); 436 437 /* Space after Xen boostrap tables should be free */ 438 bootstrap_tables = xen_start_info.pt_base + 439 (xen_start_info.nr_pt_frames * PAGE_SIZE); 440 441 /* 442 * Calculate how many space we need 443 * first everything mapped before the Xen bootstrap tables 444 */ 445 mapsize = init_tables - KERNTEXTOFF; 446 /* after the tables we'll have: 447 * - UAREA 448 * - dummy user PGD (x86_64) 449 * - HYPERVISOR_shared_info 450 * - ISA I/O mem (if needed) 451 */ 452 mapsize += UPAGES * NBPG; 453 #ifdef __x86_64__ 454 mapsize += NBPG; 455 #endif 456 mapsize += NBPG; 457 458 #ifdef DOM0OPS 459 if (xendomain_is_dom0()) { 460 /* space for ISA I/O mem */ 461 mapsize += IOM_SIZE; 462 } 463 #endif 464 /* at this point mapsize doens't include the table size */ 465 466 #ifdef __x86_64__ 467 count = TABLE_L2_ENTRIES; 468 #else 469 count = (mapsize + (NBPD_L2 -1)) >> L2_SHIFT; 470 #endif /* __x86_64__ */ 471 472 /* now compute how many L2 pages we need exactly */ 473 XENPRINTK(("bootstrap_final mapsize 0x%lx count %d\n", mapsize, count)); 474 while (mapsize + (count + l2_4_count) * PAGE_SIZE + KERNTEXTOFF > 475 ((long)count << L2_SHIFT) + KERNBASE) { 476 count++; 477 } 478 #ifndef __x86_64__ 479 /* 480 * one more L2 page: we'll alocate several pages after kva_start 481 * in pmap_bootstrap() before pmap_growkernel(), which have not been 482 * counted here. It's not a big issue to allocate one more L2 as 483 * pmap_growkernel() will be called anyway. 484 */ 485 count++; 486 nkptp[1] = count; 487 #endif 488 489 /* 490 * install bootstrap pages. We may need more L2 pages than will 491 * have the final table here, as it's installed after the final table 492 */ 493 oldcount = count; 494 495 bootstrap_again: 496 XENPRINTK(("bootstrap_again oldcount %d\n", oldcount)); 497 /* 498 * Xen space we'll reclaim may not be enough for our new page tables, 499 * move bootstrap tables if necessary 500 */ 501 if (bootstrap_tables < init_tables + ((count + l2_4_count) * PAGE_SIZE)) 502 bootstrap_tables = init_tables + 503 ((count + l2_4_count) * PAGE_SIZE); 504 /* make sure we have enough to map the bootstrap_tables */ 505 if (bootstrap_tables + ((oldcount + l2_4_count) * PAGE_SIZE) > 506 ((long)oldcount << L2_SHIFT) + KERNBASE) { 507 oldcount++; 508 goto bootstrap_again; 509 } 510 511 /* Create temporary tables */ 512 xen_bootstrap_tables(xen_start_info.pt_base, bootstrap_tables, 513 xen_start_info.nr_pt_frames, oldcount, 0); 514 515 /* Create final tables */ 516 xen_bootstrap_tables(bootstrap_tables, init_tables, 517 oldcount + l2_4_count, count, 1); 518 519 /* zero out free space after tables */ 520 memset((void *)(init_tables + ((count + l2_4_count) * PAGE_SIZE)), 0, 521 (UPAGES + 1) * NBPG); 522 return (init_tables + ((count + l2_4_count) * PAGE_SIZE)); 523 } 524 525 526 /* 527 * Build a new table and switch to it 528 * old_count is # of old tables (including PGD, PDTPE and PDE) 529 * new_count is # of new tables (PTE only) 530 * we assume areas don't overlap 531 */ 532 533 534 static void 535 xen_bootstrap_tables (vaddr_t old_pgd, vaddr_t new_pgd, 536 int old_count, int new_count, int final) 537 { 538 pd_entry_t *pdtpe, *pde, *pte; 539 pd_entry_t *cur_pgd, *bt_pgd; 540 paddr_t addr; 541 vaddr_t page, avail, text_end, map_end; 542 int i; 543 extern char __data_start; 544 545 __PRINTK(("xen_bootstrap_tables(%#" PRIxVADDR ", %#" PRIxVADDR "," 546 " %d, %d)\n", 547 old_pgd, new_pgd, old_count, new_count)); 548 text_end = ((vaddr_t)&__data_start) & ~PAGE_MASK; 549 /* 550 * size of R/W area after kernel text: 551 * xencons_interface (if present) 552 * xenstore_interface (if present) 553 * table pages (new_count + l2_4_count entries) 554 * extra mappings (only when final is true): 555 * UAREA 556 * dummy user PGD (x86_64 only)/gdt page (i386 only) 557 * HYPERVISOR_shared_info 558 * ISA I/O mem (if needed) 559 */ 560 map_end = new_pgd + ((new_count + l2_4_count) * NBPG); 561 if (final) { 562 map_end += (UPAGES + 1) * NBPG; 563 HYPERVISOR_shared_info = (shared_info_t *)map_end; 564 map_end += NBPG; 565 } 566 /* 567 * we always set atdevbase, as it's used by init386 to find the first 568 * available VA. map_end is updated only if we are dom0, so 569 * atdevbase -> atdevbase + IOM_SIZE will be mapped only in 570 * this case. 571 */ 572 if (final) 573 atdevbase = map_end; 574 #ifdef DOM0OPS 575 if (final && xendomain_is_dom0()) { 576 /* ISA I/O mem */ 577 map_end += IOM_SIZE; 578 } 579 #endif /* DOM0OPS */ 580 581 __PRINTK(("xen_bootstrap_tables text_end 0x%lx map_end 0x%lx\n", 582 text_end, map_end)); 583 __PRINTK(("console %#lx ", xen_start_info.console_mfn)); 584 __PRINTK(("xenstore %#" PRIx32 "\n", xen_start_info.store_mfn)); 585 586 /* 587 * Create bootstrap page tables 588 * What we need: 589 * - a PGD (level 4) 590 * - a PDTPE (level 3) 591 * - a PDE (level2) 592 * - some PTEs (level 1) 593 */ 594 595 cur_pgd = (pd_entry_t *) old_pgd; 596 bt_pgd = (pd_entry_t *) new_pgd; 597 memset (bt_pgd, 0, PAGE_SIZE); 598 avail = new_pgd + PAGE_SIZE; 599 #if PTP_LEVELS > 3 600 /* Install level 3 */ 601 pdtpe = (pd_entry_t *) avail; 602 memset (pdtpe, 0, PAGE_SIZE); 603 avail += PAGE_SIZE; 604 605 addr = ((u_long) pdtpe) - KERNBASE; 606 bt_pgd[pl4_pi(KERNTEXTOFF)] = 607 xpmap_ptom_masked(addr) | PG_k | PG_RW | PG_V; 608 609 __PRINTK(("L3 va %#lx pa %#" PRIxPADDR " entry %#" PRIxPADDR 610 " -> L4[%#x]\n", 611 pdtpe, addr, bt_pgd[pl4_pi(KERNTEXTOFF)], pl4_pi(KERNTEXTOFF))); 612 #else 613 pdtpe = bt_pgd; 614 #endif /* PTP_LEVELS > 3 */ 615 616 #if PTP_LEVELS > 2 617 /* Level 2 */ 618 pde = (pd_entry_t *) avail; 619 memset(pde, 0, PAGE_SIZE); 620 avail += PAGE_SIZE; 621 622 addr = ((u_long) pde) - KERNBASE; 623 pdtpe[pl3_pi(KERNTEXTOFF)] = 624 xpmap_ptom_masked(addr) | PG_k | PG_V | PG_RW; 625 __PRINTK(("L2 va %#lx pa %#" PRIxPADDR " entry %#" PRIxPADDR 626 " -> L3[%#x]\n", 627 pde, addr, pdtpe[pl3_pi(KERNTEXTOFF)], pl3_pi(KERNTEXTOFF))); 628 #elif defined(PAE) 629 /* our PAE-style level 2: 5 contigous pages (4 L2 + 1 shadow) */ 630 pde = (pd_entry_t *) avail; 631 memset(pde, 0, PAGE_SIZE * 5); 632 avail += PAGE_SIZE * 5; 633 addr = ((u_long) pde) - KERNBASE; 634 /* 635 * enter L2 pages in the L3. 636 * The real L2 kernel PD will be the last one (so that 637 * pde[L2_SLOT_KERN] always point to the shadow). 638 */ 639 for (i = 0; i < 3; i++, addr += PAGE_SIZE) { 640 /* 641 * Xen doens't want R/W mappings in L3 entries, it'll add it 642 * itself. 643 */ 644 pdtpe[i] = xpmap_ptom_masked(addr) | PG_k | PG_V; 645 __PRINTK(("L2 va %#lx pa %#" PRIxPADDR " entry %#" PRIxPADDR 646 " -> L3[%#x]\n", 647 (vaddr_t)pde + PAGE_SIZE * i, addr, pdtpe[i], i)); 648 } 649 addr += PAGE_SIZE; 650 pdtpe[3] = xpmap_ptom_masked(addr) | PG_k | PG_V; 651 __PRINTK(("L2 va %#lx pa %#" PRIxPADDR " entry %#" PRIxPADDR 652 " -> L3[%#x]\n", 653 (vaddr_t)pde + PAGE_SIZE * 4, addr, pdtpe[3], 3)); 654 655 #else /* PAE */ 656 pde = bt_pgd; 657 #endif /* PTP_LEVELS > 2 */ 658 659 /* Level 1 */ 660 page = KERNTEXTOFF; 661 for (i = 0; i < new_count; i ++) { 662 vaddr_t cur_page = page; 663 664 pte = (pd_entry_t *) avail; 665 avail += PAGE_SIZE; 666 667 memset(pte, 0, PAGE_SIZE); 668 while (pl2_pi(page) == pl2_pi (cur_page)) { 669 if (page >= map_end) { 670 /* not mapped at all */ 671 pte[pl1_pi(page)] = 0; 672 page += PAGE_SIZE; 673 continue; 674 } 675 pte[pl1_pi(page)] = xpmap_ptom_masked(page - KERNBASE); 676 if (page == (vaddr_t)HYPERVISOR_shared_info) { 677 pte[pl1_pi(page)] = xen_start_info.shared_info; 678 __PRINTK(("HYPERVISOR_shared_info " 679 "va %#lx pte %#" PRIxPADDR "\n", 680 HYPERVISOR_shared_info, pte[pl1_pi(page)])); 681 } 682 if ((xpmap_ptom_masked(page - KERNBASE) >> PAGE_SHIFT) 683 == xen_start_info.console.domU.mfn) { 684 xencons_interface = (void *)page; 685 pte[pl1_pi(page)] = xen_start_info.console_mfn; 686 pte[pl1_pi(page)] <<= PAGE_SHIFT; 687 __PRINTK(("xencons_interface " 688 "va %#lx pte %#" PRIxPADDR "\n", 689 xencons_interface, pte[pl1_pi(page)])); 690 } 691 if ((xpmap_ptom_masked(page - KERNBASE) >> PAGE_SHIFT) 692 == xen_start_info.store_mfn) { 693 xenstore_interface = (void *)page; 694 pte[pl1_pi(page)] = xen_start_info.store_mfn; 695 pte[pl1_pi(page)] <<= PAGE_SHIFT; 696 __PRINTK(("xenstore_interface " 697 "va %#lx pte %#" PRIxPADDR "\n", 698 xenstore_interface, pte[pl1_pi(page)])); 699 } 700 #ifdef DOM0OPS 701 if (page >= (vaddr_t)atdevbase && 702 page < (vaddr_t)atdevbase + IOM_SIZE) { 703 pte[pl1_pi(page)] = 704 IOM_BEGIN + (page - (vaddr_t)atdevbase); 705 } 706 #endif 707 pte[pl1_pi(page)] |= PG_k | PG_V; 708 if (page < text_end) { 709 /* map kernel text RO */ 710 pte[pl1_pi(page)] |= 0; 711 } else if (page >= old_pgd 712 && page < old_pgd + (old_count * PAGE_SIZE)) { 713 /* map old page tables RO */ 714 pte[pl1_pi(page)] |= 0; 715 } else if (page >= new_pgd && 716 page < new_pgd + ((new_count + l2_4_count) * PAGE_SIZE)) { 717 /* map new page tables RO */ 718 pte[pl1_pi(page)] |= 0; 719 } else { 720 /* map page RW */ 721 pte[pl1_pi(page)] |= PG_RW; 722 } 723 724 if ((page >= old_pgd && page < old_pgd + (old_count * PAGE_SIZE)) 725 || page >= new_pgd) { 726 __PRINTK(("va %#lx pa %#lx " 727 "entry 0x%" PRIxPADDR " -> L1[%#x]\n", 728 page, page - KERNBASE, 729 pte[pl1_pi(page)], pl1_pi(page))); 730 } 731 page += PAGE_SIZE; 732 } 733 734 addr = ((u_long) pte) - KERNBASE; 735 pde[pl2_pi(cur_page)] = 736 xpmap_ptom_masked(addr) | PG_k | PG_RW | PG_V; 737 __PRINTK(("L1 va %#lx pa %#" PRIxPADDR " entry %#" PRIxPADDR 738 " -> L2[%#x]\n", 739 pte, addr, pde[pl2_pi(cur_page)], pl2_pi(cur_page))); 740 /* Mark readonly */ 741 xen_bt_set_readonly((vaddr_t) pte); 742 } 743 744 /* Install recursive page tables mapping */ 745 #ifdef PAE 746 /* 747 * we need a shadow page for the kernel's L2 page 748 * The real L2 kernel PD will be the last one (so that 749 * pde[L2_SLOT_KERN] always point to the shadow. 750 */ 751 memcpy(&pde[L2_SLOT_KERN + NPDPG], &pde[L2_SLOT_KERN], PAGE_SIZE); 752 pmap_kl2pd = &pde[L2_SLOT_KERN + NPDPG]; 753 pmap_kl2paddr = (u_long)pmap_kl2pd - KERNBASE; 754 755 /* 756 * We don't enter a recursive entry from the L3 PD. Instead, 757 * we enter the first 4 L2 pages, which includes the kernel's L2 758 * shadow. But we have to entrer the shadow after switching 759 * %cr3, or Xen will refcount some PTE with the wrong type. 760 */ 761 addr = (u_long)pde - KERNBASE; 762 for (i = 0; i < 3; i++, addr += PAGE_SIZE) { 763 pde[PDIR_SLOT_PTE + i] = xpmap_ptom_masked(addr) | PG_k | PG_V; 764 __PRINTK(("pde[%d] va %#" PRIxVADDR " pa %#" PRIxPADDR 765 " entry %#" PRIxPADDR "\n", 766 (int)(PDIR_SLOT_PTE + i), pde + PAGE_SIZE * i, 767 addr, pde[PDIR_SLOT_PTE + i])); 768 } 769 #if 0 770 addr += PAGE_SIZE; /* point to shadow L2 */ 771 pde[PDIR_SLOT_PTE + 3] = xpmap_ptom_masked(addr) | PG_k | PG_V; 772 __PRINTK(("pde[%d] va 0x%lx pa 0x%lx entry 0x%" PRIx64 "\n", 773 (int)(PDIR_SLOT_PTE + 3), pde + PAGE_SIZE * 4, (long)addr, 774 (int64_t)pde[PDIR_SLOT_PTE + 3])); 775 #endif 776 /* Mark tables RO, and pin the kernel's shadow as L2 */ 777 addr = (u_long)pde - KERNBASE; 778 for (i = 0; i < 5; i++, addr += PAGE_SIZE) { 779 xen_bt_set_readonly(((vaddr_t)pde) + PAGE_SIZE * i); 780 if (i == 2 || i == 3) 781 continue; 782 #if 0 783 __PRINTK(("pin L2 %d addr 0x%" PRIx64 "\n", i, (int64_t)addr)); 784 xpq_queue_pin_table(xpmap_ptom_masked(addr)); 785 #endif 786 } 787 if (final) { 788 addr = (u_long)pde - KERNBASE + 3 * PAGE_SIZE; 789 __PRINTK(("pin L2 %d addr %#" PRIxPADDR "\n", 2, addr)); 790 xpq_queue_pin_table(xpmap_ptom_masked(addr)); 791 } 792 #if 0 793 addr = (u_long)pde - KERNBASE + 2 * PAGE_SIZE; 794 __PRINTK(("pin L2 %d addr 0x%" PRIx64 "\n", 2, (int64_t)addr)); 795 xpq_queue_pin_table(xpmap_ptom_masked(addr)); 796 #endif 797 #else /* PAE */ 798 /* recursive entry in higher-level PD */ 799 bt_pgd[PDIR_SLOT_PTE] = 800 xpmap_ptom_masked(new_pgd - KERNBASE) | PG_k | PG_V; 801 __PRINTK(("bt_pgd[PDIR_SLOT_PTE] va %#" PRIxVADDR " pa %#" PRIxPADDR 802 " entry %#" PRIxPADDR "\n", new_pgd, (paddr_t)new_pgd - KERNBASE, 803 bt_pgd[PDIR_SLOT_PTE])); 804 /* Mark tables RO */ 805 xen_bt_set_readonly((vaddr_t) pde); 806 #endif 807 #if PTP_LEVELS > 2 || defined(PAE) 808 xen_bt_set_readonly((vaddr_t) pdtpe); 809 #endif 810 #if PTP_LEVELS > 3 811 xen_bt_set_readonly(new_pgd); 812 #endif 813 /* Pin the PGD */ 814 __PRINTK(("pin PGD\n")); 815 #ifdef PAE 816 xpq_queue_pin_l3_table(xpmap_ptom_masked(new_pgd - KERNBASE)); 817 #else 818 xpq_queue_pin_table(xpmap_ptom_masked(new_pgd - KERNBASE)); 819 #endif 820 821 /* Save phys. addr of PDP, for libkvm. */ 822 #ifdef PAE 823 PDPpaddr = (u_long)pde - KERNBASE; /* PDP is the L2 with PAE */ 824 #else 825 PDPpaddr = (u_long)new_pgd - KERNBASE; 826 #endif 827 828 /* Switch to new tables */ 829 __PRINTK(("switch to PGD\n")); 830 xpq_queue_pt_switch(xpmap_ptom_masked(new_pgd - KERNBASE)); 831 __PRINTK(("bt_pgd[PDIR_SLOT_PTE] now entry %#" PRIxPADDR "\n", 832 bt_pgd[PDIR_SLOT_PTE])); 833 834 #ifdef PAE 835 if (final) { 836 /* save the address of the L3 page */ 837 cpu_info_primary.ci_pae_l3_pdir = pdtpe; 838 cpu_info_primary.ci_pae_l3_pdirpa = (new_pgd - KERNBASE); 839 840 /* now enter kernel's PTE mappings */ 841 addr = (u_long)pde - KERNBASE + PAGE_SIZE * 3; 842 xpq_queue_pte_update( 843 xpmap_ptom(((vaddr_t)&pde[PDIR_SLOT_PTE + 3]) - KERNBASE), 844 xpmap_ptom_masked(addr) | PG_k | PG_V); 845 xpq_flush_queue(); 846 } 847 #endif 848 849 /* Now we can safely reclaim space taken by old tables */ 850 851 __PRINTK(("unpin old PGD\n")); 852 /* Unpin old PGD */ 853 xpq_queue_unpin_table(xpmap_ptom_masked(old_pgd - KERNBASE)); 854 /* Mark old tables RW */ 855 page = old_pgd; 856 addr = (paddr_t) pde[pl2_pi(page)] & PG_FRAME; 857 addr = xpmap_mtop(addr); 858 pte = (pd_entry_t *) ((u_long)addr + KERNBASE); 859 pte += pl1_pi(page); 860 __PRINTK(("*pde %#" PRIxPADDR " addr %#" PRIxPADDR " pte %#lx\n", 861 pde[pl2_pi(page)], addr, (long)pte)); 862 while (page < old_pgd + (old_count * PAGE_SIZE) && page < map_end) { 863 addr = xpmap_ptom(((u_long) pte) - KERNBASE); 864 XENPRINTK(("addr %#" PRIxPADDR " pte %#lx " 865 "*pte %#" PRIxPADDR "\n", 866 addr, (long)pte, *pte)); 867 xpq_queue_pte_update(addr, *pte | PG_RW); 868 page += PAGE_SIZE; 869 /* 870 * Our ptes are contiguous 871 * so it's safe to just "++" here 872 */ 873 pte++; 874 } 875 xpq_flush_queue(); 876 } 877 878 879 /* 880 * Bootstrap helper functions 881 */ 882 883 /* 884 * Mark a page readonly 885 * XXX: assuming vaddr = paddr + KERNBASE 886 */ 887 888 static void 889 xen_bt_set_readonly (vaddr_t page) 890 { 891 pt_entry_t entry; 892 893 entry = xpmap_ptom_masked(page - KERNBASE); 894 entry |= PG_k | PG_V; 895 896 HYPERVISOR_update_va_mapping (page, entry, UVMF_INVLPG); 897 } 898 899 #ifdef __x86_64__ 900 void 901 xen_set_user_pgd(paddr_t page) 902 { 903 struct mmuext_op op; 904 int s = splvm(); 905 906 xpq_flush_queue(); 907 op.cmd = MMUEXT_NEW_USER_BASEPTR; 908 op.arg1.mfn = xpmap_phys_to_machine_mapping[page >> PAGE_SHIFT]; 909 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 910 panic("xen_set_user_pgd: failed to install new user page" 911 " directory %#" PRIxPADDR, page); 912 splx(s); 913 } 914 #endif /* __x86_64__ */ 915