1 /* $NetBSD: acpi_cpu_cstate.c,v 1.37 2011/01/30 08:55:52 jruoho Exp $ */ 2 3 /*- 4 * Copyright (c) 2010 Jukka Ruohonen <jruohonen@iki.fi> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: acpi_cpu_cstate.c,v 1.37 2011/01/30 08:55:52 jruoho Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/cpu.h> 34 #include <sys/device.h> 35 #include <sys/evcnt.h> 36 #include <sys/kernel.h> 37 #include <sys/once.h> 38 #include <sys/mutex.h> 39 #include <sys/timetc.h> 40 41 #include <dev/acpi/acpireg.h> 42 #include <dev/acpi/acpivar.h> 43 #include <dev/acpi/acpi_cpu.h> 44 #include <dev/acpi/acpi_timer.h> 45 46 #include <machine/acpi_machdep.h> 47 48 #define _COMPONENT ACPI_BUS_COMPONENT 49 ACPI_MODULE_NAME ("acpi_cpu_cstate") 50 51 static void acpicpu_cstate_attach_print(struct acpicpu_softc *); 52 static void acpicpu_cstate_attach_evcnt(struct acpicpu_softc *); 53 static void acpicpu_cstate_detach_evcnt(struct acpicpu_softc *); 54 static ACPI_STATUS acpicpu_cstate_cst(struct acpicpu_softc *); 55 static ACPI_STATUS acpicpu_cstate_cst_add(struct acpicpu_softc *, 56 ACPI_OBJECT *); 57 static void acpicpu_cstate_cst_bios(void); 58 static void acpicpu_cstate_memset(struct acpicpu_softc *); 59 static void acpicpu_cstate_fadt(struct acpicpu_softc *); 60 static void acpicpu_cstate_quirks(struct acpicpu_softc *); 61 static int acpicpu_cstate_latency(struct acpicpu_softc *); 62 static bool acpicpu_cstate_bm_check(void); 63 static void acpicpu_cstate_idle_enter(struct acpicpu_softc *,int); 64 65 extern struct acpicpu_softc **acpicpu_sc; 66 67 /* 68 * XXX: The local APIC timer (as well as TSC) is typically stopped in C3. 69 * For now, we cannot but disable C3. But there appears to be timer- 70 * related interrupt issues also in C2. The only entirely safe option 71 * at the moment is to use C1. 72 */ 73 #ifdef ACPICPU_ENABLE_C3 74 static int cs_state_max = ACPI_STATE_C3; 75 #else 76 static int cs_state_max = ACPI_STATE_C1; 77 #endif 78 79 void 80 acpicpu_cstate_attach(device_t self) 81 { 82 struct acpicpu_softc *sc = device_private(self); 83 ACPI_STATUS rv; 84 85 /* 86 * Either use the preferred _CST or resort to FADT. 87 */ 88 rv = acpicpu_cstate_cst(sc); 89 90 switch (rv) { 91 92 case AE_OK: 93 acpicpu_cstate_cst_bios(); 94 break; 95 96 default: 97 sc->sc_flags |= ACPICPU_FLAG_C_FADT; 98 acpicpu_cstate_fadt(sc); 99 break; 100 } 101 102 sc->sc_flags |= ACPICPU_FLAG_C; 103 104 acpicpu_cstate_quirks(sc); 105 acpicpu_cstate_attach_evcnt(sc); 106 acpicpu_cstate_attach_print(sc); 107 } 108 109 void 110 acpicpu_cstate_attach_print(struct acpicpu_softc *sc) 111 { 112 struct acpicpu_cstate *cs; 113 static bool once = false; 114 const char *str; 115 int i; 116 117 if (once != false) 118 return; 119 120 for (i = 0; i < ACPI_C_STATE_COUNT; i++) { 121 122 cs = &sc->sc_cstate[i]; 123 124 if (cs->cs_method == 0) 125 continue; 126 127 switch (cs->cs_method) { 128 129 case ACPICPU_C_STATE_HALT: 130 str = "HLT"; 131 break; 132 133 case ACPICPU_C_STATE_FFH: 134 str = "FFH"; 135 break; 136 137 case ACPICPU_C_STATE_SYSIO: 138 str = "I/O"; 139 break; 140 141 default: 142 panic("NOTREACHED"); 143 } 144 145 aprint_verbose_dev(sc->sc_dev, "C%d: %3s, " 146 "lat %3u us, pow %5u mW, flags 0x%02x\n", i, str, 147 cs->cs_latency, cs->cs_power, cs->cs_flags); 148 } 149 150 once = true; 151 } 152 153 static void 154 acpicpu_cstate_attach_evcnt(struct acpicpu_softc *sc) 155 { 156 struct acpicpu_cstate *cs; 157 const char *str; 158 int i; 159 160 for (i = 0; i < ACPI_C_STATE_COUNT; i++) { 161 162 cs = &sc->sc_cstate[i]; 163 164 if (cs->cs_method == 0) 165 continue; 166 167 str = "HALT"; 168 169 if (cs->cs_method == ACPICPU_C_STATE_FFH) 170 str = "MWAIT"; 171 172 if (cs->cs_method == ACPICPU_C_STATE_SYSIO) 173 str = "I/O"; 174 175 (void)snprintf(cs->cs_name, sizeof(cs->cs_name), 176 "C%d (%s)", i, str); 177 178 evcnt_attach_dynamic(&cs->cs_evcnt, EVCNT_TYPE_MISC, 179 NULL, device_xname(sc->sc_dev), cs->cs_name); 180 } 181 } 182 183 int 184 acpicpu_cstate_detach(device_t self) 185 { 186 struct acpicpu_softc *sc = device_private(self); 187 static ONCE_DECL(once_detach); 188 int rv; 189 190 rv = RUN_ONCE(&once_detach, acpicpu_md_idle_stop); 191 192 if (rv != 0) 193 return rv; 194 195 sc->sc_flags &= ~ACPICPU_FLAG_C; 196 acpicpu_cstate_detach_evcnt(sc); 197 198 return 0; 199 } 200 201 static void 202 acpicpu_cstate_detach_evcnt(struct acpicpu_softc *sc) 203 { 204 struct acpicpu_cstate *cs; 205 int i; 206 207 for (i = 0; i < ACPI_C_STATE_COUNT; i++) { 208 209 cs = &sc->sc_cstate[i]; 210 211 if (cs->cs_method != 0) 212 evcnt_detach(&cs->cs_evcnt); 213 } 214 } 215 216 void 217 acpicpu_cstate_start(device_t self) 218 { 219 struct acpicpu_softc *sc = device_private(self); 220 221 (void)acpicpu_md_idle_start(sc); 222 } 223 224 bool 225 acpicpu_cstate_suspend(device_t self) 226 { 227 return true; 228 } 229 230 bool 231 acpicpu_cstate_resume(device_t self) 232 { 233 static const ACPI_OSD_EXEC_CALLBACK func = acpicpu_cstate_callback; 234 struct acpicpu_softc *sc = device_private(self); 235 236 if ((sc->sc_flags & ACPICPU_FLAG_C_FADT) == 0) 237 (void)AcpiOsExecute(OSL_NOTIFY_HANDLER, func, sc->sc_dev); 238 239 return true; 240 } 241 242 void 243 acpicpu_cstate_callback(void *aux) 244 { 245 struct acpicpu_softc *sc; 246 device_t self = aux; 247 248 sc = device_private(self); 249 250 if ((sc->sc_flags & ACPICPU_FLAG_C_FADT) != 0) 251 return; 252 253 mutex_enter(&sc->sc_mtx); 254 (void)acpicpu_cstate_cst(sc); 255 mutex_exit(&sc->sc_mtx); 256 } 257 258 static ACPI_STATUS 259 acpicpu_cstate_cst(struct acpicpu_softc *sc) 260 { 261 ACPI_OBJECT *elm, *obj; 262 ACPI_BUFFER buf; 263 ACPI_STATUS rv; 264 uint32_t i, n; 265 uint8_t count; 266 267 rv = acpi_eval_struct(sc->sc_node->ad_handle, "_CST", &buf); 268 269 if (ACPI_FAILURE(rv)) 270 return rv; 271 272 obj = buf.Pointer; 273 274 if (obj->Type != ACPI_TYPE_PACKAGE) { 275 rv = AE_TYPE; 276 goto out; 277 } 278 279 if (obj->Package.Count < 2) { 280 rv = AE_LIMIT; 281 goto out; 282 } 283 284 elm = obj->Package.Elements; 285 286 if (elm[0].Type != ACPI_TYPE_INTEGER) { 287 rv = AE_TYPE; 288 goto out; 289 } 290 291 n = elm[0].Integer.Value; 292 293 if (n != obj->Package.Count - 1) { 294 rv = AE_BAD_VALUE; 295 goto out; 296 } 297 298 if (n > ACPI_C_STATES_MAX) { 299 rv = AE_LIMIT; 300 goto out; 301 } 302 303 acpicpu_cstate_memset(sc); 304 305 CTASSERT(ACPI_STATE_C0 == 0 && ACPI_STATE_C1 == 1); 306 CTASSERT(ACPI_STATE_C2 == 2 && ACPI_STATE_C3 == 3); 307 308 for (count = 0, i = 1; i <= n; i++) { 309 310 elm = &obj->Package.Elements[i]; 311 rv = acpicpu_cstate_cst_add(sc, elm); 312 313 if (ACPI_SUCCESS(rv)) 314 count++; 315 } 316 317 rv = (count != 0) ? AE_OK : AE_NOT_EXIST; 318 319 out: 320 if (buf.Pointer != NULL) 321 ACPI_FREE(buf.Pointer); 322 323 return rv; 324 } 325 326 static ACPI_STATUS 327 acpicpu_cstate_cst_add(struct acpicpu_softc *sc, ACPI_OBJECT *elm) 328 { 329 const struct acpicpu_object *ao = &sc->sc_object; 330 struct acpicpu_cstate *cs = sc->sc_cstate; 331 struct acpicpu_cstate state; 332 struct acpicpu_reg *reg; 333 ACPI_STATUS rv = AE_OK; 334 ACPI_OBJECT *obj; 335 uint32_t type; 336 337 (void)memset(&state, 0, sizeof(*cs)); 338 339 state.cs_flags = ACPICPU_FLAG_C_BM_STS; 340 341 if (elm->Type != ACPI_TYPE_PACKAGE) { 342 rv = AE_TYPE; 343 goto out; 344 } 345 346 if (elm->Package.Count != 4) { 347 rv = AE_LIMIT; 348 goto out; 349 } 350 351 /* 352 * Type. 353 */ 354 obj = &elm->Package.Elements[1]; 355 356 if (obj->Type != ACPI_TYPE_INTEGER) { 357 rv = AE_TYPE; 358 goto out; 359 } 360 361 type = obj->Integer.Value; 362 363 if (type < ACPI_STATE_C1 || type > ACPI_STATE_C3) { 364 rv = AE_TYPE; 365 goto out; 366 } 367 368 /* 369 * Latency. 370 */ 371 obj = &elm->Package.Elements[2]; 372 373 if (obj->Type != ACPI_TYPE_INTEGER) { 374 rv = AE_TYPE; 375 goto out; 376 } 377 378 state.cs_latency = obj->Integer.Value; 379 380 /* 381 * Power. 382 */ 383 obj = &elm->Package.Elements[3]; 384 385 if (obj->Type != ACPI_TYPE_INTEGER) { 386 rv = AE_TYPE; 387 goto out; 388 } 389 390 state.cs_power = obj->Integer.Value; 391 392 /* 393 * Register. 394 */ 395 obj = &elm->Package.Elements[0]; 396 397 if (obj->Type != ACPI_TYPE_BUFFER) { 398 rv = AE_TYPE; 399 goto out; 400 } 401 402 CTASSERT(sizeof(struct acpicpu_reg) == 15); 403 404 if (obj->Buffer.Length < sizeof(struct acpicpu_reg)) { 405 rv = AE_LIMIT; 406 goto out; 407 } 408 409 reg = (struct acpicpu_reg *)obj->Buffer.Pointer; 410 411 switch (reg->reg_spaceid) { 412 413 case ACPI_ADR_SPACE_SYSTEM_IO: 414 state.cs_method = ACPICPU_C_STATE_SYSIO; 415 416 if (reg->reg_addr == 0) { 417 rv = AE_AML_ILLEGAL_ADDRESS; 418 goto out; 419 } 420 421 if (reg->reg_bitwidth != 8) { 422 rv = AE_AML_BAD_RESOURCE_LENGTH; 423 goto out; 424 } 425 426 /* 427 * Check only that the address is in the mapped space. 428 * Systems are allowed to change it when operating 429 * with _CST (see ACPI 4.0, pp. 94-95). For instance, 430 * the offset of P_LVL3 may change depending on whether 431 * acpiacad(4) is connected or disconnected. 432 */ 433 if (reg->reg_addr > ao->ao_pblkaddr + ao->ao_pblklen) { 434 rv = AE_BAD_ADDRESS; 435 goto out; 436 } 437 438 state.cs_addr = reg->reg_addr; 439 break; 440 441 case ACPI_ADR_SPACE_FIXED_HARDWARE: 442 state.cs_method = ACPICPU_C_STATE_FFH; 443 444 switch (type) { 445 446 case ACPI_STATE_C1: 447 448 if ((sc->sc_flags & ACPICPU_FLAG_C_FFH) == 0) 449 state.cs_method = ACPICPU_C_STATE_HALT; 450 451 break; 452 453 default: 454 455 if ((sc->sc_flags & ACPICPU_FLAG_C_FFH) == 0) { 456 rv = AE_SUPPORT; 457 goto out; 458 } 459 } 460 461 if (sc->sc_cap != 0) { 462 463 /* 464 * The _CST FFH GAS encoding may contain 465 * additional hints on Intel processors. 466 * Use these to determine whether we can 467 * avoid the bus master activity check. 468 */ 469 if ((reg->reg_accesssize & ACPICPU_PDC_GAS_BM) == 0) 470 state.cs_flags &= ~ACPICPU_FLAG_C_BM_STS; 471 } 472 473 break; 474 475 default: 476 rv = AE_AML_INVALID_SPACE_ID; 477 goto out; 478 } 479 480 if (cs[type].cs_method != 0) { 481 rv = AE_ALREADY_EXISTS; 482 goto out; 483 } 484 485 cs[type].cs_addr = state.cs_addr; 486 cs[type].cs_power = state.cs_power; 487 cs[type].cs_flags = state.cs_flags; 488 cs[type].cs_method = state.cs_method; 489 cs[type].cs_latency = state.cs_latency; 490 491 out: 492 if (ACPI_FAILURE(rv)) 493 aprint_error_dev(sc->sc_dev, "failed to add " 494 "C-state: %s\n", AcpiFormatException(rv)); 495 496 return rv; 497 } 498 499 static void 500 acpicpu_cstate_cst_bios(void) 501 { 502 const uint8_t val = AcpiGbl_FADT.CstControl; 503 const uint32_t addr = AcpiGbl_FADT.SmiCommand; 504 505 if (addr == 0 || val == 0) 506 return; 507 508 (void)AcpiOsWritePort(addr, val, 8); 509 } 510 511 static void 512 acpicpu_cstate_memset(struct acpicpu_softc *sc) 513 { 514 int i = 0; 515 516 while (i < ACPI_C_STATE_COUNT) { 517 518 sc->sc_cstate[i].cs_addr = 0; 519 sc->sc_cstate[i].cs_power = 0; 520 sc->sc_cstate[i].cs_flags = 0; 521 sc->sc_cstate[i].cs_method = 0; 522 sc->sc_cstate[i].cs_latency = 0; 523 524 i++; 525 } 526 } 527 528 static void 529 acpicpu_cstate_fadt(struct acpicpu_softc *sc) 530 { 531 struct acpicpu_cstate *cs = sc->sc_cstate; 532 533 acpicpu_cstate_memset(sc); 534 535 /* 536 * All x86 processors should support C1 (a.k.a. HALT). 537 */ 538 if ((AcpiGbl_FADT.Flags & ACPI_FADT_C1_SUPPORTED) != 0) 539 cs[ACPI_STATE_C1].cs_method = ACPICPU_C_STATE_HALT; 540 541 if (sc->sc_object.ao_pblkaddr == 0) 542 return; 543 544 if (acpi_md_ncpus() > 1) { 545 546 if ((AcpiGbl_FADT.Flags & ACPI_FADT_C2_MP_SUPPORTED) == 0) 547 return; 548 } 549 550 cs[ACPI_STATE_C2].cs_method = ACPICPU_C_STATE_SYSIO; 551 cs[ACPI_STATE_C3].cs_method = ACPICPU_C_STATE_SYSIO; 552 553 cs[ACPI_STATE_C2].cs_latency = AcpiGbl_FADT.C2Latency; 554 cs[ACPI_STATE_C3].cs_latency = AcpiGbl_FADT.C3Latency; 555 556 cs[ACPI_STATE_C2].cs_addr = sc->sc_object.ao_pblkaddr + 4; 557 cs[ACPI_STATE_C3].cs_addr = sc->sc_object.ao_pblkaddr + 5; 558 559 /* 560 * The P_BLK length should always be 6. If it 561 * is not, reduce functionality accordingly. 562 */ 563 if (sc->sc_object.ao_pblklen < 5) 564 cs[ACPI_STATE_C2].cs_method = 0; 565 566 if (sc->sc_object.ao_pblklen < 6) 567 cs[ACPI_STATE_C3].cs_method = 0; 568 569 /* 570 * Sanity check the latency levels in FADT. 571 * Values above the thresholds are used to 572 * inform that C-states are not supported. 573 */ 574 CTASSERT(ACPICPU_C_C2_LATENCY_MAX == 100); 575 CTASSERT(ACPICPU_C_C3_LATENCY_MAX == 1000); 576 577 if (AcpiGbl_FADT.C2Latency > ACPICPU_C_C2_LATENCY_MAX) 578 cs[ACPI_STATE_C2].cs_method = 0; 579 580 if (AcpiGbl_FADT.C3Latency > ACPICPU_C_C3_LATENCY_MAX) 581 cs[ACPI_STATE_C3].cs_method = 0; 582 } 583 584 static void 585 acpicpu_cstate_quirks(struct acpicpu_softc *sc) 586 { 587 const uint32_t reg = AcpiGbl_FADT.Pm2ControlBlock; 588 const uint32_t len = AcpiGbl_FADT.Pm2ControlLength; 589 590 /* 591 * Disable C3 for PIIX4. 592 */ 593 if ((sc->sc_flags & ACPICPU_FLAG_PIIX4) != 0) { 594 sc->sc_cstate[ACPI_STATE_C3].cs_method = 0; 595 return; 596 } 597 598 /* 599 * Check bus master arbitration. If ARB_DIS 600 * is not available, processor caches must be 601 * flushed before C3 (ACPI 4.0, section 8.2). 602 */ 603 if (reg != 0 && len != 0) { 604 sc->sc_flags |= ACPICPU_FLAG_C_ARB; 605 return; 606 } 607 608 /* 609 * Disable C3 entirely if WBINVD is not present. 610 */ 611 if ((AcpiGbl_FADT.Flags & ACPI_FADT_WBINVD) == 0) 612 sc->sc_cstate[ACPI_STATE_C3].cs_method = 0; 613 else { 614 /* 615 * If WBINVD is present and functioning properly, 616 * flush all processor caches before entering C3. 617 */ 618 if ((AcpiGbl_FADT.Flags & ACPI_FADT_WBINVD_FLUSH) == 0) 619 sc->sc_flags &= ~ACPICPU_FLAG_C_BM; 620 else 621 sc->sc_cstate[ACPI_STATE_C3].cs_method = 0; 622 } 623 } 624 625 static int 626 acpicpu_cstate_latency(struct acpicpu_softc *sc) 627 { 628 static const uint32_t cs_factor = 3; 629 struct acpicpu_cstate *cs; 630 int i; 631 632 for (i = cs_state_max; i > 0; i--) { 633 634 cs = &sc->sc_cstate[i]; 635 636 if (__predict_false(cs->cs_method == 0)) 637 continue; 638 639 /* 640 * Choose a state if we have previously slept 641 * longer than the worst case latency of the 642 * state times an arbitrary multiplier. 643 */ 644 if (sc->sc_cstate_sleep > cs->cs_latency * cs_factor) 645 return i; 646 } 647 648 return ACPI_STATE_C1; 649 } 650 651 /* 652 * The main idle loop. 653 */ 654 void 655 acpicpu_cstate_idle(void) 656 { 657 struct cpu_info *ci = curcpu(); 658 struct acpicpu_softc *sc; 659 int state; 660 661 acpi_md_OsDisableInterrupt(); 662 663 if (__predict_false(ci->ci_want_resched != 0)) 664 goto out; 665 666 KASSERT(acpicpu_sc != NULL); 667 KASSERT(ci->ci_acpiid < maxcpus); 668 669 sc = acpicpu_sc[ci->ci_acpiid]; 670 671 if (__predict_false(sc == NULL)) 672 goto out; 673 674 KASSERT(ci->ci_ilevel == IPL_NONE); 675 KASSERT((sc->sc_flags & ACPICPU_FLAG_C) != 0); 676 677 if (__predict_false(sc->sc_cold != false)) 678 goto out; 679 680 if (__predict_false(mutex_tryenter(&sc->sc_mtx) == 0)) 681 goto out; 682 683 mutex_exit(&sc->sc_mtx); 684 state = acpicpu_cstate_latency(sc); 685 686 /* 687 * Apply AMD C1E quirk. 688 */ 689 if ((sc->sc_flags & ACPICPU_FLAG_C_C1E) != 0) 690 acpicpu_md_quirks_c1e(); 691 692 /* 693 * Check for bus master activity. Note that particularly usb(4) 694 * causes high activity, which may prevent the use of C3 states. 695 */ 696 if ((sc->sc_cstate[state].cs_flags & ACPICPU_FLAG_C_BM_STS) != 0) { 697 698 if (acpicpu_cstate_bm_check() != false) 699 state--; 700 701 if (__predict_false(sc->sc_cstate[state].cs_method == 0)) 702 state = ACPI_STATE_C1; 703 } 704 705 KASSERT(state != ACPI_STATE_C0); 706 707 if (state != ACPI_STATE_C3) { 708 acpicpu_cstate_idle_enter(sc, state); 709 return; 710 } 711 712 /* 713 * On all recent (Intel) CPUs caches are shared 714 * by CPUs and bus master control is required to 715 * keep these coherent while in C3. Flushing the 716 * CPU caches is only the last resort. 717 */ 718 if ((sc->sc_flags & ACPICPU_FLAG_C_BM) == 0) 719 ACPI_FLUSH_CPU_CACHE(); 720 721 /* 722 * Allow the bus master to request that any given 723 * CPU should return immediately to C0 from C3. 724 */ 725 if ((sc->sc_flags & ACPICPU_FLAG_C_BM) != 0) 726 (void)AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 1); 727 728 /* 729 * It may be necessary to disable bus master arbitration 730 * to ensure that bus master cycles do not occur while 731 * sleeping in C3 (see ACPI 4.0, section 8.1.4). 732 */ 733 if ((sc->sc_flags & ACPICPU_FLAG_C_ARB) != 0) 734 (void)AcpiWriteBitRegister(ACPI_BITREG_ARB_DISABLE, 1); 735 736 acpicpu_cstate_idle_enter(sc, state); 737 738 /* 739 * Disable bus master wake and re-enable the arbiter. 740 */ 741 if ((sc->sc_flags & ACPICPU_FLAG_C_BM) != 0) 742 (void)AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 0); 743 744 if ((sc->sc_flags & ACPICPU_FLAG_C_ARB) != 0) 745 (void)AcpiWriteBitRegister(ACPI_BITREG_ARB_DISABLE, 0); 746 747 return; 748 749 out: 750 acpi_md_OsEnableInterrupt(); 751 } 752 753 static void 754 acpicpu_cstate_idle_enter(struct acpicpu_softc *sc, int state) 755 { 756 struct acpicpu_cstate *cs = &sc->sc_cstate[state]; 757 uint32_t end, start, val; 758 759 start = acpitimer_read_fast(NULL); 760 761 switch (cs->cs_method) { 762 763 case ACPICPU_C_STATE_FFH: 764 case ACPICPU_C_STATE_HALT: 765 acpicpu_md_idle_enter(cs->cs_method, state); 766 break; 767 768 case ACPICPU_C_STATE_SYSIO: 769 (void)AcpiOsReadPort(cs->cs_addr, &val, 8); 770 break; 771 } 772 773 acpi_md_OsEnableInterrupt(); 774 775 cs->cs_evcnt.ev_count++; 776 end = acpitimer_read_fast(NULL); 777 sc->sc_cstate_sleep = hztoms(acpitimer_delta(end, start)) * 1000; 778 } 779 780 static bool 781 acpicpu_cstate_bm_check(void) 782 { 783 uint32_t val = 0; 784 ACPI_STATUS rv; 785 786 rv = AcpiReadBitRegister(ACPI_BITREG_BUS_MASTER_STATUS, &val); 787 788 if (ACPI_FAILURE(rv) || val == 0) 789 return false; 790 791 (void)AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_STATUS, 1); 792 793 return true; 794 } 795