1 /* $NetBSD: if_nireg.h,v 1.3 2001/08/20 12:20:07 wiz Exp $ */ 2 /* 3 * Copyright (c) 1988 Regents of the University of California. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to Berkeley by 7 * Chris Torek. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the University of 20 * California, Berkeley and its contributors. 21 * 4. Neither the name of the University nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * @(#)nireg.h 7.3 (Berkeley) 6/28/90 38 */ 39 40 /* 41 * Registers for the DEBNA and DEBNK Ethernet interfaces 42 * (DEC calls these Network Interfaces, hence nireg.h) 43 */ 44 45 /* 46 * this seems to be intended to be more general, but I have no details, 47 * so it goes here for now 48 * 49 * BI Vax Port (BVP) stuff first: 50 */ 51 #ifdef notdef 52 struct bvpregs { 53 u_long p_pcr; /* port control register */ 54 u_long p_psr; /* port status register */ 55 u_long p_per; /* port error register */ 56 u_long p_pdr; /* port data register */ 57 }; 58 59 /* 60 * BI node space registers 61 */ 62 struct ni_regs { 63 struct biiregs ni_bi; /* BIIC registers, except GPRs */ 64 struct bvpregs ni_tkp; /* tk50 port control via BIIC GPRs */ 65 u_long ni_xxx[64]; /* unused */ 66 u_long ni_rxcd; /* receive console data */ 67 struct bvpregs ni_nip; /* NI port control via BCI3 GPRs */ 68 u_long ni_pudr; /* power-up diagnostic register */ 69 }; 70 #endif 71 72 #define NI_PCR 0x204 73 #define NI_PSR 0x208 74 #define NI_PER 0x20c 75 #define NI_PDR 0x210 76 #define NI_PUDR 0x204 77 78 /* bits in PCR */ 79 #define PCR_OWN 0x80 80 #define PCR_MFREEQ 0x000 81 #define PCR_DFREEQ 0x100 82 #define PCR_RFREEQ 0x200 83 #define PCR_IFREEQ 0x300 84 #define PCR_CMDQ0 PCR_MFREEQ 85 #define PCR_CMDQ1 PCR_DFREEQ 86 #define PCR_CMDQ2 PCR_RFREEQ 87 #define PCR_CMDQ3 PCR_IFREEQ 88 #define PCR_RESTART 11 89 #define PCR_FREEQNE 7 90 #define PCR_CMDQNE 6 91 #define PCR_SHUTDOWN 4 92 #define PCR_ENABLE 2 93 #define PCR_INIT 1 94 95 /* bits in PSR */ 96 #define PSR_OWN 0x80000000 97 #define PSR_STATE 0x00070000 98 #define PSR_STOPPED 0x00060000 99 #define PSR_ENABLED 0x00040000 100 #define PSR_INITED 0x00020000 101 #define PSR_UNDEF 0x00010000 102 #define PSR_RSQ 0x00000080 103 #define PSR_ERR 0x00000040 104 105 /* 106 * The DEBNx uses a very weird (set of) structure(s) to communicate 107 * with something as simple as an ethernet controller. This is not 108 * very different to the way communication is done over CI with disks. 109 */ 110 111 /* Message packet */ 112 struct ni_msg { 113 u_int32_t nm_forw; 114 u_int32_t nm_back; 115 u_int32_t nm_pad1; 116 u_int8_t nm_pad2; 117 u_int8_t nm_status; 118 u_int8_t nm_opcode; 119 u_int8_t nm_pad3; 120 u_int16_t nm_len; 121 u_int8_t nm_opcode2; 122 u_int8_t nm_status2; 123 u_int32_t nm_pad4; 124 u_int8_t nm_text[128]; 125 }; 126 127 /* Datagram packet */ 128 struct ni_dg { 129 u_int32_t nd_forw; 130 u_int32_t nd_back; 131 u_int32_t nd_pad1; 132 u_int8_t nd_pad2; 133 u_int8_t nd_status; 134 u_int8_t nd_opcode; 135 u_int8_t nd_pad3; 136 u_int16_t nd_len; 137 u_int16_t nd_status2; 138 u_int32_t nd_cmdref; 139 u_int32_t nd_ptdbidx; 140 struct { 141 u_int16_t _offset; 142 u_int16_t _len; 143 u_int16_t _index; 144 u_int16_t _key; 145 } bufs[NTXFRAGS]; 146 }; 147 148 #define NIDG_CHAIN 0x8000 149 150 /* NI parameter block */ 151 struct ni_param { 152 u_int8_t np_dpa[8]; 153 u_int8_t np_apa[8]; 154 u_int8_t np_lsa[8]; 155 u_int8_t np_bvc[8]; 156 u_int16_t np_curaddr; 157 u_int16_t np_maxaddr; 158 u_int16_t np_curptt; 159 u_int16_t np_maxptt; 160 u_int16_t np_curfq; 161 u_int16_t np_maxfq; 162 u_int32_t np_sid; 163 u_int32_t np_mop; 164 u_int32_t np_flags; 165 u_int32_t np_rcto; 166 u_int32_t np_xmto; 167 }; 168 169 #define NP_ECT 0x01 170 #define NP_PAD 0x02 171 #define NP_BOO 0x04 172 #define NP_CAR 0x08 173 #define NP_ILP 0x10 174 #define NP_ELP 0x20 175 #define NP_DCRC 0x40 176 #define NP_THRU 0x80 177 178 /* Protocol type definition block */ 179 struct ni_ptdb { 180 u_int16_t np_type; /* Protocol type */ 181 u_int8_t np_fque; /* Free queue */ 182 u_int8_t np_flags; /* See below */ 183 u_int32_t np_index; /* protocol type index */ 184 u_int16_t np_adrlen; /* # of multicast addresses */ 185 u_int16_t np_802; /* for IEEE 802 packets */ 186 u_int8_t np_mcast[16][8];/* Multicast (direct match) array */ 187 }; 188 189 #define PTDB_PROMISC 0x08 190 #define PTDB_802 0x10 191 #define PTDB_BDC 0x20 192 #define PTDB_UNKN 0x40 193 #define PTDB_AMC 0x80 194 195 /* Buffer descriptor */ 196 struct ni_bbd { 197 u_int16_t nb_status; /* Offset, valid etc */ 198 u_int16_t nb_key; 199 u_int32_t nb_len; /* Buffer length */ 200 u_int32_t nb_pte; /* start (vax) PTE for this buffer */ 201 u_int32_t nb_pad; 202 }; 203 #define NIBD_OFFSET 0x1ff 204 #define NIBD_VALID 0x8000 205 206 207 /* Free Queue Block */ 208 struct ni_fqb { 209 u_int32_t nf_mlen; 210 u_int32_t nf_mpad; 211 u_int32_t nf_mforw; 212 u_int32_t nf_mback; 213 u_int32_t nf_dlen; 214 u_int32_t nf_dpad; 215 u_int32_t nf_dforw; 216 u_int32_t nf_dback; 217 u_int32_t nf_rlen; 218 u_int32_t nf_rpad; 219 u_int32_t nf_rforw; 220 u_int32_t nf_rback; 221 u_int32_t nf_ilen; 222 u_int32_t nf_ipad; 223 u_int32_t nf_iforw; 224 u_int32_t nf_iback; 225 }; 226 227 /* DEBNx specific part of Generic VAX Port */ 228 struct ni_pqb { 229 u_int16_t np_veclvl; /* Interrupt vector + level */ 230 u_int16_t np_node; /* Where to interrupt */ 231 u_int32_t np_freeq; 232 u_int32_t np_vfqb; /* Free queue block pointer */ 233 u_int32_t np_pad1[39]; 234 u_int32_t np_bvplvl; 235 u_int32_t np_vpqb; /* Virtual address of Generic PQB */ 236 u_int32_t np_vbdt; /* Virtual address of descriptors */ 237 u_int32_t np_nbdr; /* Number of descriptors */ 238 u_int32_t np_spt; /* System Page Table */ 239 u_int32_t np_sptlen; /* System Page Table length */ 240 u_int32_t np_gpt; /* Global Page Table */ 241 u_int32_t np_gptlen; /* Global Page Table length */ 242 u_int32_t np_mask; 243 u_int32_t np_pad2[67]; 244 }; 245 246 /* "Generic VAX Port Control Block" whatever it means */ 247 struct ni_gvppqb { 248 u_int32_t nc_forw0; 249 u_int32_t nc_back0; 250 u_int32_t nc_forw1; 251 u_int32_t nc_back1; 252 u_int32_t nc_forw2; 253 u_int32_t nc_back2; 254 u_int32_t nc_forw3; 255 u_int32_t nc_back3; 256 u_int32_t nc_forwr; 257 u_int32_t nc_backr; 258 struct ni_pqb nc_pqb; /* DEBNx specific part of struct */ 259 }; 260 261 262 /* BVP opcodes, should be somewhere else */ 263 #define BVP_DGRAM 1 264 #define BVP_MSG 2 265 #define BVP_DGRAMI 3 266 #define BVP_DGRAMRX 33 267 #define BVP_MSGRX 34 268 #define BVP_DGRAMIRX 35 269 270 /* NI-specific sub-opcodes */ 271 #define NI_WSYSID 1 272 #define NI_RSYSID 2 273 #define NI_WPARAM 3 274 #define NI_RPARAM 4 275 #define NI_RCCNTR 5 276 #define NI_RDCNTR 6 277 #define NI_STPTDB 7 278 #define NI_CLPTDB 8 279 280 /* bits in ni_pudr */ 281 #define PUDR_TAPE 0x40000000 /* tk50 & assoc logic ok */ 282 #define PUDR_PATCH 0x20000000 /* patch logic ok */ 283 #define PUDR_VRAM 0x10000000 /* DEBNx onboard RAM ok */ 284 #define PUDR_VROM1 0x08000000 /* uVax ROM 1 ok */ /* ? */ 285 #define PUDR_VROM2 0x04000000 /* uVax ROM 2 ok */ 286 #define PUDR_VROM3 0x02000000 /* uVax ROM 3 ok */ 287 #define PUDR_VROM4 0x01000000 /* uVax ROM 4 ok */ 288 #define PUDR_UVAX 0x00800000 /* uVax passes self test */ 289 #define PUDR_BI 0x00400000 /* BIIC and BCI3 chips ok */ 290 #define PUDR_TMR 0x00200000 /* interval timer ok */ 291 #define PUDR_IRQ 0x00100000 /* no IRQ lines stuck */ 292 #define PUDR_NI 0x00080000 /* Ethernet ctlr ok */ 293 #define PUDR_TK50 0x00040000 /* tk50 present */ 294 #define PUDR_PRES 0x00001000 /* tk50 present (again?!) */ 295 #define PUDR_UVINT 0x00000800 /* uVax-to-80186 intr logic ok */ 296 #define PUDR_BUSHD 0x00000400 /* no bus hold errors */ 297 #define PUDR_II32 0x00000200 /* II32 transceivers ok */ 298 #define PUDR_MPSC 0x00000100 /* MPSC logic ok */ 299 #define PUDR_GAP 0x00000080 /* gap-detect logic ok */ 300 #define PUDR_MISC 0x00000040 /* misc. registers ok */ 301 #define PUDR_UNEXP 0x00000020 /* unexpected interrupt trapped */ 302 #define PUDR_80186 0x00000010 /* 80186 ok */ 303 #define PUDR_PATCH2 0x00000008 /* patch logic ok (again) */ 304 #define PUDR_8RAM 0x00000004 /* 80186 RAM ok */ 305 #define PUDR_8ROM2 0x00000002 /* 80186 ROM1 ok */ 306 #define PUDR_8ROM1 0x00000001 /* 80186 ROM2 ok */ 307