1 /* $NetBSD: adv_cardbus.c,v 1.5 2001/11/13 12:51:12 lukem Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * this file was brought from ahc_cardbus.c and adv_pci.c 42 * and modified by YAMAMOTO Takashi. 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: adv_cardbus.c,v 1.5 2001/11/13 12:51:12 lukem Exp $"); 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/malloc.h> 51 #include <sys/kernel.h> 52 #include <sys/queue.h> 53 #include <sys/device.h> 54 55 #include <machine/bus.h> 56 #include <machine/intr.h> 57 58 #include <dev/scsipi/scsi_all.h> 59 #include <dev/scsipi/scsipi_all.h> 60 #include <dev/scsipi/scsiconf.h> 61 62 #include <dev/pci/pcireg.h> 63 #include <dev/pci/pcidevs.h> 64 65 #include <dev/cardbus/cardbusvar.h> 66 #include <dev/cardbus/cardbusdevs.h> 67 68 #include <dev/ic/advlib.h> 69 #include <dev/ic/adv.h> 70 71 #define ADV_CARDBUS_IOBA CARDBUS_BASE0_REG 72 #define ADV_CARDBUS_MMBA CARDBUS_BASE1_REG 73 74 #define ADV_CARDBUS_DEBUG 75 #define ADV_CARDBUS_ALLOW_MEMIO 76 77 #define DEVNAME(sc) sc->sc_dev.dv_xname 78 79 struct adv_cardbus_softc { 80 struct asc_softc sc_adv; /* real ADV */ 81 82 /* CardBus-specific goo. */ 83 cardbus_devfunc_t sc_ct; /* our CardBus devfuncs */ 84 int sc_intrline; /* our interrupt line */ 85 cardbustag_t sc_tag; 86 87 int sc_cbenable; /* what CardBus access type to enable */ 88 int sc_csr; /* CSR bits */ 89 bus_size_t sc_size; 90 }; 91 92 int adv_cardbus_match __P((struct device *, struct cfdata *, void *)); 93 void adv_cardbus_attach __P((struct device *, struct device *, void *)); 94 int adv_cardbus_detach __P((struct device *, int)); 95 96 struct cfattach adv_cardbus_ca = { 97 sizeof(struct adv_cardbus_softc), adv_cardbus_match, adv_cardbus_attach, 98 adv_cardbus_detach 99 }; 100 101 int 102 adv_cardbus_match(parent, match, aux) 103 struct device *parent; 104 struct cfdata *match; 105 void *aux; 106 { 107 struct cardbus_attach_args *ca = aux; 108 109 if (CARDBUS_VENDOR(ca->ca_id) == CARDBUS_VENDOR_ADVSYS && 110 CARDBUS_PRODUCT(ca->ca_id) == CARDBUS_PRODUCT_ADVSYS_ULTRA) 111 return (1); 112 113 return (0); 114 } 115 116 void 117 adv_cardbus_attach(parent, self, aux) 118 struct device *parent, *self; 119 void *aux; 120 { 121 struct cardbus_attach_args *ca = aux; 122 struct adv_cardbus_softc *csc = (void *) self; 123 struct asc_softc *sc = &csc->sc_adv; 124 cardbus_devfunc_t ct = ca->ca_ct; 125 cardbus_chipset_tag_t cc = ct->ct_cc; 126 cardbus_function_tag_t cf = ct->ct_cf; 127 bus_space_tag_t iot; 128 bus_space_handle_t ioh; 129 pcireg_t reg; 130 u_int8_t latency = 0x20; 131 132 sc->sc_flags = 0; 133 134 if (PCI_VENDOR(ca->ca_id) == PCI_VENDOR_ADVSYS) { 135 switch (PCI_PRODUCT(ca->ca_id)) { 136 case PCI_PRODUCT_ADVSYS_1200A: 137 printf(": AdvanSys ASC1200A SCSI adapter\n"); 138 latency = 0; 139 break; 140 141 case PCI_PRODUCT_ADVSYS_1200B: 142 printf(": AdvanSys ASC1200B SCSI adapter\n"); 143 latency = 0; 144 break; 145 146 case PCI_PRODUCT_ADVSYS_ULTRA: 147 switch (PCI_REVISION(ca->ca_class)) { 148 case ASC_PCI_REVISION_3050: 149 printf(": AdvanSys ABP-9xxUA SCSI adapter\n"); 150 break; 151 152 case ASC_PCI_REVISION_3150: 153 printf(": AdvanSys ABP-9xxU SCSI adapter\n"); 154 break; 155 } 156 break; 157 158 default: 159 printf(": unknown model!\n"); 160 return; 161 } 162 } 163 164 csc->sc_ct = ct; 165 csc->sc_tag = ca->ca_tag; 166 csc->sc_intrline = ca->ca_intrline; 167 csc->sc_cbenable = 0; 168 169 /* 170 * Map the device. 171 */ 172 csc->sc_csr = PCI_COMMAND_MASTER_ENABLE; 173 174 #ifdef ADV_CARDBUS_ALLOW_MEMIO 175 if (Cardbus_mapreg_map(csc->sc_ct, ADV_CARDBUS_MMBA, 176 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 177 &iot, &ioh, NULL, &csc->sc_size) == 0) { 178 #ifdef ADV_CARDBUS_DEBUG 179 printf("%s: memio enabled\n", DEVNAME(sc)); 180 #endif 181 csc->sc_cbenable = CARDBUS_MEM_ENABLE; 182 csc->sc_csr |= PCI_COMMAND_MEM_ENABLE; 183 } else 184 #endif 185 if (Cardbus_mapreg_map(csc->sc_ct, ADV_CARDBUS_IOBA, 186 PCI_MAPREG_TYPE_IO, 0, &iot, &ioh, NULL, &csc->sc_size) == 0) { 187 #ifdef ADV_CARDBUS_DEBUG 188 printf("%s: io enabled\n", DEVNAME(sc)); 189 #endif 190 csc->sc_cbenable = CARDBUS_IO_ENABLE; 191 csc->sc_csr |= PCI_COMMAND_IO_ENABLE; 192 } else { 193 printf("%s: unable to map device registers\n", 194 DEVNAME(sc)); 195 return; 196 } 197 198 /* Make sure the right access type is on the CardBus bridge. */ 199 (*ct->ct_cf->cardbus_ctrl)(cc, csc->sc_cbenable); 200 (*ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_BM_ENABLE); 201 202 /* Enable the appropriate bits in the PCI CSR. */ 203 reg = cardbus_conf_read(cc, cf, ca->ca_tag, PCI_COMMAND_STATUS_REG); 204 reg &= ~(PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE); 205 reg |= csc->sc_csr; 206 cardbus_conf_write(cc, cf, ca->ca_tag, PCI_COMMAND_STATUS_REG, reg); 207 208 /* 209 * Make sure the latency timer is set to some reasonable 210 * value. 211 */ 212 reg = cardbus_conf_read(cc, cf, ca->ca_tag, PCI_BHLC_REG); 213 if (PCI_LATTIMER(reg) < latency) { 214 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 215 reg |= (latency << PCI_LATTIMER_SHIFT); 216 cardbus_conf_write(cc, cf, ca->ca_tag, PCI_BHLC_REG, reg); 217 } 218 219 ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_HALT); 220 ASC_SET_CHIP_STATUS(iot, ioh, 0); 221 222 sc->sc_iot = iot; 223 sc->sc_ioh = ioh; 224 sc->sc_dmat = ca->ca_dmat; 225 sc->pci_device_id = ca->ca_id; 226 sc->bus_type = ASC_IS_PCI; 227 sc->chip_version = ASC_GET_CHIP_VER_NO(iot, ioh); 228 229 /* 230 * Initialize the board 231 */ 232 if (adv_init(sc)) { 233 printf("adv_init failed\n"); 234 return; 235 } 236 237 /* 238 * Establish the interrupt. 239 */ 240 sc->sc_ih = cardbus_intr_establish(cc, cf, ca->ca_intrline, IPL_BIO, 241 adv_intr, sc); 242 if (sc->sc_ih == NULL) { 243 printf("%s: unable to establish interrupt at %d\n", 244 DEVNAME(sc), ca->ca_intrline); 245 return; 246 } 247 printf("%s: interrupting at %d\n", DEVNAME(sc), ca->ca_intrline); 248 249 /* 250 * Attach. 251 */ 252 adv_attach(sc); 253 } 254 255 int 256 adv_cardbus_detach(self, flags) 257 struct device *self; 258 int flags; 259 { 260 struct adv_cardbus_softc *csc = (void*)self; 261 struct asc_softc *sc = &csc->sc_adv; 262 263 int rv; 264 265 rv = adv_detach(sc, flags); 266 if (rv) 267 return rv; 268 269 if (sc->sc_ih) { 270 cardbus_intr_disestablish(csc->sc_ct->ct_cc, 271 csc->sc_ct->ct_cf, sc->sc_ih); 272 sc->sc_ih = 0; 273 } 274 275 if (csc->sc_cbenable) { 276 #ifdef ADV_CARDBUS_ALLOW_MEMIO 277 if (csc->sc_cbenable == CARDBUS_MEM_ENABLE) { 278 Cardbus_mapreg_unmap(csc->sc_ct, ADV_CARDBUS_MMBA, 279 sc->sc_iot, sc->sc_ioh, csc->sc_size); 280 } else { 281 #endif 282 Cardbus_mapreg_unmap(csc->sc_ct, ADV_CARDBUS_IOBA, 283 sc->sc_iot, sc->sc_ioh, csc->sc_size); 284 #ifdef ADV_CARDBUS_ALLOW_MEMIO 285 } 286 #endif 287 csc->sc_cbenable = 0; 288 } 289 290 return 0; 291 } 292