1 /* $NetBSD: cardbus.c,v 1.107 2010/03/04 22:37:38 dyoung Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 25 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: cardbus.c,v 1.107 2010/03/04 22:37:38 dyoung Exp $"); 31 32 #include "opt_cardbus.h" 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/device.h> 37 #include <sys/malloc.h> 38 #include <sys/kernel.h> 39 #include <sys/syslog.h> 40 #include <sys/proc.h> 41 #include <sys/reboot.h> /* for AB_* needed by bootverbose */ 42 43 #include <sys/bus.h> 44 45 #include <dev/cardbus/cardbusvar.h> 46 #include <dev/pci/pcidevs.h> 47 48 #include <dev/cardbus/cardbus_exrom.h> 49 50 #include <dev/pci/pcivar.h> /* XXX */ 51 #include <dev/pci/pcireg.h> /* XXX */ 52 53 #include <dev/pcmcia/pcmciareg.h> 54 55 #include "locators.h" 56 57 #if defined CARDBUS_DEBUG 58 #define STATIC 59 #define DPRINTF(a) printf a 60 #else 61 #define STATIC static 62 #define DPRINTF(a) 63 #endif 64 65 66 STATIC void cardbusattach(device_t, device_t, void *); 67 STATIC int cardbusdetach(device_t, int); 68 STATIC int cardbusmatch(device_t, cfdata_t, void *); 69 int cardbus_rescan(device_t, const char *, const int *); 70 void cardbus_childdetached(device_t, device_t); 71 static int cardbusprint(void *, const char *); 72 73 typedef void (*tuple_decode_func)(u_int8_t*, int, void*); 74 75 static int decode_tuples(u_int8_t *, int, tuple_decode_func, void*); 76 #ifdef CARDBUS_DEBUG 77 static void print_tuple(u_int8_t*, int, void*); 78 #endif 79 80 static int cardbus_read_tuples(struct cardbus_attach_args *, 81 pcireg_t, u_int8_t *, size_t); 82 83 static void enable_function(struct cardbus_softc *, int, int); 84 static void disable_function(struct cardbus_softc *, int); 85 86 static bool cardbus_child_register(device_t); 87 88 CFATTACH_DECL3_NEW(cardbus, sizeof(struct cardbus_softc), 89 cardbusmatch, cardbusattach, cardbusdetach, NULL, 90 cardbus_rescan, cardbus_childdetached, DVF_DETACH_SHUTDOWN); 91 92 #ifndef __NetBSD_Version__ 93 struct cfdriver cardbus_cd = { 94 NULL, "cardbus", DV_DULL 95 }; 96 #endif 97 98 99 STATIC int 100 cardbusmatch(device_t parent, cfdata_t cf, void *aux) 101 { 102 103 return (1); 104 } 105 106 STATIC void 107 cardbusattach(device_t parent, device_t self, void *aux) 108 { 109 struct cardbus_softc *sc = device_private(self); 110 struct cbslot_attach_args *cba = aux; 111 112 sc->sc_dev = self; 113 114 sc->sc_bus = cba->cba_bus; 115 sc->sc_intrline = cba->cba_intrline; 116 sc->sc_cacheline = cba->cba_cacheline; 117 sc->sc_max_lattimer = MIN(0xf8, cba->cba_max_lattimer); 118 119 aprint_naive("\n"); 120 aprint_normal(": bus %d", sc->sc_bus); 121 if (bootverbose) 122 aprint_normal(" cacheline 0x%x, lattimer 0x%x", 123 sc->sc_cacheline, sc->sc_max_lattimer); 124 aprint_normal("\n"); 125 126 sc->sc_iot = cba->cba_iot; /* CardBus I/O space tag */ 127 sc->sc_memt = cba->cba_memt; /* CardBus MEM space tag */ 128 sc->sc_dmat = cba->cba_dmat; /* DMA tag */ 129 sc->sc_cc = cba->cba_cc; 130 sc->sc_cf = cba->cba_cf; 131 132 sc->sc_rbus_iot = cba->cba_rbus_iot; 133 sc->sc_rbus_memt = cba->cba_rbus_memt; 134 135 if (!pmf_device_register(self, NULL, NULL)) 136 aprint_error_dev(self, "couldn't establish power handler\n"); 137 } 138 139 STATIC int 140 cardbusdetach(device_t self, int flags) 141 { 142 int rc; 143 144 if ((rc = config_detach_children(self, flags)) != 0) 145 return rc; 146 147 pmf_device_deregister(self); 148 return 0; 149 } 150 151 static int 152 cardbus_read_tuples(struct cardbus_attach_args *ca, pcireg_t cis_ptr, 153 u_int8_t *tuples, size_t len) 154 { 155 struct cardbus_softc *sc = ca->ca_ct->ct_sc; 156 cardbus_chipset_tag_t cc = ca->ca_ct->ct_cc; 157 cardbus_function_tag_t cf = ca->ca_ct->ct_cf; 158 pcitag_t tag = ca->ca_tag; 159 pcireg_t command; 160 bus_space_tag_t bar_tag; 161 bus_space_handle_t bar_memh; 162 bus_size_t bar_size; 163 bus_addr_t bar_addr; 164 pcireg_t reg; 165 int found = 0; 166 int cardbus_space = cis_ptr & CARDBUS_CIS_ASIMASK; 167 int i, j; 168 169 memset(tuples, 0, len); 170 171 cis_ptr = cis_ptr & CARDBUS_CIS_ADDRMASK; 172 173 switch (cardbus_space) { 174 case CARDBUS_CIS_ASI_TUPLE: 175 DPRINTF(("%s: reading CIS data from configuration space\n", 176 device_xname(sc->sc_dev))); 177 for (i = cis_ptr, j = 0; i < 0xff; i += 4) { 178 u_int32_t e = (*cf->cardbus_conf_read)(cc, tag, i); 179 tuples[j] = 0xff & e; 180 e >>= 8; 181 tuples[j + 1] = 0xff & e; 182 e >>= 8; 183 tuples[j + 2] = 0xff & e; 184 e >>= 8; 185 tuples[j + 3] = 0xff & e; 186 j += 4; 187 } 188 found++; 189 break; 190 191 case CARDBUS_CIS_ASI_BAR0: 192 case CARDBUS_CIS_ASI_BAR1: 193 case CARDBUS_CIS_ASI_BAR2: 194 case CARDBUS_CIS_ASI_BAR3: 195 case CARDBUS_CIS_ASI_BAR4: 196 case CARDBUS_CIS_ASI_BAR5: 197 case CARDBUS_CIS_ASI_ROM: 198 if (cardbus_space == CARDBUS_CIS_ASI_ROM) { 199 reg = CARDBUS_ROM_REG; 200 DPRINTF(("%s: reading CIS data from ROM\n", 201 device_xname(sc->sc_dev))); 202 } else { 203 reg = CARDBUS_CIS_ASI_BAR(cardbus_space); 204 DPRINTF(("%s: reading CIS data from BAR%d\n", 205 device_xname(sc->sc_dev), cardbus_space - 1)); 206 } 207 208 /* 209 * XXX zero register so mapreg_map doesn't get confused by old 210 * contents. 211 */ 212 cardbus_conf_write(cc, cf, tag, reg, 0); 213 if (Cardbus_mapreg_map(ca->ca_ct, reg, 214 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 215 0, &bar_tag, &bar_memh, &bar_addr, &bar_size)) { 216 aprint_error_dev(sc->sc_dev, "failed to map memory\n"); 217 return (1); 218 } 219 aprint_debug_dev(sc->sc_dev, "mapped %ju bytes at 0x%jx\n", 220 (uintmax_t)bar_size, (uintmax_t)bar_addr); 221 222 if (cardbus_space == CARDBUS_CIS_ASI_ROM) { 223 pcireg_t exrom; 224 int save; 225 struct cardbus_rom_image_head rom_image; 226 struct cardbus_rom_image *p; 227 228 save = splhigh(); 229 /* enable rom address decoder */ 230 exrom = cardbus_conf_read(cc, cf, tag, reg); 231 cardbus_conf_write(cc, cf, tag, reg, exrom | 1); 232 233 command = cardbus_conf_read(cc, cf, tag, 234 PCI_COMMAND_STATUS_REG); 235 cardbus_conf_write(cc, cf, tag, 236 PCI_COMMAND_STATUS_REG, 237 command | PCI_COMMAND_MEM_ENABLE); 238 239 if (cardbus_read_exrom(bar_tag, bar_memh, &rom_image)) 240 goto out; 241 242 SIMPLEQ_FOREACH(p, &rom_image, next) { 243 if (p->rom_image == 244 CARDBUS_CIS_ASI_ROM_IMAGE(cis_ptr)) { 245 bus_space_read_region_1(p->romt, 246 p->romh, CARDBUS_CIS_ADDR(cis_ptr), 247 tuples, MIN(p->image_size, len)); 248 found++; 249 break; 250 } 251 } 252 while ((p = SIMPLEQ_FIRST(&rom_image)) != NULL) { 253 SIMPLEQ_REMOVE_HEAD(&rom_image, next); 254 free(p, M_DEVBUF); 255 } 256 out: 257 exrom = cardbus_conf_read(cc, cf, tag, reg); 258 cardbus_conf_write(cc, cf, tag, reg, exrom & ~1); 259 splx(save); 260 } else { 261 command = cardbus_conf_read(cc, cf, tag, 262 PCI_COMMAND_STATUS_REG); 263 cardbus_conf_write(cc, cf, tag, 264 PCI_COMMAND_STATUS_REG, 265 command | PCI_COMMAND_MEM_ENABLE); 266 /* XXX byte order? */ 267 bus_space_read_region_1(bar_tag, bar_memh, 268 cis_ptr, tuples, 269 MIN(bar_size - MIN(bar_size, cis_ptr), len)); 270 found++; 271 } 272 command = cardbus_conf_read(cc, cf, tag, 273 PCI_COMMAND_STATUS_REG); 274 cardbus_conf_write(cc, cf, tag, PCI_COMMAND_STATUS_REG, 275 command & ~PCI_COMMAND_MEM_ENABLE); 276 cardbus_conf_write(cc, cf, tag, reg, 0); 277 278 Cardbus_mapreg_unmap(ca->ca_ct, reg, bar_tag, bar_memh, 279 bar_size); 280 break; 281 282 #ifdef DIAGNOSTIC 283 default: 284 panic("%s: bad CIS space (%d)", device_xname(sc->sc_dev), 285 cardbus_space); 286 #endif 287 } 288 return (!found); 289 } 290 291 static void 292 parse_tuple(u_int8_t *tuple, int len, void *data) 293 { 294 struct cardbus_cis_info *cis = data; 295 char *p; 296 int i, bar_index; 297 298 switch (tuple[0]) { 299 case PCMCIA_CISTPL_MANFID: 300 if (tuple[1] != 4) { 301 DPRINTF(("%s: wrong length manufacturer id (%d)\n", 302 __func__, tuple[1])); 303 break; 304 } 305 cis->manufacturer = tuple[2] | (tuple[3] << 8); 306 cis->product = tuple[4] | (tuple[5] << 8); 307 break; 308 309 case PCMCIA_CISTPL_VERS_1: 310 memcpy(cis->cis1_info_buf, tuple + 2, tuple[1]); 311 i = 0; 312 p = cis->cis1_info_buf + 2; 313 while (i < 314 sizeof(cis->cis1_info) / sizeof(cis->cis1_info[0])) { 315 if (p >= cis->cis1_info_buf + tuple[1] || *p == '\xff') 316 break; 317 cis->cis1_info[i++] = p; 318 while (*p != '\0' && *p != '\xff') 319 p++; 320 if (*p == '\0') 321 p++; 322 } 323 break; 324 325 case PCMCIA_CISTPL_BAR: 326 if (tuple[1] != 6) { 327 DPRINTF(("%s: BAR with short length (%d)\n", 328 __func__, tuple[1])); 329 break; 330 } 331 bar_index = tuple[2] & 7; 332 if (bar_index == 0) { 333 DPRINTF(("%s: invalid ASI in BAR tuple\n", __func__)); 334 break; 335 } 336 bar_index--; 337 cis->bar[bar_index].flags = tuple[2]; 338 cis->bar[bar_index].size = 339 (tuple[4] << 0) | 340 (tuple[5] << 8) | 341 (tuple[6] << 16) | 342 (tuple[7] << 24); 343 break; 344 345 case PCMCIA_CISTPL_FUNCID: 346 cis->funcid = tuple[2]; 347 break; 348 349 case PCMCIA_CISTPL_FUNCE: 350 switch (cis->funcid) { 351 case PCMCIA_FUNCTION_SERIAL: 352 if (tuple[1] >= 2 && 353 /* XXX PCMCIA_TPLFE_TYPE_SERIAL_??? */ 354 tuple[2] == 0) { 355 cis->funce.serial.uart_type = tuple[3] & 0x1f; 356 cis->funce.serial.uart_present = 1; 357 } 358 break; 359 360 case PCMCIA_FUNCTION_NETWORK: 361 if (tuple[1] >= 8 && 362 tuple[2] == PCMCIA_TPLFE_TYPE_LAN_NID) { 363 if (tuple[3] > 364 sizeof(cis->funce.network.netid)) { 365 DPRINTF(("%s: unknown network id type " 366 "(len = %d)\n", 367 __func__, tuple[3])); 368 } else { 369 cis->funce.network.netid_present = 1; 370 memcpy(cis->funce.network.netid, 371 tuple + 4, tuple[3]); 372 } 373 } 374 break; 375 } 376 break; 377 } 378 } 379 380 /* 381 * int cardbus_attach_card(struct cardbus_softc *sc) 382 * 383 * This function attaches the card on the slot: turns on power, 384 * reads and analyses tuple, sets configuration index. 385 * 386 * This function returns the number of recognised device functions. 387 * If no functions are recognised, return 0. 388 */ 389 int 390 cardbus_attach_card(struct cardbus_softc *sc) 391 { 392 cardbus_chipset_tag_t cc; 393 cardbus_function_tag_t cf; 394 int cdstatus; 395 static int wildcard[CARDBUSCF_NLOCS] = { 396 CARDBUSCF_FUNCTION_DEFAULT 397 }; 398 399 cc = sc->sc_cc; 400 cf = sc->sc_cf; 401 402 DPRINTF(("cardbus_attach_card: cb%d start\n", 403 device_unit(sc->sc_dev))); 404 405 /* inspect initial voltage */ 406 if ((cdstatus = (*cf->cardbus_ctrl)(cc, CARDBUS_CD)) == 0) { 407 DPRINTF(("%s: no CardBus card on cb%d\n", __func__, 408 device_unit(sc->sc_dev))); 409 return (0); 410 } 411 412 device_pmf_driver_set_child_register(sc->sc_dev, cardbus_child_register); 413 cardbus_rescan(sc->sc_dev, "cardbus", wildcard); 414 return (1); /* XXX */ 415 } 416 417 int 418 cardbus_rescan(device_t self, const char *ifattr, 419 const int *locators) 420 { 421 struct cardbus_softc *sc = device_private(self); 422 cardbus_chipset_tag_t cc; 423 cardbus_function_tag_t cf; 424 pcitag_t tag; 425 pcireg_t id, class, cis_ptr; 426 pcireg_t bhlc, icr, lattimer; 427 int cdstatus; 428 int function, nfunction; 429 device_t csc; 430 cardbus_devfunc_t ct; 431 432 cc = sc->sc_cc; 433 cf = sc->sc_cf; 434 435 /* inspect initial voltage */ 436 if ((cdstatus = (*cf->cardbus_ctrl)(cc, CARDBUS_CD)) == 0) { 437 DPRINTF(("%s: no CardBus card on cb%d\n", __func__, 438 device_unit(sc->sc_dev))); 439 return (0); 440 } 441 442 /* 443 * XXX use fake function 8 to keep power on during whole 444 * configuration. 445 */ 446 enable_function(sc, cdstatus, 8); 447 function = 0; 448 449 tag = cardbus_make_tag(cc, cf, sc->sc_bus, function); 450 451 /* 452 * Wait until power comes up. Maxmum 500 ms. 453 * 454 * XXX What is this for? The bridge driver ought to have waited 455 * XXX already. 456 */ 457 { 458 int i; 459 460 for (i = 0; i < 5; ++i) { 461 id = cardbus_conf_read(cc, cf, tag, PCI_ID_REG); 462 if (id != 0xffffffff && id != 0) { 463 break; 464 } 465 if (cold) { /* before kernel thread invoked */ 466 delay(100 * 1000); 467 } else { /* thread context */ 468 if (tsleep((void *)sc, PCATCH, "cardbus", 469 hz / 10) != EWOULDBLOCK) { 470 break; 471 } 472 } 473 } 474 aprint_debug_dev(self, "id reg valid in %d iterations\n", i); 475 if (i == 5) { 476 return (EIO); 477 } 478 } 479 480 bhlc = cardbus_conf_read(cc, cf, tag, PCI_BHLC_REG); 481 DPRINTF(("%s bhlc 0x%08x -> ", device_xname(sc->sc_dev), bhlc)); 482 nfunction = PCI_HDRTYPE_MULTIFN(bhlc) ? 8 : 1; 483 484 for (function = 0; function < nfunction; function++) { 485 struct cardbus_attach_args ca; 486 int locs[CARDBUSCF_NLOCS]; 487 488 if (locators[CARDBUSCF_FUNCTION] != 489 CARDBUSCF_FUNCTION_DEFAULT && 490 locators[CARDBUSCF_FUNCTION] != function) 491 continue; 492 493 if (sc->sc_funcs[function]) 494 continue; 495 496 tag = cardbus_make_tag(cc, cf, sc->sc_bus, function); 497 498 id = cardbus_conf_read(cc, cf, tag, PCI_ID_REG); 499 class = cardbus_conf_read(cc, cf, tag, PCI_CLASS_REG); 500 cis_ptr = cardbus_conf_read(cc, cf, tag, CARDBUS_CIS_REG); 501 502 /* Invalid vendor ID value? */ 503 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) { 504 continue; 505 } 506 507 DPRINTF(("cardbus_attach_card: " 508 "Vendor 0x%x, Product 0x%x, CIS 0x%x\n", 509 PCI_VENDOR(id), PCI_PRODUCT(id), cis_ptr)); 510 511 enable_function(sc, cdstatus, function); 512 513 /* clean up every BAR */ 514 cardbus_conf_write(cc, cf, tag, PCI_BAR0, 0); 515 cardbus_conf_write(cc, cf, tag, PCI_BAR1, 0); 516 cardbus_conf_write(cc, cf, tag, PCI_BAR2, 0); 517 cardbus_conf_write(cc, cf, tag, PCI_BAR3, 0); 518 cardbus_conf_write(cc, cf, tag, PCI_BAR4, 0); 519 cardbus_conf_write(cc, cf, tag, PCI_BAR5, 0); 520 cardbus_conf_write(cc, cf, tag, CARDBUS_ROM_REG, 0); 521 522 /* set initial latency and cacheline size */ 523 bhlc = cardbus_conf_read(cc, cf, tag, PCI_BHLC_REG); 524 icr = cardbus_conf_read(cc, cf, tag, PCI_INTERRUPT_REG); 525 DPRINTF(("%s func%d icr 0x%08x bhlc 0x%08x -> ", 526 device_xname(sc->sc_dev), function, icr, bhlc)); 527 bhlc &= ~(PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT); 528 bhlc |= (sc->sc_cacheline & PCI_CACHELINE_MASK) << 529 PCI_CACHELINE_SHIFT; 530 /* 531 * Set the initial value of the Latency Timer. 532 * 533 * While a PCI device owns the bus, its Latency 534 * Timer counts down bus cycles from its initial 535 * value to 0. Minimum Grant tells for how long 536 * the device wants to own the bus once it gets 537 * access, in units of 250ns. 538 * 539 * On a 33 MHz bus, there are 8 cycles per 250ns. 540 * So I multiply the Minimum Grant by 8 to find 541 * out the initial value of the Latency Timer. 542 * 543 * Avoid setting a Latency Timer less than 0x10, 544 * since the old code did not do that. 545 */ 546 lattimer = 547 MIN(sc->sc_max_lattimer, MAX(0x10, 8 * PCI_MIN_GNT(icr))); 548 if (PCI_LATTIMER(bhlc) < lattimer) { 549 bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 550 bhlc |= (lattimer << PCI_LATTIMER_SHIFT); 551 } 552 553 cardbus_conf_write(cc, cf, tag, PCI_BHLC_REG, bhlc); 554 bhlc = cardbus_conf_read(cc, cf, tag, PCI_BHLC_REG); 555 DPRINTF(("0x%08x\n", bhlc)); 556 557 /* 558 * We need to allocate the ct here, since we might 559 * need it when reading the CIS 560 */ 561 if ((ct = malloc(sizeof(struct cardbus_devfunc), 562 M_DEVBUF, M_NOWAIT)) == NULL) { 563 panic("no room for cardbus_tag"); 564 } 565 566 ct->ct_bhlc = bhlc; 567 ct->ct_cc = sc->sc_cc; 568 ct->ct_cf = sc->sc_cf; 569 ct->ct_bus = sc->sc_bus; 570 ct->ct_func = function; 571 ct->ct_sc = sc; 572 sc->sc_funcs[function] = ct; 573 574 memset(&ca, 0, sizeof(ca)); 575 576 ca.ca_ct = ct; 577 578 ca.ca_iot = sc->sc_iot; 579 ca.ca_memt = sc->sc_memt; 580 ca.ca_dmat = sc->sc_dmat; 581 582 ca.ca_rbus_iot = sc->sc_rbus_iot; 583 ca.ca_rbus_memt= sc->sc_rbus_memt; 584 585 ca.ca_tag = tag; 586 ca.ca_bus = sc->sc_bus; 587 ca.ca_function = function; 588 ca.ca_id = id; 589 ca.ca_class = class; 590 591 ca.ca_intrline = sc->sc_intrline; 592 593 if (cis_ptr != 0) { 594 #define TUPLESIZE 2048 595 u_int8_t *tuple = malloc(TUPLESIZE, M_DEVBUF, M_WAITOK); 596 if (cardbus_read_tuples(&ca, cis_ptr, 597 tuple, TUPLESIZE)) { 598 printf("cardbus_attach_card: " 599 "failed to read CIS\n"); 600 } else { 601 #ifdef CARDBUS_DEBUG 602 decode_tuples(tuple, TUPLESIZE, 603 print_tuple, NULL); 604 #endif 605 decode_tuples(tuple, TUPLESIZE, 606 parse_tuple, &ca.ca_cis); 607 } 608 free(tuple, M_DEVBUF); 609 } 610 611 locs[CARDBUSCF_FUNCTION] = function; 612 613 if ((csc = config_found_sm_loc(sc->sc_dev, "cardbus", locs, 614 &ca, cardbusprint, config_stdsubmatch)) == NULL) { 615 /* do not match */ 616 disable_function(sc, function); 617 sc->sc_funcs[function] = NULL; 618 free(ct, M_DEVBUF); 619 } else { 620 /* found */ 621 ct->ct_device = csc; 622 } 623 } 624 /* 625 * XXX power down pseudo function 8 (this will power down the card 626 * if no functions were attached). 627 */ 628 disable_function(sc, 8); 629 630 return (0); 631 } 632 633 static int 634 cardbusprint(void *aux, const char *pnp) 635 { 636 struct cardbus_attach_args *ca = aux; 637 char devinfo[256]; 638 int i; 639 640 if (pnp) { 641 pci_devinfo(ca->ca_id, ca->ca_class, 1, devinfo, 642 sizeof(devinfo)); 643 for (i = 0; i < 4; i++) { 644 if (ca->ca_cis.cis1_info[i] == NULL) 645 break; 646 if (i) 647 aprint_normal(", "); 648 aprint_normal("%s", ca->ca_cis.cis1_info[i]); 649 } 650 aprint_verbose("%s(manufacturer 0x%x, product 0x%x)", 651 i ? " " : "", 652 ca->ca_cis.manufacturer, ca->ca_cis.product); 653 aprint_normal(" %s at %s", devinfo, pnp); 654 } 655 aprint_normal(" function %d", ca->ca_function); 656 657 return (UNCONF); 658 } 659 660 /* 661 * void cardbus_detach_card(struct cardbus_softc *sc) 662 * 663 * This function detaches the card on the slot: detach device data 664 * structure and turns off the power. 665 * 666 * This function must not be called under interrupt context. 667 */ 668 void 669 cardbus_detach_card(struct cardbus_softc *sc) 670 { 671 int f; 672 struct cardbus_devfunc *ct; 673 674 for (f = 0; f < 8; f++) { 675 ct = sc->sc_funcs[f]; 676 if (!ct) 677 continue; 678 679 DPRINTF(("%s: detaching %s\n", device_xname(sc->sc_dev), 680 device_xname(ct->ct_device))); 681 /* call device detach function */ 682 683 if (config_detach(ct->ct_device, 0) != 0) { 684 aprint_error_dev(sc->sc_dev, 685 "cannot detach dev %s, function %d\n", 686 device_xname(ct->ct_device), ct->ct_func); 687 } 688 } 689 690 sc->sc_poweron_func = 0; 691 (*sc->sc_cf->cardbus_power)(sc->sc_cc, 692 CARDBUS_VCC_0V | CARDBUS_VPP_0V); 693 } 694 695 void 696 cardbus_childdetached(device_t self, device_t child) 697 { 698 struct cardbus_softc *sc = device_private(self); 699 struct cardbus_devfunc *ct; 700 701 ct = sc->sc_funcs[device_locator(child, CARDBUSCF_FUNCTION)]; 702 KASSERT(ct->ct_device == child); 703 704 sc->sc_poweron_func &= ~(1 << ct->ct_func); 705 sc->sc_funcs[ct->ct_func] = NULL; 706 free(ct, M_DEVBUF); 707 } 708 709 void * 710 Cardbus_intr_establish(cardbus_devfunc_t ct, 711 cardbus_intr_line_t irq, int level, int (*func)(void *), void *arg) 712 { 713 return cardbus_intr_establish(ct->ct_cc, ct->ct_cf, irq, level, func, 714 arg); 715 } 716 717 /* 718 * void *cardbus_intr_establish(cc, cf, irq, level, func, arg) 719 * Interrupt handler of pccard. 720 * args: 721 * cardbus_chipset_tag_t *cc 722 * int irq: 723 */ 724 void * 725 cardbus_intr_establish(cardbus_chipset_tag_t cc, cardbus_function_tag_t cf, 726 cardbus_intr_line_t irq, int level, int (*func)(void *), void *arg) 727 { 728 729 DPRINTF(("- cardbus_intr_establish: irq %d\n", irq)); 730 return ((*cf->cardbus_intr_establish)(cc, irq, level, func, arg)); 731 } 732 733 void 734 Cardbus_intr_disestablish(cardbus_devfunc_t ct, void *handler) 735 { 736 cardbus_intr_disestablish(ct->ct_cc, ct->ct_cf, handler); 737 } 738 739 /* 740 * void cardbus_intr_disestablish(cc, cf, handler) 741 * Interrupt handler of pccard. 742 * args: 743 * cardbus_chipset_tag_t *cc 744 */ 745 void 746 cardbus_intr_disestablish(cardbus_chipset_tag_t cc, cardbus_function_tag_t cf, 747 void *handler) 748 { 749 750 DPRINTF(("- pccard_intr_disestablish\n")); 751 (*cf->cardbus_intr_disestablish)(cc, handler); 752 } 753 754 /* 755 * XXX this should be merged with cardbus_function_{enable,disable}, 756 * but we don't have a ct when these functions are called. 757 */ 758 static void 759 enable_function(struct cardbus_softc *sc, int cdstatus, int function) 760 { 761 762 if (sc->sc_poweron_func == 0) { 763 /* switch to 3V and/or wait for power to stabilize */ 764 if (cdstatus & CARDBUS_3V_CARD) { 765 /* 766 * sc_poweron_func must be substituted before 767 * entering sleep, in order to avoid turn on 768 * power twice. 769 */ 770 sc->sc_poweron_func |= (1 << function); 771 (*sc->sc_cf->cardbus_power)(sc->sc_cc, CARDBUS_VCC_3V); 772 } else { 773 /* No cards other than 3.3V cards. */ 774 return; 775 } 776 (*sc->sc_cf->cardbus_ctrl)(sc->sc_cc, CARDBUS_RESET); 777 } 778 sc->sc_poweron_func |= (1 << function); 779 } 780 781 static void 782 disable_function(struct cardbus_softc *sc, int function) 783 { 784 bool powerdown; 785 cardbus_devfunc_t ct; 786 device_t dv; 787 int i; 788 789 sc->sc_poweron_func &= ~(1 << function); 790 if (sc->sc_poweron_func != 0) 791 return; 792 for (i = 0; i < __arraycount(sc->sc_funcs); i++) { 793 if ((ct = sc->sc_funcs[i]) == NULL) 794 continue; 795 dv = ct->ct_device; 796 if (prop_dictionary_get_bool(device_properties(dv), 797 "pmf-powerdown", &powerdown) && !powerdown) 798 return; 799 } 800 /* power-off because no functions are enabled */ 801 (*sc->sc_cf->cardbus_power)(sc->sc_cc, CARDBUS_VCC_0V); 802 } 803 804 /* 805 * int cardbus_function_enable(struct cardbus_softc *sc, int func) 806 * 807 * This function enables a function on a card. When no power is 808 * applied on the card, power will be applied on it. 809 */ 810 int 811 cardbus_function_enable(struct cardbus_softc *sc, int func) 812 { 813 cardbus_chipset_tag_t cc = sc->sc_cc; 814 cardbus_function_tag_t cf = sc->sc_cf; 815 cardbus_devfunc_t ct; 816 pcireg_t command; 817 pcitag_t tag; 818 819 DPRINTF(("entering cardbus_function_enable... ")); 820 821 /* entering critical area */ 822 823 /* XXX: sc_vold should be used */ 824 enable_function(sc, CARDBUS_3V_CARD, func); 825 826 /* exiting critical area */ 827 828 tag = cardbus_make_tag(cc, cf, sc->sc_bus, func); 829 830 command = cardbus_conf_read(cc, cf, tag, PCI_COMMAND_STATUS_REG); 831 command |= (PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_IO_ENABLE | 832 PCI_COMMAND_MASTER_ENABLE); /* XXX: good guess needed */ 833 834 cardbus_conf_write(cc, cf, tag, PCI_COMMAND_STATUS_REG, command); 835 836 if ((ct = sc->sc_funcs[func]) != NULL) 837 Cardbus_conf_write(ct, tag, PCI_BHLC_REG, ct->ct_bhlc); 838 839 DPRINTF(("%x\n", sc->sc_poweron_func)); 840 841 return (0); 842 } 843 844 /* 845 * int cardbus_function_disable(struct cardbus_softc *, int func) 846 * 847 * This function disable a function on a card. When no functions are 848 * enabled, it turns off the power. 849 */ 850 int 851 cardbus_function_disable(struct cardbus_softc *sc, int func) 852 { 853 854 DPRINTF(("entering cardbus_function_disable... ")); 855 856 disable_function(sc, func); 857 858 return (0); 859 } 860 861 /* 862 * int cardbus_get_capability(cardbus_chipset_tag_t cc, 863 * cardbus_function_tag_t cf, pcitag_t tag, int capid, int *offset, 864 * pcireg_t *value) 865 * 866 * Find the specified PCI capability. 867 */ 868 int 869 cardbus_get_capability(cardbus_chipset_tag_t cc, cardbus_function_tag_t cf, 870 pcitag_t tag, int capid, int *offset, pcireg_t *value) 871 { 872 pcireg_t reg; 873 unsigned int ofs; 874 875 reg = cardbus_conf_read(cc, cf, tag, PCI_COMMAND_STATUS_REG); 876 if (!(reg & PCI_STATUS_CAPLIST_SUPPORT)) 877 return (0); 878 879 ofs = PCI_CAPLIST_PTR(cardbus_conf_read(cc, cf, tag, 880 PCI_CAPLISTPTR_REG)); 881 while (ofs != 0) { 882 #ifdef DIAGNOSTIC 883 if ((ofs & 3) || (ofs < 0x40)) 884 panic("cardbus_get_capability"); 885 #endif 886 reg = cardbus_conf_read(cc, cf, tag, ofs); 887 if (PCI_CAPLIST_CAP(reg) == capid) { 888 if (offset) 889 *offset = ofs; 890 if (value) 891 *value = reg; 892 return (1); 893 } 894 ofs = PCI_CAPLIST_NEXT(reg); 895 } 896 897 return (0); 898 } 899 900 /* 901 * below this line, there are some functions for decoding tuples. 902 * They should go out from this file. 903 */ 904 905 static u_int8_t * 906 decode_tuple(u_int8_t *, u_int8_t *, tuple_decode_func, void *); 907 908 static int 909 decode_tuples(u_int8_t *tuple, int buflen, tuple_decode_func func, void *data) 910 { 911 u_int8_t *tp = tuple; 912 913 if (PCMCIA_CISTPL_LINKTARGET != *tuple) { 914 DPRINTF(("WRONG TUPLE: 0x%x\n", *tuple)); 915 return (0); 916 } 917 918 while ((tp = decode_tuple(tp, tuple + buflen, func, data)) != NULL) 919 ; 920 921 return (1); 922 } 923 924 static u_int8_t * 925 decode_tuple(u_int8_t *tuple, u_int8_t *end, 926 tuple_decode_func func, void *data) 927 { 928 u_int8_t type; 929 u_int8_t len; 930 931 type = tuple[0]; 932 switch (type) { 933 case PCMCIA_CISTPL_NULL: 934 case PCMCIA_CISTPL_END: 935 len = 1; 936 break; 937 default: 938 if (tuple + 2 > end) 939 return (NULL); 940 len = tuple[1] + 2; 941 break; 942 } 943 944 if (tuple + len > end) 945 return (NULL); 946 947 (*func)(tuple, len, data); 948 949 if (type == PCMCIA_CISTPL_END || tuple + len == end) 950 return (NULL); 951 952 return (tuple + len); 953 } 954 955 /* 956 * XXX: this is another reason why this code should be shared with PCI. 957 */ 958 static int 959 cardbus_get_powerstate_int(cardbus_devfunc_t ct, pcitag_t tag, 960 pcireg_t *state, int offset) 961 { 962 pcireg_t value, now; 963 cardbus_chipset_tag_t cc = ct->ct_cc; 964 cardbus_function_tag_t cf = ct->ct_cf; 965 966 value = cardbus_conf_read(cc, cf, tag, offset + PCI_PMCSR); 967 now = value & PCI_PMCSR_STATE_MASK; 968 switch (now) { 969 case PCI_PMCSR_STATE_D0: 970 case PCI_PMCSR_STATE_D1: 971 case PCI_PMCSR_STATE_D2: 972 case PCI_PMCSR_STATE_D3: 973 *state = now; 974 return 0; 975 default: 976 return EINVAL; 977 } 978 } 979 980 int 981 cardbus_get_powerstate(cardbus_devfunc_t ct, pcitag_t tag, pcireg_t *state) 982 { 983 cardbus_chipset_tag_t cc = ct->ct_cc; 984 cardbus_function_tag_t cf = ct->ct_cf; 985 int offset; 986 pcireg_t value; 987 988 if (!cardbus_get_capability(cc, cf, tag, PCI_CAP_PWRMGMT, &offset, &value)) 989 return EOPNOTSUPP; 990 991 return cardbus_get_powerstate_int(ct, tag, state, offset); 992 } 993 994 static int 995 cardbus_set_powerstate_int(cardbus_devfunc_t ct, pcitag_t tag, 996 pcireg_t state, int offset, pcireg_t cap_reg) 997 { 998 cardbus_chipset_tag_t cc = ct->ct_cc; 999 cardbus_function_tag_t cf = ct->ct_cf; 1000 1001 pcireg_t value, cap, now; 1002 1003 KASSERT((offset & 0x3) == 0); 1004 1005 cap = cap_reg >> PCI_PMCR_SHIFT; 1006 value = cardbus_conf_read(cc, cf, tag, offset + PCI_PMCSR); 1007 now = value & PCI_PMCSR_STATE_MASK; 1008 value &= ~PCI_PMCSR_STATE_MASK; 1009 1010 if (now == state) 1011 return 0; 1012 switch (state) { 1013 case PCI_PMCSR_STATE_D0: 1014 break; 1015 case PCI_PMCSR_STATE_D1: 1016 if (now == PCI_PMCSR_STATE_D2 || now == PCI_PMCSR_STATE_D3) { 1017 printf("invalid transition from %d to D1\n", (int)now); 1018 return EINVAL; 1019 } 1020 if (!(cap & PCI_PMCR_D1SUPP)) { 1021 printf("D1 not supported\n"); 1022 return EOPNOTSUPP; 1023 } 1024 break; 1025 case PCI_PMCSR_STATE_D2: 1026 if (now == PCI_PMCSR_STATE_D3) { 1027 printf("invalid transition from %d to D2\n", (int)now); 1028 return EINVAL; 1029 } 1030 if (!(cap & PCI_PMCR_D2SUPP)) { 1031 printf("D2 not supported\n"); 1032 return EOPNOTSUPP; 1033 } 1034 break; 1035 case PCI_PMCSR_STATE_D3: 1036 break; 1037 default: 1038 return EINVAL; 1039 } 1040 value |= state; 1041 cardbus_conf_write(cc, cf, tag, offset + PCI_PMCSR, value); 1042 if (state == PCI_PMCSR_STATE_D3 || now == PCI_PMCSR_STATE_D3) 1043 DELAY(10000); 1044 else if (state == PCI_PMCSR_STATE_D2 || now == PCI_PMCSR_STATE_D2) 1045 DELAY(200); 1046 1047 return 0; 1048 } 1049 1050 int 1051 cardbus_set_powerstate(cardbus_devfunc_t ct, pcitag_t tag, pcireg_t state) 1052 { 1053 cardbus_chipset_tag_t cc = ct->ct_cc; 1054 cardbus_function_tag_t cf = ct->ct_cf; 1055 int offset; 1056 pcireg_t value; 1057 1058 if (!cardbus_get_capability(cc, cf, tag, PCI_CAP_PWRMGMT, &offset, 1059 &value)) 1060 return EOPNOTSUPP; 1061 1062 return cardbus_set_powerstate_int(ct, tag, state, offset, value); 1063 } 1064 1065 #ifdef CARDBUS_DEBUG 1066 static const char *tuple_name(int); 1067 static const char *tuple_names[] = { 1068 "TPL_NULL", "TPL_DEVICE", "Reserved", "Reserved", /* 0-3 */ 1069 "CONFIG_CB", "CFTABLE_ENTRY_CB", "Reserved", "BAR", /* 4-7 */ 1070 "Reserved", "Reserved", "Reserved", "Reserved", /* 8-B */ 1071 "Reserved", "Reserved", "Reserved", "Reserved", /* C-F */ 1072 "CHECKSUM", "LONGLINK_A", "LONGLINK_C", "LINKTARGET", /* 10-13 */ 1073 "NO_LINK", "VERS_1", "ALTSTR", "DEVICE_A", 1074 "JEDEC_C", "JEDEC_A", "CONFIG", "CFTABLE_ENTRY", 1075 "DEVICE_OC", "DEVICE_OA", "DEVICE_GEO", "DEVICE_GEO_A", 1076 "MANFID", "FUNCID", "FUNCE", "SWIL", /* 20-23 */ 1077 "Reserved", "Reserved", "Reserved", "Reserved", /* 24-27 */ 1078 "Reserved", "Reserved", "Reserved", "Reserved", /* 28-2B */ 1079 "Reserved", "Reserved", "Reserved", "Reserved", /* 2C-2F */ 1080 "Reserved", "Reserved", "Reserved", "Reserved", /* 30-33 */ 1081 "Reserved", "Reserved", "Reserved", "Reserved", /* 34-37 */ 1082 "Reserved", "Reserved", "Reserved", "Reserved", /* 38-3B */ 1083 "Reserved", "Reserved", "Reserved", "Reserved", /* 3C-3F */ 1084 "VERS_2", "FORMAT", "GEOMETRY", "BYTEORDER", 1085 "DATE", "BATTERY", "ORG" 1086 }; 1087 #define NAME_LEN(x) (sizeof x / sizeof(x[0])) 1088 1089 static const char * 1090 tuple_name(int type) 1091 { 1092 1093 if (0 <= type && type < NAME_LEN(tuple_names)) { 1094 return (tuple_names[type]); 1095 } else if (type == 0xff) { 1096 return ("END"); 1097 } else { 1098 return ("Reserved"); 1099 } 1100 } 1101 1102 static void 1103 print_tuple(u_int8_t *tuple, int len, void *data) 1104 { 1105 int i; 1106 1107 printf("tuple: %s len %d\n", tuple_name(tuple[0]), len); 1108 1109 for (i = 0; i < len; ++i) { 1110 if (i % 16 == 0) { 1111 printf(" 0x%2x:", i); 1112 } 1113 printf(" %x", tuple[i]); 1114 if (i % 16 == 15) { 1115 printf("\n"); 1116 } 1117 } 1118 if (i % 16 != 0) { 1119 printf("\n"); 1120 } 1121 } 1122 #endif 1123 1124 void 1125 cardbus_conf_capture(cardbus_chipset_tag_t cc, cardbus_function_tag_t cf, 1126 pcitag_t tag, struct cardbus_conf_state *pcs) 1127 { 1128 int off; 1129 1130 for (off = 0; off < 16; off++) 1131 pcs->reg[off] = cardbus_conf_read(cc, cf, tag, (off * 4)); 1132 } 1133 1134 void 1135 cardbus_conf_restore(cardbus_chipset_tag_t cc, cardbus_function_tag_t cf, 1136 pcitag_t tag, struct cardbus_conf_state *pcs) 1137 { 1138 int off; 1139 pcireg_t val; 1140 1141 for (off = 15; off >= 0; off--) { 1142 val = cardbus_conf_read(cc, cf, tag, (off * 4)); 1143 if (val != pcs->reg[off]) 1144 cardbus_conf_write(cc, cf,tag, (off * 4), pcs->reg[off]); 1145 } 1146 } 1147 1148 struct cardbus_child_power { 1149 struct cardbus_conf_state p_cardbusconf; 1150 cardbus_devfunc_t p_ct; 1151 pcitag_t p_tag; 1152 cardbus_chipset_tag_t p_cc; 1153 cardbus_function_tag_t p_cf; 1154 pcireg_t p_pm_cap; 1155 bool p_has_pm; 1156 int p_pm_offset; 1157 }; 1158 1159 static bool 1160 cardbus_child_suspend(device_t dv, const pmf_qual_t *qual) 1161 { 1162 struct cardbus_child_power *priv = device_pmf_bus_private(dv); 1163 1164 cardbus_conf_capture(priv->p_cc, priv->p_cf, priv->p_tag, 1165 &priv->p_cardbusconf); 1166 1167 if (priv->p_has_pm && 1168 cardbus_set_powerstate_int(priv->p_ct, priv->p_tag, 1169 PCI_PMCSR_STATE_D3, priv->p_pm_offset, priv->p_pm_cap)) { 1170 aprint_error_dev(dv, "unsupported state, continuing.\n"); 1171 return false; 1172 } 1173 1174 Cardbus_function_disable(priv->p_ct); 1175 1176 return true; 1177 } 1178 1179 static bool 1180 cardbus_child_resume(device_t dv, const pmf_qual_t *qual) 1181 { 1182 struct cardbus_child_power *priv = device_pmf_bus_private(dv); 1183 1184 Cardbus_function_enable(priv->p_ct); 1185 1186 if (priv->p_has_pm && 1187 cardbus_set_powerstate_int(priv->p_ct, priv->p_tag, 1188 PCI_PMCSR_STATE_D0, priv->p_pm_offset, priv->p_pm_cap)) { 1189 aprint_error_dev(dv, "unsupported state, continuing.\n"); 1190 return false; 1191 } 1192 1193 cardbus_conf_restore(priv->p_cc, priv->p_cf, priv->p_tag, 1194 &priv->p_cardbusconf); 1195 1196 return true; 1197 } 1198 1199 static void 1200 cardbus_child_deregister(device_t dv) 1201 { 1202 struct cardbus_child_power *priv = device_pmf_bus_private(dv); 1203 1204 free(priv, M_DEVBUF); 1205 } 1206 1207 static bool 1208 cardbus_child_register(device_t child) 1209 { 1210 device_t self = device_parent(child); 1211 struct cardbus_softc *sc = device_private(self); 1212 struct cardbus_devfunc *ct; 1213 struct cardbus_child_power *priv; 1214 int off; 1215 pcireg_t reg; 1216 1217 ct = sc->sc_funcs[device_locator(child, CARDBUSCF_FUNCTION)]; 1218 1219 priv = malloc(sizeof(*priv), M_DEVBUF, M_WAITOK); 1220 1221 priv->p_ct = ct; 1222 priv->p_cc = ct->ct_cc; 1223 priv->p_cf = ct->ct_cf; 1224 priv->p_tag = cardbus_make_tag(priv->p_cc, priv->p_cf, ct->ct_bus, 1225 ct->ct_func); 1226 1227 if (cardbus_get_capability(priv->p_cc, priv->p_cf, priv->p_tag, 1228 PCI_CAP_PWRMGMT, &off, ®)) { 1229 priv->p_has_pm = true; 1230 priv->p_pm_offset = off; 1231 priv->p_pm_cap = reg; 1232 } else { 1233 priv->p_has_pm = false; 1234 priv->p_pm_offset = -1; 1235 } 1236 1237 device_pmf_bus_register(child, priv, cardbus_child_suspend, 1238 cardbus_child_resume, 0, cardbus_child_deregister); 1239 1240 return true; 1241 } 1242