1 /* $NetBSD: if_ath_cardbus.c,v 1.42 2010/03/04 22:34:37 dyoung Exp $ */ 2 /* 3 * Copyright (c) 2003 4 * Ichiro FUKUHARA <ichiro@ichiro.org>. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR 20 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 /* 29 * CardBus bus front-end for the AR5001 Wireless LAN 802.11a/b/g CardBus. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: if_ath_cardbus.c,v 1.42 2010/03/04 22:34:37 dyoung Exp $"); 34 35 #include "opt_inet.h" 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/mbuf.h> 40 #include <sys/malloc.h> 41 #include <sys/kernel.h> 42 #include <sys/socket.h> 43 #include <sys/ioctl.h> 44 #include <sys/errno.h> 45 #include <sys/device.h> 46 47 #include <machine/endian.h> 48 49 #include <net/if.h> 50 #include <net/if_dl.h> 51 #include <net/if_media.h> 52 #include <net/if_ether.h> 53 54 #include <net80211/ieee80211_netbsd.h> 55 #include <net80211/ieee80211_var.h> 56 57 #ifdef INET 58 #include <netinet/in.h> 59 #include <netinet/if_inarp.h> 60 #endif 61 62 63 #include <sys/bus.h> 64 #include <sys/intr.h> 65 66 #include <dev/mii/miivar.h> 67 #include <dev/mii/mii_bitbang.h> 68 69 #include <dev/ic/ath_netbsd.h> 70 #include <dev/ic/athvar.h> 71 72 #include <external/isc/atheros_hal/dist/ah.h> 73 74 #include <dev/pci/pcivar.h> 75 #include <dev/pci/pcireg.h> 76 #include <dev/pci/pcidevs.h> 77 78 #include <dev/cardbus/cardbusvar.h> 79 #include <dev/pci/pcidevs.h> 80 81 /* 82 * PCI configuration space registers 83 */ 84 #define ATH_PCI_MMBA 0x10 /* memory mapped base */ 85 86 struct ath_cardbus_softc { 87 struct ath_softc sc_ath; 88 89 /* CardBus-specific goo. */ 90 void *sc_ih; /* interrupt handle */ 91 cardbus_devfunc_t sc_ct; /* our CardBus devfuncs */ 92 pcitag_t sc_tag; /* our CardBus tag */ 93 bus_size_t sc_mapsize; /* the size of mapped bus space region */ 94 95 pcireg_t sc_bar_val; /* value of the BAR */ 96 97 cardbus_intr_line_t sc_intrline; /* interrupt line */ 98 bus_space_tag_t sc_iot; 99 bus_space_handle_t sc_ioh; 100 }; 101 102 int ath_cardbus_match(device_t, cfdata_t, void *); 103 void ath_cardbus_attach(device_t, device_t, void *); 104 int ath_cardbus_detach(device_t, int); 105 106 CFATTACH_DECL_NEW(ath_cardbus, sizeof(struct ath_cardbus_softc), 107 ath_cardbus_match, ath_cardbus_attach, ath_cardbus_detach, NULL); 108 109 void ath_cardbus_setup(struct ath_cardbus_softc *); 110 111 static bool 112 ath_cardbus_suspend(device_t self, const pmf_qual_t *qual) 113 { 114 struct ath_cardbus_softc *csc = device_private(self); 115 116 ath_suspend(&csc->sc_ath); 117 if (csc->sc_ih != NULL) { 118 Cardbus_intr_disestablish(csc->sc_ct, csc->sc_ih); 119 csc->sc_ih = NULL; 120 } 121 return true; 122 } 123 124 static bool 125 ath_cardbus_resume(device_t self, const pmf_qual_t *qual) 126 { 127 struct ath_cardbus_softc *csc = device_private(self); 128 129 csc->sc_ih = Cardbus_intr_establish(csc->sc_ct, 130 csc->sc_intrline, IPL_NET, ath_intr, 131 &csc->sc_ath); 132 133 if (csc->sc_ih == NULL) { 134 aprint_error_dev(self, 135 "unable to establish interrupt\n"); 136 return false; 137 } 138 139 return ath_resume(&csc->sc_ath); 140 } 141 142 int 143 ath_cardbus_match(device_t parent, cfdata_t match, void *aux) 144 { 145 struct cardbus_attach_args *ca = aux; 146 const char *devname; 147 148 devname = ath_hal_probe(PCI_VENDOR(ca->ca_id), PCI_PRODUCT(ca->ca_id)); 149 150 if (devname) 151 return 1; 152 153 return 0; 154 } 155 156 void 157 ath_cardbus_attach(device_t parent, device_t self, void *aux) 158 { 159 struct ath_cardbus_softc *csc = device_private(self); 160 struct ath_softc *sc = &csc->sc_ath; 161 struct cardbus_attach_args *ca = aux; 162 cardbus_devfunc_t ct = ca->ca_ct; 163 bus_addr_t adr; 164 165 sc->sc_dev = self; 166 sc->sc_dmat = ca->ca_dmat; 167 csc->sc_ct = ct; 168 csc->sc_tag = ca->ca_tag; 169 170 aprint_normal("\n"); 171 172 /* 173 * Map the device. 174 */ 175 if (Cardbus_mapreg_map(ct, ATH_PCI_MMBA, PCI_MAPREG_TYPE_MEM, 0, 176 &csc->sc_iot, &csc->sc_ioh, &adr, &csc->sc_mapsize) == 0) { 177 csc->sc_bar_val = adr | PCI_MAPREG_TYPE_MEM; 178 } else { 179 aprint_error_dev(self, "unable to map device registers\n"); 180 return; 181 } 182 183 sc->sc_st = HALTAG(csc->sc_iot); 184 sc->sc_sh = HALHANDLE(csc->sc_ioh); 185 186 /* 187 * Set up the PCI configuration registers. 188 */ 189 ath_cardbus_setup(csc); 190 191 /* Remember which interrupt line. */ 192 csc->sc_intrline = ca->ca_intrline; 193 194 ATH_LOCK_INIT(sc); 195 196 /* 197 * Finish off the attach. 198 */ 199 if (ath_attach(PCI_PRODUCT(ca->ca_id), sc) != 0) 200 return; 201 202 if (pmf_device_register(self, 203 ath_cardbus_suspend, ath_cardbus_resume)) { 204 pmf_class_network_register(self, &sc->sc_if); 205 pmf_device_suspend(self, &sc->sc_qual); 206 } else 207 aprint_error_dev(self, "couldn't establish power handler\n"); 208 } 209 210 int 211 ath_cardbus_detach(device_t self, int flags) 212 { 213 struct ath_cardbus_softc *csc = device_private(self); 214 struct ath_softc *sc = &csc->sc_ath; 215 struct cardbus_devfunc *ct = csc->sc_ct; 216 int rv; 217 218 #if defined(DIAGNOSTIC) 219 if (ct == NULL) 220 panic("%s: data structure lacks", device_xname(sc->sc_dev)); 221 #endif 222 223 rv = ath_detach(sc); 224 if (rv) 225 return (rv); 226 227 pmf_device_deregister(self); 228 229 /* 230 * Unhook the interrupt handler. 231 */ 232 if (csc->sc_ih != NULL) { 233 Cardbus_intr_disestablish(ct, csc->sc_ih); 234 csc->sc_ih = NULL; 235 } 236 237 /* 238 * Release bus space and close window. 239 */ 240 Cardbus_mapreg_unmap(ct, ATH_PCI_MMBA, csc->sc_iot, csc->sc_ioh, 241 csc->sc_mapsize); 242 243 ATH_LOCK_DESTROY(sc); 244 245 return (0); 246 } 247 248 void 249 ath_cardbus_setup(struct ath_cardbus_softc *csc) 250 { 251 cardbus_devfunc_t ct = csc->sc_ct; 252 int rc; 253 pcireg_t reg; 254 255 if ((rc = cardbus_set_powerstate(ct, csc->sc_tag, PCI_PWR_D0)) != 0) 256 aprint_debug("%s: cardbus_set_powerstate %d\n", __func__, rc); 257 258 /* Program the BAR. */ 259 Cardbus_conf_write(ct, csc->sc_tag, ATH_PCI_MMBA, csc->sc_bar_val); 260 261 /* Enable the appropriate bits in the PCI CSR. */ 262 reg = Cardbus_conf_read(ct, csc->sc_tag, 263 PCI_COMMAND_STATUS_REG); 264 reg |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE; 265 Cardbus_conf_write(ct, csc->sc_tag, PCI_COMMAND_STATUS_REG, reg); 266 } 267