1 /* $NetBSD: rbus_ppb.c,v 1.3 2002/05/16 01:01:28 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Michael Richardson <mcr@sandelman.ottawa.on.ca> 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * CardBus front-end for the Intel/Digital DECchip 21152 PCI-PCI bridge 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: rbus_ppb.c,v 1.3 2002/05/16 01:01:28 thorpej Exp $"); 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/mbuf.h> 49 #include <sys/malloc.h> 50 #include <sys/kernel.h> 51 #include <sys/socket.h> 52 #include <sys/ioctl.h> 53 #include <sys/errno.h> 54 #include <sys/device.h> 55 56 #if NRND > 0 57 #include <sys/rnd.h> 58 #endif 59 60 #include <machine/endian.h> 61 62 #include <machine/bus.h> 63 #include <machine/intr.h> 64 65 #include <dev/pci/pcivar.h> 66 #include <dev/pci/pcireg.h> 67 #include <dev/pci/pcidevs.h> 68 #include <dev/pci/ppbreg.h> 69 70 #include <dev/ic/i82365reg.h> 71 #include <dev/ic/i82365var.h> 72 73 #include <dev/pci/pccbbreg.h> 74 #include <dev/pci/pccbbvar.h> 75 76 #include <dev/cardbus/cardbusvar.h> 77 #include <dev/cardbus/cardbusdevs.h> 78 79 #include <i386/pci/pci_addr_fixup.h> 80 #include <i386/pci/pci_bus_fixup.h> 81 #include <i386/pci/pci_intr_fixup.h> 82 #include <i386/pci/pcibios.h> 83 84 struct ppb_softc; 85 86 static int ppb_cardbus_match __P((struct device *, struct cfdata *, void *)); 87 static void ppb_cardbus_attach __P((struct device *, struct device *, void *)); 88 static int ppb_cardbus_detach __P((struct device * self, int flags)); 89 /*static*/ void ppb_cardbus_setup __P((struct ppb_softc * sc)); 90 /*static*/ int ppb_cardbus_enable __P((struct ppb_softc * sc)); 91 /*static*/ void ppb_cardbus_disable __P((struct ppb_softc * sc)); 92 static int ppb_activate __P((struct device *self, enum devact act)); 93 int rppbprint __P((void *aux, const char *pnp)); 94 int rbus_intr_fixup __P((pci_chipset_tag_t pc, int minbus, 95 int maxbus, int line)); 96 void rbus_do_header_fixup __P((pci_chipset_tag_t pc, pcitag_t tag, 97 void *context)); 98 99 static void rbus_pci_phys_allocate __P((pci_chipset_tag_t pc, 100 pcitag_t tag, 101 void *context)); 102 103 static int rbus_do_phys_allocate __P((pci_chipset_tag_t pc, 104 pcitag_t tag, 105 int mapreg, 106 void *ctx, 107 int type, 108 bus_addr_t *addr, 109 bus_size_t size)); 110 111 static void rbus_pci_phys_countspace __P((pci_chipset_tag_t pc, 112 pcitag_t tag, 113 void *context)); 114 115 static int rbus_do_phys_countspace __P((pci_chipset_tag_t pc, 116 pcitag_t tag, 117 int mapreg, 118 void *ctx, 119 int type, 120 bus_addr_t *addr, 121 bus_size_t size)); 122 123 unsigned int rbus_round_up __P((unsigned int size, unsigned int min)); 124 125 126 struct ppb_cardbus_softc { 127 struct device sc_dev; 128 pcitag_t sc_tag; 129 int foo; 130 }; 131 132 struct cfattach rbus_ppb_ca = { 133 sizeof(struct ppb_cardbus_softc), 134 ppb_cardbus_match, 135 ppb_cardbus_attach, 136 ppb_cardbus_detach, 137 ppb_activate 138 }; 139 140 #ifdef CBB_DEBUG 141 int rbus_ppb_debug = 0; /* hack with kdb */ 142 #define DPRINTF(X) if(rbus_ppb_debug) printf X 143 #else 144 #define DPRINTF(X) 145 #endif 146 147 static int 148 ppb_cardbus_match(parent, match, aux) 149 struct device *parent; 150 struct cfdata *match; 151 void *aux; 152 { 153 struct cardbus_attach_args *ca = aux; 154 155 if (CARDBUS_VENDOR(ca->ca_id) == PCI_VENDOR_DEC && 156 CARDBUS_PRODUCT(ca->ca_id) == PCI_PRODUCT_DEC_21152) 157 return (1); 158 159 if(PCI_CLASS(ca->ca_class) == PCI_CLASS_BRIDGE && 160 PCI_SUBCLASS(ca->ca_class) == PCI_SUBCLASS_BRIDGE_PCI) { 161 /* XXX */ 162 printf("recognizing generic bridge chip\n"); 163 } 164 165 return (0); 166 } 167 168 169 int 170 rppbprint(aux, pnp) 171 void *aux; 172 const char *pnp; 173 { 174 struct pcibus_attach_args *pba = aux; 175 176 /* only PCIs can attach to PPBs; easy. */ 177 if (pnp) 178 printf("pci at %s", pnp); 179 printf(" bus %d (rbus)", pba->pba_bus); 180 return (UNCONF); 181 } 182 183 int 184 rbus_intr_fixup(pci_chipset_tag_t pc, 185 int minbus, 186 int maxbus, 187 int line) 188 { 189 pci_device_foreach_min(pc, minbus, 190 maxbus, rbus_do_header_fixup, (void *)&line); 191 return 0; 192 } 193 194 void 195 rbus_do_header_fixup(pc, tag, context) 196 pci_chipset_tag_t pc; 197 pcitag_t tag; 198 void *context; 199 { 200 int pin, irq; 201 int bus, device, function; 202 pcireg_t intr, id; 203 int *pline = (int *)context; 204 int line = *pline; 205 206 pci_decompose_tag(pc, tag, &bus, &device, &function); 207 id = pci_conf_read(pc, tag, PCI_ID_REG); 208 209 intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 210 pin = PCI_INTERRUPT_PIN(intr); 211 irq = PCI_INTERRUPT_LINE(intr); 212 213 #if 0 214 printf("do_header %02x:%02x:%02x pin=%d => line %d\n", 215 bus, device, function, pin, line); 216 #endif 217 218 intr &= ~(PCI_INTERRUPT_LINE_MASK << PCI_INTERRUPT_LINE_SHIFT); 219 intr |= (line << PCI_INTERRUPT_LINE_SHIFT); 220 pci_conf_write(pc, tag, PCI_INTERRUPT_REG, intr); 221 222 } 223 224 /* 225 * This function takes a range of PCI bus numbers and 226 * allocates space for all devices found in this space (the BARs) from 227 * the rbus space maps (I/O and memory). 228 * 229 * It assumes that "rbus" is defined. The whole concept does. 230 * 231 * It uses pci_device_foreach_min() to call rbus_pci_phys_allocate. 232 * This function is mostly stolen from 233 * pci_addr_fixup.c:pciaddr_resource_reserve. 234 * 235 */ 236 struct rbus_pci_addr_fixup_context { 237 struct ppb_cardbus_softc *csc; 238 cardbus_chipset_tag_t ct; 239 struct cardbus_softc *sc; 240 struct cardbus_attach_args *caa; 241 int minbus; 242 int maxbus; 243 bus_size_t *bussize_ioreqs; 244 bus_size_t *bussize_memreqs; 245 rbus_tag_t *iobustags; 246 rbus_tag_t *membustags; 247 }; 248 249 unsigned int 250 rbus_round_up(unsigned int size, unsigned int min) 251 { 252 unsigned int power2; 253 254 if(size == 0) { 255 return 0; 256 } 257 258 power2=min; 259 260 while(power2 < (1 << 31) && 261 power2 < size) { 262 power2 = power2 << 1; 263 } 264 265 return power2; 266 } 267 268 static void 269 rbus_pci_addr_fixup(struct ppb_cardbus_softc *csc, 270 cardbus_chipset_tag_t ct, 271 struct cardbus_softc *sc, 272 pci_chipset_tag_t pc, 273 struct cardbus_attach_args *caa, 274 int minbus, int maxbus) 275 { 276 struct rbus_pci_addr_fixup_context rct; 277 int size, busnum; 278 bus_addr_t start; 279 bus_space_handle_t handle; 280 u_int32_t reg; 281 282 rct.csc=csc; 283 rct.ct=ct; 284 rct.sc=sc; 285 rct.caa=caa; 286 rct.minbus = minbus; 287 rct.maxbus = maxbus; 288 size = sizeof(bus_size_t)*(maxbus+1); 289 rct.bussize_ioreqs = alloca(size); 290 rct.bussize_memreqs = alloca(size); 291 rct.iobustags = alloca(maxbus * sizeof(rbus_tag_t)); 292 rct.membustags = alloca(maxbus * sizeof(rbus_tag_t)); 293 294 bzero(rct.bussize_ioreqs, size); 295 bzero(rct.bussize_memreqs, size); 296 297 printf("%s: sizing buses %d-%d\n", 298 rct.csc->sc_dev.dv_xname, 299 minbus, maxbus); 300 301 pci_device_foreach_min(pc, minbus, maxbus, 302 rbus_pci_phys_countspace, &rct); 303 304 /* 305 * we need to determine amount of address space for each 306 * bus. To do this, we have to roll up amounts and then 307 * we need to divide up the cardbus's extent to allocate 308 * some space to each bus. 309 */ 310 311 for(busnum=maxbus; busnum > minbus; busnum--) { 312 if(pci_bus_parent[busnum] != 0) { 313 if(pci_bus_parent[busnum] < minbus || 314 pci_bus_parent[busnum] >= maxbus) { 315 printf("%s: bus %d has illegal parent %d\n", 316 rct.csc->sc_dev.dv_xname, 317 busnum, pci_bus_parent[busnum]); 318 continue; 319 } 320 321 /* first round amount of space up */ 322 rct.bussize_ioreqs[busnum] = 323 rbus_round_up(rct.bussize_ioreqs[busnum], PPB_IO_MIN); 324 rct.bussize_ioreqs[pci_bus_parent[busnum]] += 325 rct.bussize_ioreqs[busnum]; 326 327 rct.bussize_memreqs[busnum] = 328 rbus_round_up(rct.bussize_memreqs[busnum], PPB_MEM_MIN); 329 rct.bussize_memreqs[pci_bus_parent[busnum]] += 330 rct.bussize_memreqs[busnum]; 331 332 } 333 } 334 335 rct.bussize_ioreqs[minbus] = 336 rbus_round_up(rct.bussize_ioreqs[minbus], 4096); 337 rct.bussize_memreqs[minbus] = 338 rbus_round_up(rct.bussize_memreqs[minbus], 8); 339 340 printf("%s: total needs IO %08lx and MEM %08lx\n", 341 rct.csc->sc_dev.dv_xname, 342 rct.bussize_ioreqs[minbus], rct.bussize_memreqs[minbus]); 343 344 if(!caa->ca_rbus_iot) { 345 panic("no iot bus"); 346 } 347 348 if(rct.bussize_ioreqs[minbus]) { 349 if(rbus_space_alloc(caa->ca_rbus_iot, 0, 350 rct.bussize_ioreqs[minbus], 351 rct.bussize_ioreqs[minbus]-1 /* mask */, 352 rct.bussize_ioreqs[minbus] /* align */, 353 /* flags */ 0, 354 &start, 355 &handle) != 0) { 356 panic("rbus_ppb: can not allocate %ld bytes in IO bus %d\n", 357 rct.bussize_ioreqs[minbus], minbus); 358 } 359 rct.iobustags[minbus]=rbus_new(caa->ca_rbus_iot, 360 start, 361 rct.bussize_ioreqs[minbus], 362 0 /* offset to add to physical address 363 to make processor address */, 364 RBUS_SPACE_DEDICATE); 365 } 366 367 if(rct.bussize_memreqs[minbus]) { 368 if(rbus_space_alloc(caa->ca_rbus_memt, 0, 369 rct.bussize_memreqs[minbus], 370 rct.bussize_memreqs[minbus]-1 /* mask */, 371 rct.bussize_memreqs[minbus] /* align */, 372 /* flags */ 0, 373 &start, 374 &handle) != 0) { 375 panic("%s: can not allocate %ld bytes in MEM bus %d\n", 376 rct.csc->sc_dev.dv_xname, 377 rct.bussize_memreqs[minbus], minbus); 378 } 379 rct.membustags[minbus]=rbus_new(caa->ca_rbus_memt, 380 start, 381 rct.bussize_memreqs[minbus], 382 0 /* offset to add to physical 383 address to make processor 384 address */, 385 RBUS_SPACE_DEDICATE); 386 } 387 388 for(busnum=minbus+1; busnum <= maxbus; busnum++) { 389 int busparent; 390 391 busparent = pci_bus_parent[busnum]; 392 393 printf("%s: bus %d (parent=%d) needs IO %08lx and MEM %08lx\n", 394 rct.csc->sc_dev.dv_xname, 395 busnum, 396 busparent, 397 rct.bussize_ioreqs[busnum], 398 rct.bussize_memreqs[busnum]); 399 400 if(busparent > maxbus) { 401 panic("rbus_ppb: illegal parent"); 402 } 403 404 if(rct.bussize_ioreqs[busnum]) { 405 if(rbus_space_alloc(rct.iobustags[busparent], 406 0, 407 rct.bussize_ioreqs[busnum], 408 rct.bussize_ioreqs[busnum]-1 /*mask */, 409 rct.bussize_ioreqs[busnum] /* align */, 410 /* flags */ 0, 411 &start, 412 &handle) != 0) { 413 panic("rbus_ppb: can not allocate %ld bytes in IO bus %d\n", 414 rct.bussize_ioreqs[busnum], busnum); 415 } 416 rct.iobustags[busnum]=rbus_new(rct.iobustags[busparent], 417 start, 418 rct.bussize_ioreqs[busnum], 419 0 /* offset to add to physical 420 address 421 to make processor address */, 422 RBUS_SPACE_DEDICATE); 423 424 /* program the bridge */ 425 426 /* enable I/O space */ 427 reg = pci_conf_read(pc, pci_bus_tag[busnum], 428 PCI_COMMAND_STATUS_REG); 429 reg |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE; 430 pci_conf_write(pc, pci_bus_tag[busnum], 431 PCI_COMMAND_STATUS_REG, reg); 432 433 /* now init the limit register for I/O */ 434 pci_conf_write(pc, pci_bus_tag[busnum], PPB_REG_IOSTATUS, 435 (((start & 0xf000) >> 8) << PPB_IOBASE_SHIFT) | 436 ((((start + 437 rct.bussize_ioreqs[busnum] + 438 4095) & 0xf000) >> 8) << PPB_IOLIMIT_SHIFT)); 439 } 440 441 if(rct.bussize_memreqs[busnum]) { 442 if(rbus_space_alloc(rct.membustags[busparent], 443 0, 444 rct.bussize_memreqs[busnum] /* size */, 445 rct.bussize_memreqs[busnum]-1 /*mask */, 446 rct.bussize_memreqs[busnum] /* align */, 447 /* flags */ 0, 448 &start, 449 &handle) != 0) { 450 panic("rbus_ppb: can not allocate %ld bytes in MEM bus %d\n", 451 rct.bussize_memreqs[busnum], busnum); 452 } 453 rct.membustags[busnum]=rbus_new(rct.membustags[busparent], 454 start, 455 rct.bussize_memreqs[busnum], 456 0 /* offset to add to physical 457 address to make processor 458 address */, 459 RBUS_SPACE_DEDICATE); 460 461 /* program the bridge */ 462 /* enable memory space */ 463 reg = pci_conf_read(pc, pci_bus_tag[busnum], 464 PCI_COMMAND_STATUS_REG); 465 reg |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 466 pci_conf_write(pc, pci_bus_tag[busnum], 467 PCI_COMMAND_STATUS_REG, reg); 468 469 /* now init the limit register for memory */ 470 pci_conf_write(pc, pci_bus_tag[busnum], PPB_REG_MEM, 471 ((start & PPB_MEM_MASK) 472 >> PPB_MEM_SHIFT) << PPB_MEMBASE_SHIFT | 473 (((start + 474 rct.bussize_memreqs[busnum] + 475 PPB_MEM_MIN-1) >> PPB_MEM_SHIFT) 476 << PPB_MEMLIMIT_SHIFT)); 477 478 /* and set the prefetchable limits as well */ 479 pci_conf_write(pc, pci_bus_tag[busnum], PPB_REG_PREFMEM, 480 ((start & PPB_MEM_MASK) 481 >> PPB_MEM_SHIFT) << PPB_MEMBASE_SHIFT | 482 (((start + 483 rct.bussize_memreqs[busnum] + 484 PPB_MEM_MIN-1) >> PPB_MEM_SHIFT) 485 << PPB_MEMLIMIT_SHIFT)); 486 487 /* pci_conf_print(pc, pci_bus_tag[busnum], NULL); */ 488 } 489 } 490 491 printf("%s: configuring buses %d-%d\n", 492 rct.csc->sc_dev.dv_xname, 493 minbus, maxbus); 494 pci_device_foreach_min(pc, minbus, maxbus, 495 rbus_pci_phys_allocate, &rct); 496 } 497 498 static void 499 rbus_pci_phys_countspace(pc, tag, context) 500 pci_chipset_tag_t pc; 501 pcitag_t tag; 502 void *context; 503 { 504 int bus, device, function; 505 struct rbus_pci_addr_fixup_context *rct = 506 (struct rbus_pci_addr_fixup_context *)context; 507 508 pci_decompose_tag(pc, tag, &bus, &device, &function); 509 510 printf("%s: configuring device %02x:%02x:%02x\n", 511 rct->csc->sc_dev.dv_xname, 512 bus, device, function); 513 514 pciaddr_resource_manage(pc, tag, 515 rbus_do_phys_countspace, context); 516 } 517 518 519 int 520 rbus_do_phys_countspace(pc, tag, mapreg, ctx, type, addr, size) 521 pci_chipset_tag_t pc; 522 pcitag_t tag; 523 void *ctx; 524 int mapreg, type; 525 bus_addr_t *addr; 526 bus_size_t size; 527 { 528 struct rbus_pci_addr_fixup_context *rct = 529 (struct rbus_pci_addr_fixup_context *)ctx; 530 int bus, device, function; 531 532 pci_decompose_tag(pc, tag, &bus, &device, &function); 533 534 if(size > (1<<24)) { 535 printf("%s: skipping huge space request of size=%08x\n", 536 rct->csc->sc_dev.dv_xname, (unsigned int)size); 537 return 0; 538 } 539 540 if(PCI_MAPREG_TYPE(type) == PCI_MAPREG_TYPE_IO) { 541 rct->bussize_ioreqs[bus] += size; 542 } else { 543 rct->bussize_memreqs[bus]+= size; 544 } 545 546 return 0; 547 } 548 549 static void 550 rbus_pci_phys_allocate(pc, tag, context) 551 pci_chipset_tag_t pc; 552 pcitag_t tag; 553 void *context; 554 { 555 int bus, device, function, command; 556 struct rbus_pci_addr_fixup_context *rct = 557 (struct rbus_pci_addr_fixup_context *)context; 558 //cardbus_chipset_tag_t ct = rct->ct; 559 // struct cardbus_softc *sc = rct->sc; 560 561 pci_decompose_tag(pc, tag, &bus, &device, &function); 562 563 printf("%s: configuring device %02x:%02x:%02x\n", 564 rct->csc->sc_dev.dv_xname, 565 bus, device, function); 566 567 pciaddr_resource_manage(pc, tag, 568 rbus_do_phys_allocate, context); 569 570 /* now turn the device's memory and I/O on */ 571 command = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 572 command |= PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE; 573 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, command); 574 } 575 576 int 577 rbus_do_phys_allocate(pc, tag, mapreg, ctx, type, addr, size) 578 pci_chipset_tag_t pc; 579 pcitag_t tag; 580 void *ctx; 581 int mapreg, type; 582 bus_addr_t *addr; 583 bus_size_t size; 584 { 585 struct rbus_pci_addr_fixup_context *rct = 586 (struct rbus_pci_addr_fixup_context *)ctx; 587 cardbus_chipset_tag_t ct = rct->ct; 588 struct cardbus_softc *sc = rct->sc; 589 cardbus_function_t *cf = sc->sc_cf; 590 rbus_tag_t rbustag; 591 bus_space_tag_t bustag; 592 bus_addr_t mask = size -1; 593 bus_addr_t base = 0; 594 bus_space_handle_t handle; 595 int busflags = 0; 596 int flags = 0; 597 char *bustype; 598 int bus, device, function; 599 600 pci_decompose_tag(pc, tag, &bus, &device, &function); 601 602 /* 603 * some devices come up with garbage in them (Tulip?) 604 * we are in charge here, so give them address 605 * space anyway. 606 * 607 * XXX this may be due to no secondary PCI reset!!! 608 */ 609 #if 0 610 if (*addr) { 611 printf("Already allocated space at %08x\n", 612 (unsigned int)*addr); 613 return (0); 614 } 615 #endif 616 617 if(size > (1<<24)) { 618 printf("%s: skipping huge space request of size=%08x\n", 619 rct->csc->sc_dev.dv_xname, (unsigned int)size); 620 return 0; 621 } 622 623 if(PCI_MAPREG_TYPE(type) == PCI_MAPREG_TYPE_IO) { 624 bustag = sc->sc_iot; 625 rbustag = rct->iobustags[bus]; 626 bustype = "io"; 627 } else { 628 bustag = sc->sc_memt; 629 rbustag = rct->membustags[bus]; 630 bustype = "mem"; 631 } 632 633 if((*cf->cardbus_space_alloc)(ct, rbustag, base, size, 634 mask, size, busflags|flags, 635 addr, &handle)) { 636 printf("%s: no available resources (size=%08x) for bar %2d. fixup failed\n", 637 rct->csc->sc_dev.dv_xname, (unsigned int)size, mapreg); 638 639 *addr = 0; 640 pci_conf_write(pc, tag, mapreg, *addr); 641 return (1); 642 } 643 644 printf("%s: alloc %s space of size %08x for %02d:%02d:%02d -> %08x\n", 645 rct->csc->sc_dev.dv_xname, 646 bustype, 647 (unsigned int)size, 648 bus, device, function, (unsigned int)*addr); 649 650 /* write new address to PCI device configuration header */ 651 pci_conf_write(pc, tag, mapreg, *addr); 652 653 /* check */ 654 { 655 DPRINTF(("%s: pci_addr_fixup: ", 656 rct->csc->sc_dev.dv_xname)); 657 #ifdef CBB_DEBUG 658 if(rbus_ppb_debug) { pciaddr_print_devid(pc, tag); } 659 #endif 660 } 661 662 /* double check that the value got inserted correctly */ 663 if (pciaddr_ioaddr(pci_conf_read(pc, tag, mapreg)) != *addr) { 664 pci_conf_write(pc, tag, mapreg, 0); /* clear */ 665 printf("%s: fixup failed. (new address=%#x)\n", 666 rct->csc->sc_dev.dv_xname, 667 (unsigned)*addr); 668 return (1); 669 } 670 671 DPRINTF(("new address 0x%08x\n", 672 (unsigned)*addr)); 673 674 return (0); 675 } 676 677 static void 678 ppb_cardbus_attach(parent, self, aux) 679 struct device *parent, *self; 680 void *aux; 681 { 682 struct ppb_cardbus_softc *csc = (struct ppb_cardbus_softc *) self; 683 struct cardbus_softc *parent_sc = 684 (struct cardbus_softc *) csc->sc_dev.dv_parent; 685 struct cardbus_attach_args *ca = aux; 686 cardbus_devfunc_t ct = ca->ca_ct; 687 cardbus_chipset_tag_t cc = ct->ct_cc; 688 cardbus_function_tag_t cf = ct->ct_cf; 689 struct pccbb_softc *psc = (struct pccbb_softc *)cc; 690 struct pcibus_attach_args pba; 691 char devinfo[256]; 692 pcireg_t busdata; 693 int mybus, rv; 694 u_int16_t pciirq; 695 int minbus, maxbus; 696 697 mybus = ct->ct_bus; 698 pciirq = 0; 699 rv = 0; 700 701 /* shut up compiler */ 702 csc->foo=parent_sc->sc_intrline; 703 704 705 pci_devinfo(ca->ca_id, ca->ca_class, 0, devinfo); 706 printf(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(ca->ca_class)); 707 708 sc->sc_tag = ca->ca_tag; /* XXX cardbustag_t == pcitag_t */ 709 710 busdata = cardbus_conf_read(cc, cf, ca->ca_tag, PPB_REG_BUSINFO); 711 minbus = pcibios_max_bus; 712 713 if (PPB_BUSINFO_SECONDARY(busdata) == 0) { 714 printf("%s: not configured by system firmware calling pci_bus_fixup(%d)\n", 715 self->dv_xname, 0); 716 717 /* 718 * first, pull the reset wire on the secondary bridge 719 * to clear all devices 720 */ 721 busdata = cardbus_conf_read(cc, cf, ca->ca_tag, 722 PPB_REG_BRIDGECONTROL); 723 cardbus_conf_write(cc, cf, ca->ca_tag, PPB_REG_BRIDGECONTROL, 724 busdata | PPB_BC_SECONDARY_RESET); 725 delay(1); 726 cardbus_conf_write(cc, cf, ca->ca_tag, PPB_REG_BRIDGECONTROL, 727 busdata); 728 729 /* then go initialize the bridge control registers */ 730 maxbus = pci_bus_fixup(psc->sc_pc, 0); 731 } 732 733 busdata = cardbus_conf_read(cc, cf, ca->ca_tag, PPB_REG_BUSINFO); 734 if(PPB_BUSINFO_SECONDARY(busdata) == 0) { 735 printf("%s: still not configured, not fixable.\n", 736 self->dv_xname); 737 return; 738 } 739 740 #if 0 741 minbus = PPB_BUSINFO_SECONDARY(busdata); 742 maxbus = PPB_BUSINFO_SUBORDINATE(busdata); 743 #endif 744 745 /* now, go and assign addresses for the new devices */ 746 rbus_pci_addr_fixup(csc, cc, parent_sc, 747 psc->sc_pc, 748 ca, 749 minbus, maxbus); 750 751 /* 752 * now configure all connected devices to the IRQ which 753 * was assigned to this slot, as they will all arrive from 754 * that IRQ. 755 */ 756 rbus_intr_fixup(psc->sc_pc, minbus, maxbus, ca->ca_intrline); 757 758 /* 759 * enable direct routing of interrupts. We do this because 760 * we can not manage to get pccb_intr_establish() called until 761 * PCI subsystem is merged with rbus. The major thing that this 762 * routine does is avoid calling the driver's interrupt routine 763 * when the card has been removed. 764 * 765 * The rbus_ppb.c can not cope with card desertions until the merging 766 * anyway. 767 */ 768 pccbb_intr_route(psc); 769 770 /* 771 * Attach the PCI bus than hangs off of it. 772 * 773 * XXX Don't pass-through Memory Read Multiple. Should we? 774 * XXX Consult the spec... 775 */ 776 pba.pba_busname = "pci"; 777 pba.pba_iot = ca->ca_iot; 778 pba.pba_memt = ca->ca_memt; 779 pba.pba_dmat = ca->ca_dmat; 780 pba.pba_pc = psc->sc_pc; 781 pba.pba_flags = PCI_FLAGS_IO_ENABLED|PCI_FLAGS_MEM_ENABLED; 782 pba.pba_bus = PPB_BUSINFO_SECONDARY(busdata); 783 pba.pba_bridgetag = &sc->sc_tag; 784 /*pba.pba_intrswiz = parent_sc->sc_intrswiz; */ 785 pba.pba_intrtag = psc->sc_pa.pa_intrtag; 786 787 config_found(self, &pba, rppbprint); 788 } 789 790 void 791 ppb_cardbus_setup(struct ppb_softc * sc) 792 { 793 struct ppb_cardbus_softc *csc = (struct ppb_cardbus_softc *) sc; 794 #if 0 795 cardbus_chipset_tag_t cc = psc->sc_cc; 796 cardbus_function_tag_t cf = psc->sc_cf; 797 #endif 798 799 /* shut up compiler */ 800 csc->foo=2; 801 802 printf("ppb_cardbus_setup called\n"); 803 #if 0 804 /* not sure what to do here */ 805 cardbustag_t tag = cardbus_make_tag(cc, cf, csc->ct->ct_bus, 806 csc->ct->ct_dev, csc->ct->ct_func); 807 808 command = Cardbus_conf_read(csc->ct, tag, CARDBUS_COMMAND_STATUS_REG); 809 if (csc->base0_reg) { 810 Cardbus_conf_write(csc->ct, tag, 811 CARDBUS_BASE0_REG, csc->base0_reg); 812 (cf->cardbus_ctrl) (cc, CARDBUS_MEM_ENABLE); 813 command |= CARDBUS_COMMAND_MEM_ENABLE | 814 CARDBUS_COMMAND_MASTER_ENABLE; 815 } else if (csc->base1_reg) { 816 Cardbus_conf_write(csc->ct, tag, 817 CARDBUS_BASE1_REG, csc->base1_reg); 818 (cf->cardbus_ctrl) (cc, CARDBUS_IO_ENABLE); 819 command |= (CARDBUS_COMMAND_IO_ENABLE | 820 CARDBUS_COMMAND_MASTER_ENABLE); 821 } 822 823 (cf->cardbus_ctrl) (cc, CARDBUS_BM_ENABLE); 824 825 /* enable the card */ 826 Cardbus_conf_write(csc->ct, tag, CARDBUS_COMMAND_STATUS_REG, command); 827 #endif 828 } 829 830 int 831 ppb_cardbus_enable(struct ppb_softc * sc) 832 { 833 #if 0 834 struct ppb_cardbus_softc *csc = (struct fxp_cardbus_softc *) sc; 835 struct cardbus_softc *psc = 836 (struct cardbus_softc *) sc->sc_dev.dv_parent; 837 cardbus_chipset_tag_t cc = psc->sc_cc; 838 cardbus_function_tag_t cf = psc->sc_cf; 839 840 Cardbus_function_enable(csc->ct); 841 842 fxp_cardbus_setup(sc); 843 844 /* Map and establish the interrupt. */ 845 846 sc->sc_ih = cardbus_intr_establish(cc, cf, psc->sc_intrline, IPL_NET, 847 fxp_intr, sc); 848 if (NULL == sc->sc_ih) { 849 printf("%s: couldn't establish interrupt\n", 850 sc->sc_dev.dv_xname); 851 return 1; 852 } 853 854 printf("%s: interrupting at %d\n", sc->sc_dev.dv_xname, 855 psc->sc_intrline); 856 857 #endif 858 return 0; 859 } 860 861 void 862 ppb_cardbus_disable(struct ppb_softc * sc) 863 { 864 #if 0 865 struct cardbus_softc *psc = 866 (struct cardbus_softc *) sc->sc_dev.dv_parent; 867 cardbus_chipset_tag_t cc = psc->sc_cc; 868 cardbus_function_tag_t cf = psc->sc_cf; 869 870 /* Remove interrupt handler. */ 871 cardbus_intr_disestablish(cc, cf, sc->sc_ih); 872 873 Cardbus_function_disable(((struct fxp_cardbus_softc *) sc)->ct); 874 #endif 875 } 876 877 static int 878 ppb_cardbus_detach(self, flags) 879 struct device *self; 880 int flags; 881 { 882 /* struct ppb_softc *sc = (struct ppb_softc *) self;*/ 883 struct ppb_cardbus_softc *csc = (struct ppb_cardbus_softc *) self; 884 885 #if 0 886 struct cardbus_devfunc *ct = csc->ct; 887 int rv, reg; 888 889 #ifdef DIAGNOSTIC 890 if (ct == NULL) 891 panic("%s: data structure lacks\n", sc->sc_dev.dv_xname); 892 #endif 893 894 rv = fxp_detach(sc); 895 if (rv == 0) { 896 /* 897 * Unhook the interrupt handler. 898 */ 899 cardbus_intr_disestablish(ct->ct_cc, ct->ct_cf, sc->sc_ih); 900 901 /* 902 * release bus space and close window 903 */ 904 if (csc->base0_reg) 905 reg = CARDBUS_BASE0_REG; 906 else 907 reg = CARDBUS_BASE1_REG; 908 Cardbus_mapreg_unmap(ct, reg, sc->sc_st, sc->sc_sh, csc->size); 909 } 910 return (rv); 911 912 #endif 913 csc->foo=1; 914 return 0; 915 916 } 917 918 int 919 ppb_activate(self, act) 920 struct device *self; 921 enum devact act; 922 { 923 printf("ppb_activate called\n"); 924 return 0; 925 } 926 927