1 /* $NetBSD: ahbreg.h,v 1.10 2000/07/12 21:15:33 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace 9 * Simulation Facility, NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Originally written by Julian Elischer (julian@tfs.com) 42 * for TRW Financial Systems for use under the MACH(2.5) operating system. 43 * 44 * TRW Financial Systems, in accordance with their agreement with Carnegie 45 * Mellon University, makes this software available to CMU to distribute 46 * or use in any manner that they see fit as long as this message is kept with 47 * the software. For this reason TFS also grants any other persons or 48 * organisations permission to use or modify this software. 49 * 50 * TFS supplies this software to be publicly redistributed 51 * on the understanding that TFS is not responsible for the correct 52 * functioning of this software in any circumstances. 53 */ 54 55 typedef u_int32_t physaddr; 56 typedef u_int32_t physlen; 57 58 /* 59 * Offset of AHA1740 registers, relative from slot base. 60 */ 61 #define AHB_EISA_SLOT_OFFSET 0x0c80 62 #define AHB_EISA_IOSIZE 0x0080 63 64 /* 65 * AHA1740 EISA board mode registers (relative to port offset) 66 */ 67 #define PORTADDR 0x40 68 #define PORTADDR_ENHANCED 0x80 69 #define BIOSADDR 0x41 70 #define INTDEF 0x42 71 #define SCSIDEF 0x43 72 #define BUSDEF 0x44 73 /**** bit definitions for INTDEF ****/ 74 #define INT9 0x00 75 #define INT10 0x01 76 #define INT11 0x02 77 #define INT12 0x03 78 #define INT14 0x05 79 #define INT15 0x06 80 #define INTHIGH 0x08 /* int high=ACTIVE (else edge) */ 81 #define INTEN 0x10 82 /**** bit definitions for SCSIDEF ****/ 83 #define HSCSIID 0x0F /* our SCSI ID */ 84 #define RSTPWR 0x10 /* reset scsi bus on power up or reset */ 85 /**** bit definitions for BUSDEF ****/ 86 #define B0uS 0x00 /* give up bus immediatly */ 87 #define B4uS 0x01 /* delay 4uSec. */ 88 #define B8uS 0x02 89 90 /* 91 * AHA1740 ENHANCED mode mailbox control regs (relative to port offset) 92 */ 93 #define MBOXOUT0 0x50 94 #define MBOXOUT1 0x51 95 #define MBOXOUT2 0x52 96 #define MBOXOUT3 0x53 97 98 #define ATTN 0x54 99 #define G2CNTRL 0x55 100 #define G2INTST 0x56 101 #define G2STAT 0x57 102 103 #define MBOXIN0 0x58 104 #define MBOXIN1 0x59 105 #define MBOXIN2 0x5A 106 #define MBOXIN3 0x5B 107 108 #define G2STAT2 0x5C 109 110 /* 111 * Bit definitions for the 5 control/status registers 112 */ 113 #define ATTN_TARGET 0x0F 114 #define ATTN_OPCODE 0xF0 115 #define OP_IMMED 0x10 116 #define AHB_TARG_RESET 0x80 117 #define OP_START_ECB 0x40 118 #define OP_ABORT_ECB 0x50 119 120 #define G2CNTRL_SET_HOST_READY 0x20 121 #define G2CNTRL_CLEAR_EISA_INT 0x40 122 #define G2CNTRL_HARD_RESET 0x80 123 124 #define G2INTST_TARGET 0x0F 125 #define G2INTST_INT_STAT 0xF0 126 #define AHB_ECB_OK 0x10 127 #define AHB_ECB_RECOVERED 0x50 128 #define AHB_HW_ERR 0x70 129 #define AHB_IMMED_OK 0xA0 130 #define AHB_ECB_ERR 0xC0 131 #define AHB_ASN 0xD0 /* for target mode */ 132 #define AHB_IMMED_ERR 0xE0 133 134 #define G2STAT_BUSY 0x01 135 #define G2STAT_INT_PEND 0x02 136 #define G2STAT_MBOX_EMPTY 0x04 137 138 #define G2STAT2_HOST_READY 0x01 139 140 #define AHB_NSEG 33 /* number of dma segments supported */ 141 142 struct ahb_dma_seg { 143 physaddr seg_addr; 144 physlen seg_len; 145 }; 146 147 struct ahb_ecb_status { 148 u_short status; 149 #define ST_DON 0x0001 150 #define ST_DU 0x0002 151 #define ST_QF 0x0008 152 #define ST_SC 0x0010 153 #define ST_DO 0x0020 154 #define ST_CH 0x0040 155 #define ST_INT 0x0080 156 #define ST_ASA 0x0100 157 #define ST_SNS 0x0200 158 #define ST_INI 0x0800 159 #define ST_ME 0x1000 160 #define ST_ECA 0x4000 161 u_char host_stat; 162 #define HS_OK 0x00 163 #define HS_CMD_ABORTED_HOST 0x04 164 #define HS_CMD_ABORTED_ADAPTER 0x05 165 #define HS_TIMED_OUT 0x11 166 #define HS_HARDWARE_ERR 0x20 167 #define HS_SCSI_RESET_ADAPTER 0x22 168 #define HS_SCSI_RESET_INCOMING 0x23 169 u_char target_stat; 170 u_int32_t resid_count; 171 u_int32_t resid_addr; 172 u_short addit_status; 173 u_char sense_len; 174 u_char unused[9]; 175 u_char cdb[6]; 176 }; 177 178 struct ahb_ecb { 179 u_char opcode; 180 #define ECB_SCSI_OP 0x01 181 u_char:4; 182 u_char options:3; 183 u_char:1; 184 short opt1; 185 #define ECB_CNE 0x0001 186 #define ECB_DI 0x0080 187 #define ECB_SES 0x0400 188 #define ECB_S_G 0x1000 189 #define ECB_DSB 0x4000 190 #define ECB_ARS 0x8000 191 short opt2; 192 #define ECB_LUN 0x0007 193 #define ECB_TAG 0x0008 194 #define ECB_TT 0x0030 195 #define ECB_ND 0x0040 196 #define ECB_DAT 0x0100 197 #define ECB_DIR 0x0200 198 #define ECB_ST 0x0400 199 #define ECB_CHK 0x0800 200 #define ECB_REC 0x4000 201 #define ECB_NRB 0x8000 202 u_short unused1; 203 physaddr data_addr; 204 physlen data_length; 205 physaddr status; 206 physaddr link_addr; 207 short unused2; 208 short unused3; 209 physaddr sense_ptr; 210 u_char req_sense_length; 211 u_char scsi_cmd_length; 212 short cksum; 213 struct scsi_generic scsi_cmd; 214 215 struct ahb_dma_seg ahb_dma[AHB_NSEG]; 216 struct ahb_ecb_status ecb_status; 217 struct scsipi_sense_data ecb_sense; 218 /*-----------------end of hardware supported fields----------------*/ 219 TAILQ_ENTRY(ahb_ecb) chain; 220 struct ahb_ecb *nexthash; 221 int32_t hashkey; 222 struct scsipi_xfer *xs; /* the scsipi_xfer for this cmd */ 223 int flags; 224 #define ECB_ALLOC 0x01 225 #define ECB_ABORT 0x02 226 #define ECB_IMMED 0x04 227 #define ECB_IMMED_FAIL 0x08 228 int timeout; 229 230 /* 231 * This DMA map maps the buffer involved in the transfer. 232 * Its contents are loaded into "ahb_dma" above. 233 */ 234 bus_dmamap_t dmamap_xfer; 235 }; 236