1 /* $NetBSD: max6900.c,v 1.12 2009/12/12 14:44:10 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford and Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: max6900.c,v 1.12 2009/12/12 14:44:10 tsutsui Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 #include <sys/kernel.h> 45 #include <sys/fcntl.h> 46 #include <sys/uio.h> 47 #include <sys/conf.h> 48 #include <sys/event.h> 49 50 #include <dev/clock_subr.h> 51 52 #include <dev/i2c/i2cvar.h> 53 #include <dev/i2c/max6900reg.h> 54 55 struct maxrtc_softc { 56 device_t sc_dev; 57 i2c_tag_t sc_tag; 58 int sc_address; 59 int sc_open; 60 struct todr_chip_handle sc_todr; 61 }; 62 63 static int maxrtc_match(device_t, cfdata_t, void *); 64 static void maxrtc_attach(device_t, device_t, void *); 65 66 CFATTACH_DECL_NEW(maxrtc, sizeof(struct maxrtc_softc), 67 maxrtc_match, maxrtc_attach, NULL, NULL); 68 extern struct cfdriver maxrtc_cd; 69 70 dev_type_open(maxrtc_open); 71 dev_type_close(maxrtc_close); 72 dev_type_read(maxrtc_read); 73 dev_type_write(maxrtc_write); 74 75 const struct cdevsw maxrtc_cdevsw = { 76 maxrtc_open, maxrtc_close, maxrtc_read, maxrtc_write, noioctl, 77 nostop, notty, nopoll, nommap, nokqfilter, D_OTHER 78 }; 79 80 static int maxrtc_clock_read(struct maxrtc_softc *, struct clock_ymdhms *); 81 static int maxrtc_clock_write(struct maxrtc_softc *, struct clock_ymdhms *); 82 static int maxrtc_gettime(struct todr_chip_handle *, struct timeval *); 83 static int maxrtc_settime(struct todr_chip_handle *, struct timeval *); 84 85 int 86 maxrtc_match(device_t parent, cfdata_t cf, void *aux) 87 { 88 struct i2c_attach_args *ia = aux; 89 90 if ((ia->ia_addr & MAX6900_ADDRMASK) == MAX6900_ADDR) 91 return (1); 92 93 return (0); 94 } 95 96 void 97 maxrtc_attach(device_t parent, device_t self, void *aux) 98 { 99 struct maxrtc_softc *sc = device_private(self); 100 struct i2c_attach_args *ia = aux; 101 102 sc->sc_tag = ia->ia_tag; 103 sc->sc_address = ia->ia_addr; 104 sc->sc_dev = self; 105 106 aprint_naive(": Real-time Clock/NVRAM\n"); 107 aprint_normal(": MAX6900 Real-time Clock/NVRAM\n"); 108 109 sc->sc_open = 0; 110 111 sc->sc_todr.cookie = sc; 112 sc->sc_todr.todr_gettime = maxrtc_gettime; 113 sc->sc_todr.todr_settime = maxrtc_settime; 114 sc->sc_todr.todr_setwen = NULL; 115 116 todr_attach(&sc->sc_todr); 117 } 118 119 /*ARGSUSED*/ 120 int 121 maxrtc_open(dev_t dev, int flag, int fmt, struct lwp *l) 122 { 123 struct maxrtc_softc *sc; 124 125 if ((sc = device_lookup_private(&maxrtc_cd, minor(dev))) == NULL) 126 return (ENXIO); 127 128 /* XXX: Locking */ 129 130 if (sc->sc_open) 131 return (EBUSY); 132 133 sc->sc_open = 1; 134 return (0); 135 } 136 137 /*ARGSUSED*/ 138 int 139 maxrtc_close(dev_t dev, int flag, int fmt, struct lwp *l) 140 { 141 struct maxrtc_softc *sc; 142 143 if ((sc = device_lookup_private(&maxrtc_cd, minor(dev))) == NULL) 144 return (ENXIO); 145 146 sc->sc_open = 0; 147 return (0); 148 } 149 150 /*ARGSUSED*/ 151 int 152 maxrtc_read(dev_t dev, struct uio *uio, int flags) 153 { 154 struct maxrtc_softc *sc; 155 u_int8_t ch, cmdbuf[1]; 156 int a, error; 157 158 if ((sc = device_lookup_private(&maxrtc_cd, minor(dev))) == NULL) 159 return (ENXIO); 160 161 if (uio->uio_offset >= MAX6900_RAM_BYTES) 162 return (EINVAL); 163 164 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 165 return (error); 166 167 while (uio->uio_resid && uio->uio_offset < MAX6900_RAM_BYTES) { 168 a = (int)uio->uio_offset; 169 cmdbuf[0] = MAX6900_REG_RAM(a) | MAX6900_CMD_READ; 170 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 171 sc->sc_address, cmdbuf, 1, 172 &ch, 1, 0)) != 0) { 173 iic_release_bus(sc->sc_tag, 0); 174 aprint_error_dev(sc->sc_dev, 175 "maxrtc_read: read failed at 0x%x\n", a); 176 return (error); 177 } 178 if ((error = uiomove(&ch, 1, uio)) != 0) { 179 iic_release_bus(sc->sc_tag, 0); 180 return (error); 181 } 182 } 183 184 iic_release_bus(sc->sc_tag, 0); 185 186 return (0); 187 } 188 189 /*ARGSUSED*/ 190 int 191 maxrtc_write(dev_t dev, struct uio *uio, int flags) 192 { 193 struct maxrtc_softc *sc; 194 u_int8_t cmdbuf[2]; 195 int a, error, sverror; 196 197 if ((sc = device_lookup_private(&maxrtc_cd, minor(dev))) == NULL) 198 return (ENXIO); 199 200 if (uio->uio_offset >= MAX6900_RAM_BYTES) 201 return (EINVAL); 202 203 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 204 return (error); 205 206 /* Start by clearing the control register's write-protect bit. */ 207 cmdbuf[0] = MAX6900_REG_CONTROL | MAX6900_CMD_WRITE; 208 cmdbuf[1] = 0; 209 210 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address, 211 cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 212 iic_release_bus(sc->sc_tag, 0); 213 aprint_error_dev(sc->sc_dev, 214 "maxrtc_write: failed to clear WP bit\n"); 215 return (error); 216 } 217 218 while (uio->uio_resid && uio->uio_offset < MAX6900_RAM_BYTES) { 219 a = (int)uio->uio_offset; 220 221 cmdbuf[0] = MAX6900_REG_RAM(a) | MAX6900_CMD_WRITE; 222 if ((error = uiomove(&cmdbuf[1], 1, uio)) != 0) 223 break; 224 225 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address, 226 cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 227 aprint_error_dev(sc->sc_dev, 228 "maxrtc_write: write failed at 0x%x\n", a); 229 break; 230 } 231 } 232 233 /* Set the write-protect bit again. */ 234 cmdbuf[0] = MAX6900_REG_CONTROL | MAX6900_CMD_WRITE; 235 cmdbuf[1] = MAX6900_CONTROL_WP; 236 237 sverror = error; 238 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, 239 sc->sc_address, cmdbuf, 1, 240 &cmdbuf[1], 1, 0)) != 0) { 241 if (sverror != 0) 242 error = sverror; 243 aprint_error_dev(sc->sc_dev, 244 "maxrtc_write: failed to set WP bit\n"); 245 } 246 247 iic_release_bus(sc->sc_tag, 0); 248 249 return (error); 250 } 251 252 static int 253 maxrtc_gettime(struct todr_chip_handle *ch, struct timeval *tv) 254 { 255 struct maxrtc_softc *sc = ch->cookie; 256 struct clock_ymdhms dt; 257 258 if (maxrtc_clock_read(sc, &dt) == 0) 259 return (-1); 260 261 tv->tv_sec = clock_ymdhms_to_secs(&dt); 262 tv->tv_usec = 0; 263 264 return (0); 265 } 266 267 static int 268 maxrtc_settime(struct todr_chip_handle *ch, struct timeval *tv) 269 { 270 struct maxrtc_softc *sc = ch->cookie; 271 struct clock_ymdhms dt; 272 273 clock_secs_to_ymdhms(tv->tv_sec, &dt); 274 275 if (maxrtc_clock_write(sc, &dt) == 0) 276 return (-1); 277 278 return (0); 279 } 280 281 /* 282 * While the MAX6900 has a nice Clock Burst Read/Write command, 283 * we can't use it, since some I2C controllers do not support 284 * anything other than single-byte transfers. 285 */ 286 static int max6900_rtc_offset[] = { 287 MAX6900_REG_SECOND, 288 MAX6900_REG_MINUTE, 289 MAX6900_REG_HOUR, 290 MAX6900_REG_DATE, 291 MAX6900_REG_MONTH, 292 MAX6900_REG_DAY, 293 MAX6900_REG_YEAR, 294 MAX6900_REG_CENTURY, /* control, if burst */ 295 }; 296 297 static int 298 maxrtc_clock_read(struct maxrtc_softc *sc, struct clock_ymdhms *dt) 299 { 300 u_int8_t bcd[MAX6900_BURST_LEN], cmdbuf[1]; 301 int i; 302 303 if (iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) { 304 aprint_error_dev(sc->sc_dev, 305 "maxrtc_clock_read: failed to acquire I2C bus\n"); 306 return (0); 307 } 308 309 /* Read each timekeeping register in order. */ 310 for (i = 0; i < MAX6900_BURST_LEN; i++) { 311 cmdbuf[0] = max6900_rtc_offset[i] | MAX6900_CMD_READ; 312 313 if (iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 314 sc->sc_address, cmdbuf, 1, 315 &bcd[i], 1, I2C_F_POLL)) { 316 iic_release_bus(sc->sc_tag, I2C_F_POLL); 317 aprint_error_dev(sc->sc_dev, 318 "maxrtc_clock_read: failed to read rtc " 319 "at 0x%x\n", 320 max6900_rtc_offset[i]); 321 return (0); 322 } 323 } 324 325 /* Done with I2C */ 326 iic_release_bus(sc->sc_tag, I2C_F_POLL); 327 328 /* 329 * Convert the MAX6900's register values into something useable 330 */ 331 dt->dt_sec = FROMBCD(bcd[MAX6900_BURST_SECOND] & MAX6900_SECOND_MASK); 332 dt->dt_min = FROMBCD(bcd[MAX6900_BURST_MINUTE] & MAX6900_MINUTE_MASK); 333 334 if (bcd[MAX6900_BURST_HOUR] & MAX6900_HOUR_12HRS) { 335 dt->dt_hour = FROMBCD(bcd[MAX6900_BURST_HOUR] & 336 MAX6900_HOUR_12MASK); 337 if (bcd[MAX6900_BURST_HOUR] & MAX6900_HOUR_12HRS_PM) 338 dt->dt_hour += 12; 339 } else { 340 dt->dt_hour = FROMBCD(bcd[MAX6900_BURST_HOUR] & 341 MAX6900_HOUR_24MASK); 342 } 343 344 dt->dt_day = FROMBCD(bcd[MAX6900_BURST_DATE] & MAX6900_DATE_MASK); 345 dt->dt_mon = FROMBCD(bcd[MAX6900_BURST_MONTH] & MAX6900_MONTH_MASK); 346 dt->dt_year = FROMBCD(bcd[MAX6900_BURST_YEAR]); 347 /* century in the burst control slot */ 348 dt->dt_year += (int)FROMBCD(bcd[MAX6900_BURST_CONTROL]) * 100; 349 350 return (1); 351 } 352 353 static int 354 maxrtc_clock_write(struct maxrtc_softc *sc, struct clock_ymdhms *dt) 355 { 356 uint8_t bcd[MAX6900_BURST_LEN], cmdbuf[2]; 357 uint8_t init_seconds, final_seconds; 358 int i; 359 360 /* 361 * Convert our time representation into something the MAX6900 362 * can understand. 363 */ 364 bcd[MAX6900_BURST_SECOND] = TOBCD(dt->dt_sec); 365 bcd[MAX6900_BURST_MINUTE] = TOBCD(dt->dt_min); 366 bcd[MAX6900_BURST_HOUR] = TOBCD(dt->dt_hour) & MAX6900_HOUR_24MASK; 367 bcd[MAX6900_BURST_DATE] = TOBCD(dt->dt_day); 368 bcd[MAX6900_BURST_WDAY] = TOBCD(dt->dt_wday); 369 bcd[MAX6900_BURST_MONTH] = TOBCD(dt->dt_mon); 370 bcd[MAX6900_BURST_YEAR] = TOBCD(dt->dt_year % 100); 371 /* century in control slot */ 372 bcd[MAX6900_BURST_CONTROL] = TOBCD(dt->dt_year / 100); 373 374 if (iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) { 375 aprint_error_dev(sc->sc_dev, 376 "maxrtc_clock_write: failed to acquire I2C bus\n"); 377 return (0); 378 } 379 380 /* Start by clearing the control register's write-protect bit. */ 381 cmdbuf[0] = MAX6900_REG_CONTROL | MAX6900_CMD_WRITE; 382 cmdbuf[1] = 0; 383 384 if (iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address, 385 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) { 386 iic_release_bus(sc->sc_tag, I2C_F_POLL); 387 aprint_error_dev(sc->sc_dev, 388 "maxrtc_clock_write: failed to clear WP bit\n"); 389 return (0); 390 } 391 392 /* 393 * The MAX6900 RTC manual recommends ensuring "atomicity" of 394 * a non-burst write by: 395 * 396 * - writing SECONDS 397 * - reading back SECONDS, remembering it as "initial seconds" 398 * - write the remaing RTC registers 399 * - read back SECONDS as "final seconds" 400 * - if "initial seconds" == 59, ensure "final seconds" == 59 401 * - else, ensure "final seconds" is no more than one second 402 * beyond "initial seconds". 403 */ 404 again: 405 cmdbuf[0] = MAX6900_REG_SECOND | MAX6900_CMD_WRITE; 406 if (iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address, 407 cmdbuf, 1, &bcd[MAX6900_BURST_SECOND], 1, I2C_F_POLL)) { 408 iic_release_bus(sc->sc_tag, I2C_F_POLL); 409 aprint_error_dev(sc->sc_dev, 410 "maxrtc_clock_write: failed to write SECONDS\n"); 411 return (0); 412 } 413 414 cmdbuf[0] = MAX6900_REG_SECOND | MAX6900_CMD_READ; 415 if (iic_exec(sc->sc_tag, I2C_OP_READ, sc->sc_address, 416 cmdbuf, 1, &init_seconds, 1, I2C_F_POLL)) { 417 iic_release_bus(sc->sc_tag, I2C_F_POLL); 418 aprint_error_dev(sc->sc_dev, 419 "maxrtc_clock_write: failed to read " 420 "INITIAL SECONDS\n"); 421 return (0); 422 } 423 424 for (i = 1; i < MAX6900_BURST_LEN; i++) { 425 cmdbuf[0] = max6900_rtc_offset[i] | MAX6900_CMD_WRITE; 426 if (iic_exec(sc->sc_tag, 427 i != MAX6900_BURST_LEN - 1 ? I2C_OP_WRITE : 428 I2C_OP_WRITE_WITH_STOP, sc->sc_address, 429 cmdbuf, 1, &bcd[i], 1, I2C_F_POLL)) { 430 iic_release_bus(sc->sc_tag, I2C_F_POLL); 431 aprint_error_dev(sc->sc_dev, 432 "maxrtc_clock_write: failed to write rtc " 433 " at 0x%x\n", 434 max6900_rtc_offset[i]); 435 return (0); 436 } 437 } 438 439 cmdbuf[0] = MAX6900_REG_SECOND | MAX6900_CMD_READ; 440 if (iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_address, 441 cmdbuf, 1, &final_seconds, 1, I2C_F_POLL)) { 442 iic_release_bus(sc->sc_tag, I2C_F_POLL); 443 aprint_error_dev(sc->sc_dev, 444 "maxrtc_clock_write: failed to read " 445 "FINAL SECONDS\n"); 446 return (0); 447 } 448 449 if ((init_seconds == 59 && final_seconds != 59) || 450 (init_seconds != 59 && final_seconds != init_seconds + 1)) { 451 #if 1 452 printf("%s: maxrtc_clock_write: init %d, final %d, try again\n", 453 device_xname(sc->sc_dev), init_seconds, final_seconds); 454 #endif 455 goto again; 456 } 457 458 /* Finish by setting the control register's write-protect bit. */ 459 cmdbuf[0] = MAX6900_REG_CONTROL | MAX6900_CMD_WRITE; 460 cmdbuf[1] = MAX6900_CONTROL_WP; 461 462 if (iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, sc->sc_address, 463 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) { 464 iic_release_bus(sc->sc_tag, I2C_F_POLL); 465 aprint_error_dev(sc->sc_dev, 466 "maxrtc_clock_write: failed to set WP bit\n"); 467 return (0); 468 } 469 470 iic_release_bus(sc->sc_tag, I2C_F_POLL); 471 472 return (1); 473 } 474