1 /* $NetBSD: aic6915reg.h,v 1.2 2002/05/03 00:04:07 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #ifndef _DEV_IC_AIC6915REG_H_ 40 #define _DEV_IC_AIC6915REG_H_ 41 42 /* 43 * Register description for the Adaptec AIC-6915 (``Starfire'') 44 * 10/100 Ethernet controller. 45 */ 46 47 /* 48 * Receive Buffer Descriptor (One-size, 32-bit addressing) 49 */ 50 struct sf_rbd32 { 51 uint32_t rbd32_addr; /* address, flags */ 52 } __attribute__((__packed__)); 53 54 /* 55 * Receive Buffer Descriptor (One-size, 64-bit addressing) 56 */ 57 struct sf_rbd64 { 58 uint32_t rbd64_addr_lo; /* address (LSD), flags */ 59 uint32_t rbd64_addr_hi; /* address (MDS) */ 60 } __attribute__((__packed__)); 61 62 #define RBD_V (1U << 0) /* valid descriptor */ 63 #define RBD_E (1U << 1) /* end of ring */ 64 65 /* 66 * Short (Type 0) Completion Descriptor 67 */ 68 struct sf_rcd_short { 69 uint32_t rcd_word0; /* length, end index, status1 */ 70 } __attribute__((__packed__)); 71 72 /* 73 * Basic (Type 1) Completion Descriptor 74 */ 75 struct sf_rcd_basic { 76 uint32_t rcd_word0; /* length, end index, status1 */ 77 uint32_t rcd_word1; /* VLAN ID, status2 */ 78 } __attribute__((__packed__)); 79 80 /* 81 * Checksum (Type 2) Completion Descriptor 82 */ 83 struct sf_rcd_checksum { 84 uint32_t rcd_word0; /* length, end index, status1 */ 85 uint32_t rcd_word1; /* partial TCP/UDP checksum, status2 */ 86 } __attribute__((__packed__)); 87 88 /* 89 * Full (Type 3) Completion Descriptor 90 */ 91 struct sf_rcd_full { 92 uint32_t rcd_word0; /* length, end index, status1 */ 93 uint32_t rcd_word1; /* start index, status3, status2 */ 94 uint32_t rcd_word2; /* VLAN ID + priority, TCP/UDP csum */ 95 uint32_t rcd_timestamp; /* timestamp */ 96 } __attribute__((__packed__)); 97 98 #define RCD_W0_ID (1U << 30) 99 100 #define RCD_W0_Length(x) ((x) & 0xffff) 101 #define RCD_W0_EndIndex(x) (((x) >> 16) & 0x7ff) 102 #define RCD_W0_BufferQueue (1U << 27) /* 1 == Queue 2 */ 103 #define RCD_W0_FifoFull (1U << 28) /* FIFO full */ 104 #define RCD_W0_OK (1U << 29) /* packet is OK */ 105 106 /* Status2 field */ 107 #define RCD_W1_FrameType (7U << 16) 108 #define RCD_W1_FrameType_Unknown (0 << 16) 109 #define RCD_W1_FrameType_IPv4 (1U << 16) 110 #define RCD_W1_FrameType_IPv6 (2U << 16) 111 #define RCD_W1_FrameType_IPX (3U << 16) 112 #define RCD_W1_FrameType_ICMP (4U << 16) 113 #define RCD_W1_FrameType_Unsupported (5U << 16) 114 #define RCD_W1_UdpFrame (1U << 19) 115 #define RCD_W1_TcpFrame (1U << 20) 116 #define RCD_W1_Fragmented (1U << 21) 117 #define RCD_W1_PartialChecksumValid (1U << 22) 118 #define RCD_W1_ChecksumBad (1U << 23) 119 #define RCD_W1_ChecksumOk (1U << 24) 120 #define RCD_W1_VlanFrame (1U << 25) 121 #define RCD_W1_ReceiveCodeViolation (1U << 26) 122 #define RCD_W1_Dribble (1U << 27) 123 #define RCD_W1_ISLCRCerror (1U << 28) 124 #define RCD_W1_CRCerror (1U << 29) 125 #define RCD_W1_Hash (1U << 30) 126 #define RCD_W1_Perfect (1U << 31) 127 128 #define RCD_W1_VLANID(x) ((x) & 0xffff) 129 #define RCD_W1_TCP_UDP_Checksum(x) ((x) & 0xffff) 130 131 /* Status3 field */ 132 #define RCD_W1_Trailer (1U << 11) 133 #define RCD_W1_Header (1U << 12) 134 #define RCD_W1_ControlFrame (1U << 13) 135 #define RCD_W1_PauseFrame (1U << 14) 136 #define RCD_W1_IslFrame (1U << 15) 137 138 #define RCD_W1_StartIndex(x) ((x) & 0x7ff) 139 140 #define RCD_W2_TCP_UDP_Checksum(x) ((x) >> 16) 141 #define RCD_W2_VLANID(x) ((x) & 0xffff) 142 143 /* 144 * Number of transmit buffer fragments we use. This is arbitrary, but 145 * we choose it carefully; see blow. 146 */ 147 #define SF_NTXFRAGS 15 148 149 /* 150 * Type 0, 32-bit addressing mode (Frame Descriptor) Transmit Descriptor 151 * 152 * NOTE: The total length of this structure is: 8 + (15 * 8) == 128 153 * This means 16 Tx indices per Type 0 descriptor. This is important later 154 * on; see below. 155 */ 156 struct sf_txdesc0 { 157 /* skip field */ 158 uint32_t td_word0; /* ID, flags */ 159 uint32_t td_word1; /* Tx buffer count */ 160 struct { 161 uint32_t fr_addr; /* address */ 162 uint32_t fr_len; /* length */ 163 } __attribute__((__packed__)) td_frags[SF_NTXFRAGS]; 164 } __attribute__((__packed__)); 165 166 #define TD_W1_NTXBUFS (0xff << 0) 167 168 /* 169 * Type 1, 32-bit addressing mode (Buffer Descriptor) Transmit Descriptor 170 */ 171 struct sf_txdesc1 { 172 /* skip field */ 173 uint32_t td_word0; /* ID, flags */ 174 uint32_t td_addr; /* buffer address */ 175 } __attribute__((__packed__)); 176 177 #define TD_W0_ID (0xb << 28) 178 #define TD_W0_INTR (1U << 27) 179 #define TD_W0_END (1U << 26) 180 #define TD_W0_CALTCP (1U << 25) 181 #define TD_W0_CRCEN (1U << 24) 182 #define TD_W0_LEN (0xffff << 0) 183 #define TD_W0_NTXBUFS (0xff << 16) 184 #define TD_W0_NTXBUFS_SHIFT 16 185 186 /* 187 * Type 2, 64-bit addressing mode (Buffer Descriptor) Transmit Descriptor 188 */ 189 struct sf_txdesc2 { 190 /* skip field */ 191 uint32_t td_word0; /* ID, flags */ 192 uint32_t td_reserved; 193 uint32_t td_addr_lo; /* buffer address (LSD) */ 194 uint32_t td_addr_hi; /* buffer address (MSD) */ 195 } __attribute__((__packed__)); 196 197 /* 198 * Transmit Completion Descriptor. 199 */ 200 struct sf_tcd { 201 uint32_t tcd_word0; /* index, priority, flags */ 202 } __attribute__((__packed__)); 203 204 #define TCD_DMA_ID (0x4 << 29) 205 #define TCD_INDEX(x) ((x) & 0x7fff) 206 #define TCD_PR (1U << 15) 207 #define TCD_TIMESTAMP(x) (((x) >> 16) & 0x1fff) 208 209 #define TCD_TX_ID (0x5 << 29) 210 #define TCD_CRCerror (1U << 16) 211 #define TCD_FieldLengthCkError (1U << 17) 212 #define TCD_FieldLengthRngError (1U << 18) 213 #define TCD_PacketTxOk (1U << 19) 214 #define TCD_Deferred (1U << 20) 215 #define TCD_ExDeferral (1U << 21) 216 #define TCD_ExCollisions (1U << 22) 217 #define TCD_LateCollision (1U << 23) 218 #define TCD_LongFrame (1U << 24) 219 #define TCD_FIFOUnderrun (1U << 25) 220 #define TCD_ControlTx (1U << 26) 221 #define TCD_PauseTx (1U << 27) 222 #define TCD_TxPaused (1U << 28) 223 224 /* 225 * The Tx indices are in units of 8 bytes, and since we are using 226 * Tx descriptors that are 128 bytes long, we need to divide by 16 227 * to get the actual index that we care about. 228 */ 229 #define SF_TXDINDEX_TO_HOST(x) ((x) >> 4) 230 #define SF_TXDINDEX_TO_CHIP(x) ((x) << 4) 231 232 /* 233 * To make matters worse, the manual lies about the indices in the 234 * completion queue entires. It claims they are in 8-byte units, 235 * but they're actually *BYTES*, which means we need to divide by 236 * 128 to get the actual index. 237 */ 238 #define SF_TCD_INDEX_TO_HOST(x) ((x) >> 7) 239 240 /* 241 * PCI configuration space addresses. 242 */ 243 #define SF_PCI_MEMBA (PCI_MAPREG_START + 0x00) 244 #define SF_PCI_IOBA (PCI_MAPREG_START + 0x08) 245 246 #define SF_GENREG_OFFSET 0x50000 247 #define SF_FUNCREG_SIZE 0x100 248 249 /* 250 * PCI functional registers. 251 */ 252 #define SF_PciDeviceConfig 0x40 253 #define PDC_EnDpeInt (1U << 31) /* enable DPE PCIint */ 254 #define PDC_EnSseInt (1U << 30) /* enable SSE PCIint */ 255 #define PDC_EnRmaInt (1U << 29) /* enable RMA PCIint */ 256 #define PDC_EnRtaInt (1U << 28) /* enable RTA PCIint */ 257 #define PDC_EnStaInt (1U << 27) /* enable STA PCIint */ 258 #define PDC_EnDprInt (1U << 24) /* enable DPR PCIint */ 259 #define PDC_IntEnable (1U << 23) /* enable PCI_INTA_ */ 260 #define PDC_ExternalRegCsWidth (7U << 20) /* external chip-sel width */ 261 #define PDC_StopMWrOnCacheLineDis (1U << 19) 262 #define PDC_EpromCsWidth (7U << 16) 263 #define PDC_EnBeLogic (1U << 15) 264 #define PDC_LatencyStopOnCacheLine (1U << 14) 265 #define PDC_PCIMstDmaEn (1U << 13) 266 #define PDC_StopOnCachelineEn (1U << 12) 267 #define PDC_FifoThreshold (0xf << 8) 268 #define PDC_FifoThreshold_SHIFT 8 269 #define PDC_MemRdCmdEn (1U << 7) 270 #define PDC_StopOnPerr (1U << 6) 271 #define PDC_AbortOnAddrParityErr (1U << 5) 272 #define PDC_EnIncrement (1U << 4) 273 #define PDC_System64 (1U << 2) 274 #define PDC_Force64 (1U << 1) 275 #define PDC_SoftReset (1U << 0) 276 277 #define SF_BacControl 0x44 278 #define BC_DescSwapMode (0x3 << 6) 279 #define BC_DataSwapMode (0x3 << 4) 280 #define BC_SingleDmaMode (1U << 3) 281 #define BC_PreferTxDmaReq (1U << 2) 282 #define BC_PreferRxDmaReq (1U << 1) 283 #define BC_BacDmaEn (1U << 0) 284 285 #define SF_PciMonitor1 0x48 286 287 #define SF_PciMonitor2 0x4c 288 289 #define SF_PMC 0x50 290 291 #define SF_PMCSR 0x54 292 293 #define SF_PMEvent 0x58 294 295 #define SF_SerialEpromControl 0x60 296 #define SEC_InitDone (1U << 3) 297 #define SEC_Idle (1U << 2) 298 #define SEC_WriteEnable (1U << 1) 299 #define SEC_WriteDisable (1U << 0) 300 301 #define SF_PciComplianceTesting 0x64 302 303 #define SF_IndirectIoAccess 0x68 304 305 #define SF_IndirectIoDataPort 0x6c 306 307 /* 308 * Ethernet functional registers. 309 */ 310 #define SF_GeneralEthernetCtrl 0x70 311 #define GEC_SetSoftInt (1U << 8) 312 #define GEC_TxGfpEn (1U << 5) 313 #define GEC_RxGfpEn (1U << 4) 314 #define GEC_TxDmaEn (1U << 3) 315 #define GEC_RxDmaEn (1U << 2) 316 #define GEC_TransmitEn (1U << 1) 317 #define GEC_ReceiveEn (1U << 0) 318 319 #define SF_TimersControl 0x74 320 #define TC_EarlyRxQ1IntDelayDisable (1U << 31) 321 #define TC_RxQ1DoneIntDelayDisable (1U << 30) 322 #define TC_EarlyRxQ2IntDelayDisable (1U << 29) 323 #define TC_RxQ2DoneIntDelayDisable (1U << 28) 324 #define TC_TimeStampResolution (1U << 26) 325 #define TC_GeneralTimerResolution (1U << 25) 326 #define TC_OneShotMode (1U << 24) 327 #define TC_GeneralTimerInterval (0xff << 16) 328 #define TC_GeneralTimerInterval_SHIFT 16 329 #define TC_TxFrameCompleteIntDelayDisable (1U << 15) 330 #define TC_TxQueueDoneIntDelayDisable (1U << 14) 331 #define TC_TxDmaDoneIntDelayDisable (1U << 13) 332 #define TC_RxHiPrBypass (1U << 12) 333 #define TC_Timer10X (1U << 11) 334 #define TC_SmallRxFrame (3U << 9) 335 #define TC_SmallFrameBypass (1U << 8) 336 #define TC_IntMaskMode (3U << 5) 337 #define TC_IntMaskPeriod (0x1f << 0) 338 339 #define SF_CurrentTime 0x78 340 341 #define SF_InterruptStatus 0x80 342 #define IS_GPIO3 (1U << 31) 343 #define IS_GPIO2 (1U << 30) 344 #define IS_GPIO1 (1U << 29) 345 #define IS_GPIO0 (1U << 28) 346 #define IS_StatisticWrapInt (1U << 27) 347 #define IS_AbnormalInterrupt (1U << 25) 348 #define IS_GeneralTimerInt (1U << 24) 349 #define IS_SoftInt (1U << 23) 350 #define IS_RxCompletionQueue1Int (1U << 22) 351 #define IS_TxCompletionQueueInt (1U << 21) 352 #define IS_PCIInt (1U << 20) 353 #define IS_DmaErrInt (1U << 19) 354 #define IS_TxDataLowInt (1U << 18) 355 #define IS_RxCompletionQueue2Int (1U << 17) 356 #define IS_RxQ1LowBuffersInt (1U << 16) 357 #define IS_NormalInterrupt (1U << 15) 358 #define IS_TxFrameCompleteInt (1U << 14) 359 #define IS_TxDmaDoneInt (1U << 13) 360 #define IS_TxQueueDoneInt (1U << 12) 361 #define IS_EarlyRxQ2Int (1U << 11) 362 #define IS_EarlyRxQ1Int (1U << 10) 363 #define IS_RxQ2DoneInt (1U << 9) 364 #define IS_RxQ1DoneInt (1U << 8) 365 #define IS_RxGfpNoResponseInt (1U << 7) 366 #define IS_RxQ2LowBuffersInt (1U << 6) 367 #define IS_NoTxChecksumInt (1U << 5) 368 #define IS_TxLowPrMismatchInt (1U << 4) 369 #define IS_TxHiPrMismatchInt (1U << 3) 370 #define IS_GfpRxInt (1U << 2) 371 #define IS_GfpTxInt (1U << 1) 372 #define IS_PCIPadInt (1U << 0) 373 374 #define SF_ShadowInterruptStatus 0x84 375 376 #define SF_InterruptEn 0x88 377 378 #define SF_GPIO 0x8c 379 #define GPIOCtrl(x) (1U << (24 + (x))) 380 #define GPIOOutMode(x) (1U << (16 + (x))) 381 #define GPIOInpMode(x, y) ((y) << (8 + ((x) * 2))) 382 #define GPIOData(x) (1U << (x)) 383 384 #define SF_TxDescQueueCtrl 0x90 385 #define TDQC_TxHighPriorityFifoThreshold(x) ((x) << 24) 386 #define TDQC_SkipLength(x) ((x) << 16) 387 #define TDQC_TxDmaBurstSize(x) ((x) << 8) 388 #define TDQC_TxDescQueue64bitAddr (1U << 7) 389 #define TDQC_MinFrameSpacing(x) ((x) << 4) 390 #define TDQC_DisableTxDmaCompletion (1U << 3) 391 #define TDQC_TxDescType(x) ((x) << 0) 392 393 #define SF_HiPrTxDescQueueBaseAddr 0x94 394 395 #define SF_LoPrTxDescQueueBaseAddr 0x98 396 397 #define SF_TxDescQueueHighAddr 0x9c 398 399 #define SF_TxDescQueueProducerIndex 0xa0 400 #define TDQPI_HiPrTxProducerIndex(x) ((x) << 16) 401 #define TDQPI_LoPrTxProducerIndex(x) ((x) << 0) 402 #define TDQPI_HiPrTxProducerIndex_get(x) (((x) >> 16) & 0x7ff) 403 #define TDQPI_LoPrTxProducerIndex_get(x) (((x) >> 0) & 0x7ff) 404 405 #define SF_TxDescQueueConsumerIndex 0xa4 406 #define TDQCI_HiPrTxConsumerIndex(x) (((x) >> 16) & 0x7ff) 407 #define TDQCI_LoPrTxConsumerIndex(s) (((x) >> 0) & 0x7ff) 408 409 #define SF_TxDmaStatus1 0xa8 410 411 #define SF_TxDmaStatus2 0xac 412 413 #define SF_TransmitFrameCSR 0xb0 414 #define TFCSR_TxFrameStatus (0xff << 16) 415 #define TFCSR_TxDebugConfigBits (0x7f << 9) 416 #define TFCSR_DmaCompletionAfterTransmitComplete (1U << 8) 417 #define TFCSR_TransmitThreshold(x) ((x) << 0) 418 419 #define SF_CompletionQueueHighAddr 0xb4 420 421 #define SF_TxCompletionQueueCtrl 0xb8 422 #define TCQC_TxCompletionBaseAddress 0xffffff00 423 #define TCQC_TxCompletion64bitAddress (1U << 7) 424 #define TCQC_TxCompletionProducerWe (1U << 6) 425 #define TCQC_TxCompletionSize (1U << 5) 426 #define TCQC_CommonQueueMode (1U << 4) 427 #define TCQC_TxCompletionQueueThreshold ((x) << 0) 428 429 #define SF_RxCompletionQueue1Ctrl 0xbc 430 #define RCQ1C_RxCompletionQ1BaseAddress 0xffffff00 431 #define RCQ1C_RxCompletionQ164bitAddress (1U << 7) 432 #define RCQ1C_RxCompletionQ1ProducerWe (1U << 6) 433 #define RCQ1C_RxCompletionQ1Type(x) ((x) << 4) 434 #define RCQ1C_RxCompletionQ1Threshold(x) ((x) << 0) 435 436 #define SF_RxCompletionQueue2Ctrl 0xc0 437 #define RCQ1C_RxCompletionQ2BaseAddress 0xffffff00 438 #define RCQ1C_RxCompletionQ264bitAddress (1U << 7) 439 #define RCQ1C_RxCompletionQ2ProducerWe (1U << 6) 440 #define RCQ1C_RxCompletionQ2Type(x) ((x) << 4) 441 #define RCQ1C_RxCompletionQ2Threshold(x) ((x) << 0) 442 443 #define SF_CompletionQueueConsumerIndex 0xc4 444 #define CQCI_TxCompletionThresholdMode (1U << 31) 445 #define CQCI_TxCompletionConsumerIndex(x) ((x) << 16) 446 #define CQCI_TxCompletionConsumerIndex_get(x) (((x) >> 16) & 0x7ff) 447 #define CQCI_RxCompletionQ1ThresholdMode (1U << 15) 448 #define CQCI_RxCompletionQ1ConsumerIndex(x) ((x) << 0) 449 #define CQCI_RxCompletionQ1ConsumerIndex_get(x) ((x) & 0x7ff) 450 451 #define SF_CompletionQueueProducerIndex 0xc8 452 #define CQPI_TxCompletionProducerIndex(x) ((x) << 16) 453 #define CQPI_TxCompletionProducerIndex_get(x) (((x) >> 16) & 0x7ff) 454 #define CQPI_RxCompletionQ1ProducerIndex(x) ((x) << 0) 455 #define CQPI_RxCompletionQ1ProducerIndex_get(x) ((x) & 0x7ff) 456 457 #define SF_RxHiPrCompletionPtrs 0xcc 458 #define RHPCP_RxCompletionQ2ProducerIndex(x) ((x) << 16) 459 #define RHPCP_RxCompletionQ2ThresholdMode (1U << 15) 460 #define RHPCP_RxCompletionQ2ConsumerIndex(x) ((x) << 0) 461 462 #define SF_RxDmaCtrl 0xd0 463 #define RDC_RxReportBadFrames (1U << 31) 464 #define RDC_RxDmaShortFrames (1U << 30) 465 #define RDC_RxDmaBadFrames (1U << 29) 466 #define RDC_RxDmaCrcErrorFrames (1U << 28) 467 #define RDC_RxDmaControlFrame (1U << 27) 468 #define RDC_RxDmaPauseFrame (1U << 26) 469 #define RDC_RxChecksumMode(x) ((x) << 24) 470 #define RDC_RxCompletionQ2Enable (1U << 23) 471 #define RDC_RxDmaQueueMode(x) ((x) << 20) 472 #define RDC_RxUseBackupQueue (1U << 19) 473 #define RDC_RxDmaCrc (1U << 18) 474 #define RDC_RxEarlyIntThreshold(x) ((x) << 12) 475 #define RDC_RxHighPriorityThreshold(x) ((x) << 8) 476 #define RDC_RxBurstSize(x) ((x) << 0) 477 478 #define SF_RxDescQueue1Ctrl 0xd4 479 #define RDQ1C_RxQ1BufferLength(x) ((x) << 16) 480 #define RDQ1C_RxPrefetchDescriptorsMode (1U << 15) 481 #define RDQ1C_RxDescQ1Entries (1U << 14) 482 #define RDQ1C_RxVariableSizeQueues (1U << 13) 483 #define RDQ1C_Rx64bitBufferAddresses (1U << 12) 484 #define RDQ1C_Rx64bitDescQueueAddress (1U << 11) 485 #define RDQ1C_RxDescSpacing(x) ((x) << 8) 486 #define RDQ1C_RxQ1ConsumerWe (1U << 7) 487 #define RDQ1C_RxQ1MinDescriptorsThreshold(x) ((x) << 0) 488 489 #define SF_RxDescQueue2Ctrl 0xd8 490 #define RDQ2C_RxQ2BufferLength(x) ((x) << 16) 491 #define RDQ2C_RxDescQ2Entries (1U << 14) 492 #define RDQ2C_RxQ2MinDescriptorsThreshold(x) ((x) << 0) 493 494 #define SF_RxDescQueueHighAddress 0xdc 495 496 #define SF_RxDescQueue1LowAddress 0xe0 497 498 #define SF_RxDescQueue2LowAddress 0xe4 499 500 #define SF_RxDescQueue1Ptrs 0xe8 501 #define RXQ1P_RxDescQ1Consumer(x) ((x) << 16) 502 #define RXQ1P_RxDescQ1Producer(x) ((x) << 0) 503 #define RXQ1P_RxDescQ1Producer_get(x) ((x) & 0x7ff) 504 505 #define SF_RxDescQueue2Ptrs 0xec 506 #define RXQ2P_RxDescQ2Consumer(x) ((x) << 16) 507 #define RXQ2P_RxDescQ2Producer(x) ((x) << 0) 508 509 #define SF_RxDmaStatus 0xf0 510 #define RDS_RxFramesLostCount(x) ((x) & 0xffff) 511 512 #define SF_RxAddressFilteringCtl 0xf4 513 #define RAFC_PerfectAddressPriority(x) (1U << ((x) + 16)) 514 #define RAFC_MinVlanPriority(x) ((x) << 13) 515 #define RAFC_PassMulticastExceptBroadcast (1U << 12) 516 #define RAFC_WakeupMode(x) ((x) << 10) 517 #define RAFC_VlanMode(x) ((x) << 8) 518 #define RAFC_PerfectFilteringMode(x) ((x) << 6) 519 #define RAFC_HashFilteringMode(x) ((x) << 4) 520 #define RAFC_HashPriorityEnable (1U << 3) 521 #define RAFC_PassBroadcast (1U << 2) 522 #define RAFC_PassMulticast (1U << 1) 523 #define RAFC_PromiscuousMode (1U << 0) 524 525 #define SF_RxFrameTestOut 0xf8 526 527 /* 528 * Additional PCI registers. To access these registers via I/O space, 529 * indirect access must be used. 530 */ 531 #define SF_PciTargetStatus 0x100 532 533 #define SF_PciMasterStatus1 0x104 534 535 #define SF_PciMasterStatus2 0x108 536 537 #define SF_PciDmaLowHostAddr 0x10c 538 539 #define SF_BacDmaDiagnostic0 0x110 540 541 #define SF_BacDmaDiagnostic1 0x114 542 543 #define SF_BacDmaDiagnostic2 0x118 544 545 #define SF_BacDmaDiagnostic3 0x11c 546 547 #define SF_MacAddr1 0x120 548 549 #define SF_MacAddr2 0x124 550 551 #define SF_FunctionEvent 0x130 552 553 #define SF_FunctionEventMask 0x134 554 555 #define SF_FunctionPresentState 0x138 556 557 #define SF_ForceFunction 0x13c 558 559 #define SF_EEPROM_BASE 0x1000 560 561 #define SF_MII_BASE 0x2000 562 #define MiiDataValid (1U << 31) 563 #define MiiBusy (1U << 30) 564 #define MiiRegDataPort(x) ((x) & 0xffff) 565 566 #define SF_MII_PHY_REG(p, r) (SF_MII_BASE + \ 567 ((p) * 32 * sizeof(uint32_t)) + \ 568 ((r) * sizeof(uint32_t))) 569 570 #define SF_TestMode 0x4000 571 572 #define SF_RxFrameProcessorCtrl 0x4004 573 574 #define SF_TxFrameProcessorCtrl 0x4008 575 576 #define SF_MacConfig1 0x5000 577 #define MC1_SoftRst (1U << 15) 578 #define MC1_MiiLoopBack (1U << 14) 579 #define MC1_TestMode(x) ((x) << 12) 580 #define MC1_TxFlowEn (1U << 11) 581 #define MC1_RxFlowEn (1U << 10) 582 #define MC1_PreambleDetectCount (1U << 9) 583 #define MC1_PassAllRxPackets (1U << 8) 584 #define MC1_PurePreamble (1U << 7) 585 #define MC1_LengthCheck (1U << 6) 586 #define MC1_NoBackoff (1U << 5) 587 #define MC1_DelayCRC (1U << 4) 588 #define MC1_TxHalfDuplexJam (1U << 3) 589 #define MC1_PadEn (1U << 2) 590 #define MC1_FullDuplex (1U << 1) 591 #define MC1_HugeFrame (1U << 0) 592 593 #define SF_MacConfig2 0x5004 594 #define MC2_TxCRCerr (1U << 15) 595 #define MC2_TxIslCRCerr (1U << 14) 596 #define MC2_RxCRCerr (1U << 13) 597 #define MC2_RxIslCRCerr (1U << 12) 598 #define MC2_TXCF (1U << 11) 599 #define MC2_CtlSoftRst (1U << 10) 600 #define MC2_RxSoftRst (1U << 9) 601 #define MC2_TxSoftRst (1U << 8) 602 #define MC2_RxISLEn (1U << 7) 603 #define MC2_BackPressureNoBackOff (1U << 6) 604 #define MC2_AutoVlanPad (1U << 5) 605 #define MC2_MandatoryVLANPad (1U << 4) 606 #define MC2_TxISLAppen (1U << 3) 607 #define MC2_TxISLEn (1U << 2) 608 #define MC2_SimuRst (1U << 1) 609 #define MC2_TxXmtEn (1U << 0) 610 611 #define SF_BkToBkIPG 0x5008 612 613 #define SF_NonBkToBkIPG 0x500c 614 615 #define SF_ColRetry 0x5010 616 617 #define SF_MaxLength 0x5014 618 619 #define SF_TxNibbleCnt 0x5018 620 621 #define SF_TxByteCnt 0x501c 622 623 #define SF_ReTxCnt 0x5020 624 625 #define SF_RandomNumGen 0x5024 626 627 #define SF_MskRandomNum 0x5028 628 629 #define SF_TotalTxCnt 0x5034 630 631 #define SF_RxByteCnt 0x5040 632 633 #define SF_TxPauseTimer 0x5060 634 635 #define SF_VLANType 0x5064 636 637 #define SF_MiiStatus 0x5070 638 639 #define SF_PERFECT_BASE 0x6000 640 #define SF_PERFECT_SIZE 0x100 641 642 #define SF_HASH_BASE 0x6100 643 #define SF_HASH_SIZE 0x200 644 645 #define SF_STATS_BASE 0x7000 646 struct sf_stats { 647 uint32_t TransmitOKFrames; 648 uint32_t SingleCollisionFrames; 649 uint32_t MultipleCollisionFrames; 650 uint32_t TransmitCRCErrors; 651 uint32_t TransmitOKOctets; 652 uint32_t TransmitDeferredFrames; 653 uint32_t TransmitLateCollisionCount; 654 uint32_t TransmitPauseControlFrames; 655 uint32_t TransmitControlFrames; 656 uint32_t TransmitAbortDueToExcessiveCollisions; 657 uint32_t TransmitAbortDueToExcessingDeferral; 658 uint32_t MulticastFramesTransmittedOK; 659 uint32_t BroadcastFramesTransmittedOK; 660 uint32_t FramesLostDueToInternalTransmitErrors; 661 uint32_t ReceiveOKFrames; 662 uint32_t ReceiveCRCErrors; 663 uint32_t AlignmentErrors; 664 uint32_t ReceiveOKOctets; 665 uint32_t PauseFramesReceivedOK; 666 uint32_t ControlFramesReceivedOK; 667 uint32_t ControlFramesReceivedWithUnsupportedOpcode; 668 uint32_t ReceiveFramesTooLong; 669 uint32_t ReceiveFramesTooShort; 670 uint32_t ReceiveFramesJabbersError; 671 uint32_t ReceiveFramesFragments; 672 uint32_t ReceivePackets64Bytes; 673 uint32_t ReceivePackets127Bytes; 674 uint32_t ReceivePackets255Bytes; 675 uint32_t ReceivePackets511Bytes; 676 uint32_t ReceivePackets1023Bytes; 677 uint32_t ReceivePackets1518Bytes; 678 uint32_t FramesLostDueToInternalReceiveErrors; 679 uint32_t TransmitFifoUnderflowCounts; 680 }; 681 682 #define SF_TxGfpMem 0x8000 683 684 #define SF_RxGfpMem 0xa000 685 686 #endif /* _DEV_IC_AIC6915REG_H_ */ 687