1 /* $NetBSD: aic7xxx.c,v 1.91 2002/09/27 15:37:14 provos Exp $ */ 2 3 /* 4 * Generic driver for the aic7xxx based adaptec SCSI controllers 5 * Product specific probe and attach routines can be found in: 6 * i386/eisa/ahc_eisa.c 27/284X and aic7770 motherboard controllers 7 * pci/ahc_pci.c 3985, 3980, 3940, 2940, aic7895, aic7890, 8 * aic7880, aic7870, aic7860, and aic7850 controllers 9 * cardbus/ahc_cardbus.c aic7860 cardbus controllers 10 * 11 * Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000 Justin T. Gibbs. 12 * All rights reserved. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions, and the following disclaimer, 19 * without modification. 20 * 2. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * Alternatively, this software may be distributed under the terms of the 24 * the GNU Public License ("GPL"). 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 30 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * $FreeBSD: src/sys/dev/aic7xxx/aic7xxx.c,v 1.42 2000/03/18 22:28:18 gibbs Exp $ 39 */ 40 /* 41 * A few notes on features of the driver. 42 * 43 * SCB paging takes advantage of the fact that devices stay disconnected 44 * from the bus a relatively long time and that while they're disconnected, 45 * having the SCBs for these transactions down on the host adapter is of 46 * little use. Instead of leaving this idle SCB down on the card we copy 47 * it back up into kernel memory and reuse the SCB slot on the card to 48 * schedule another transaction. This can be a real payoff when doing random 49 * I/O to tagged queueing devices since there are more transactions active at 50 * once for the device to sort for optimal seek reduction. The algorithm goes 51 * like this... 52 * 53 * The sequencer maintains two lists of its hardware SCBs. The first is the 54 * singly linked free list which tracks all SCBs that are not currently in 55 * use. The second is the doubly linked disconnected list which holds the 56 * SCBs of transactions that are in the disconnected state sorted most 57 * recently disconnected first. When the kernel queues a transaction to 58 * the card, a hardware SCB to "house" this transaction is retrieved from 59 * either of these two lists. If the SCB came from the disconnected list, 60 * a check is made to see if any data transfer or SCB linking (more on linking 61 * in a bit) information has been changed since it was copied from the host 62 * and if so, DMAs the SCB back up before it can be used. Once a hardware 63 * SCB has been obtained, the SCB is DMAed from the host. Before any work 64 * can begin on this SCB, the sequencer must ensure that either the SCB is 65 * for a tagged transaction or the target is not already working on another 66 * non-tagged transaction. If a conflict arises in the non-tagged case, the 67 * sequencer finds the SCB for the active transactions and sets the SCB_LINKED 68 * field in that SCB to this next SCB to execute. To facilitate finding 69 * active non-tagged SCBs, the last four bytes of up to the first four hardware 70 * SCBs serve as a storage area for the currently active SCB ID for each 71 * target. 72 * 73 * When a device reconnects, a search is made of the hardware SCBs to find 74 * the SCB for this transaction. If the search fails, a hardware SCB is 75 * pulled from either the free or disconnected SCB list and the proper 76 * SCB is DMAed from the host. If the MK_MESSAGE control bit is set 77 * in the control byte of the SCB while it was disconnected, the sequencer 78 * will assert ATN and attempt to issue a message to the host. 79 * 80 * When a command completes, a check for non-zero status and residuals is 81 * made. If either of these conditions exists, the SCB is DMAed back up to 82 * the host so that it can interpret this information. Additionally, in the 83 * case of bad status, the sequencer generates a special interrupt and pauses 84 * itself. This allows the host to setup a request sense command if it 85 * chooses for this target synchronously with the error so that sense 86 * information isn't lost. 87 * 88 */ 89 90 #include <sys/cdefs.h> 91 __KERNEL_RCSID(0, "$NetBSD: aic7xxx.c,v 1.91 2002/09/27 15:37:14 provos Exp $"); 92 93 #include "opt_ddb.h" 94 #include "opt_ahc.h" 95 96 #include <sys/param.h> 97 #include <sys/kernel.h> 98 #include <sys/systm.h> 99 #include <sys/device.h> 100 #include <sys/malloc.h> 101 #include <sys/buf.h> 102 #include <sys/proc.h> 103 #include <sys/scsiio.h> 104 105 #include <machine/bus.h> 106 #include <machine/intr.h> 107 108 #include <dev/scsipi/scsi_all.h> 109 #include <dev/scsipi/scsipi_all.h> 110 #include <dev/scsipi/scsi_message.h> 111 #include <dev/scsipi/scsipi_debug.h> 112 #include <dev/scsipi/scsiconf.h> 113 114 #include <uvm/uvm_extern.h> 115 116 #include <dev/ic/aic7xxxvar.h> 117 #include <dev/microcode/aic7xxx/sequencer.h> 118 #include <dev/microcode/aic7xxx/aic7xxx_reg.h> 119 #include <dev/microcode/aic7xxx/aic7xxx_seq.h> 120 121 #define ALL_CHANNELS '\0' 122 #define ALL_TARGETS_MASK 0xFFFF 123 #define INITIATOR_WILDCARD (~0) 124 125 #define SIM_IS_SCSIBUS_B(ahc, periph) \ 126 ((periph)->periph_channel->chan_channel == 1) 127 #define SIM_CHANNEL(ahc, periph) \ 128 (SIM_IS_SCSIBUS_B(ahc, periph) ? 'B' : 'A') 129 #define SIM_SCSI_ID(ahc, periph) \ 130 (SIM_IS_SCSIBUS_B(ahc, periph) ? ahc->our_id_b : ahc->our_id) 131 #define SCB_IS_SCSIBUS_B(scb) \ 132 (((scb)->hscb->tcl & SELBUSB) != 0) 133 #define SCB_TARGET(scb) \ 134 (((scb)->hscb->tcl & TID) >> 4) 135 #define SCB_CHANNEL(scb) \ 136 (SCB_IS_SCSIBUS_B(scb) ? 'B' : 'A') 137 #define SCB_LUN(scb) \ 138 ((scb)->hscb->tcl & LID) 139 #define SCB_TARGET_OFFSET(scb) \ 140 (SCB_TARGET(scb) + (SCB_IS_SCSIBUS_B(scb) ? 8 : 0)) 141 #define SCB_TARGET_MASK(scb) \ 142 (0x01 << (SCB_TARGET_OFFSET(scb))) 143 #define TCL_CHANNEL(ahc, tcl) \ 144 ((((ahc)->features & AHC_TWIN) && ((tcl) & SELBUSB)) ? 'B' : 'A') 145 #define TCL_SCSI_ID(ahc, tcl) \ 146 (TCL_CHANNEL((ahc), (tcl)) == 'B' ? (ahc)->our_id_b : (ahc)->our_id) 147 #define TCL_TARGET(tcl) (((tcl) & TID) >> TCL_TARGET_SHIFT) 148 #define TCL_LUN(tcl) ((tcl) & LID) 149 150 #define XS_TCL(ahc, xs) \ 151 ((((xs)->xs_periph->periph_target << 4) & 0xF0) \ 152 | (SIM_IS_SCSIBUS_B((ahc), (xs)->xs_periph) ? SELBUSB : 0) \ 153 | ((xs)->xs_periph->periph_lun & 0x07)) 154 155 const char * const ahc_chip_names[] = 156 { 157 "NONE", 158 "aic7770", 159 "aic7850", 160 "aic7855", 161 "aic7859", 162 "aic7860", 163 "aic7870", 164 "aic7880", 165 "aic7890/91", 166 "aic7892", 167 "aic7895", 168 "aic7896/97", 169 "aic7899" 170 }; 171 172 typedef enum { 173 ROLE_UNKNOWN, 174 ROLE_INITIATOR, 175 ROLE_TARGET 176 } role_t; 177 178 struct ahc_devinfo { 179 int our_scsiid; 180 int target_offset; 181 u_int16_t target_mask; 182 u_int8_t target; 183 u_int8_t lun; 184 char channel; 185 role_t role; /* 186 * Only guaranteed to be correct if not 187 * in the busfree state. 188 */ 189 }; 190 191 typedef enum { 192 SEARCH_COMPLETE, 193 SEARCH_COUNT, 194 SEARCH_REMOVE 195 } ahc_search_action; 196 197 #ifdef AHC_DEBUG 198 static int ahc_debug = AHC_DEBUG; 199 #endif 200 201 static int ahcinitscbdata(struct ahc_softc *); 202 static void ahcfiniscbdata(struct ahc_softc *); 203 204 #if UNUSED 205 static void ahc_dump_targcmd(struct target_cmd *); 206 #endif 207 static void ahc_shutdown(void *arg); 208 static void ahc_action(struct scsipi_channel *, 209 scsipi_adapter_req_t, void *); 210 static int ahc_ioctl(struct scsipi_channel *, u_long, caddr_t, int, 211 struct proc *); 212 static void ahc_execute_scb(void *, bus_dma_segment_t *, int); 213 static int ahc_poll(struct ahc_softc *, int); 214 static void ahc_setup_data(struct ahc_softc *, struct scsipi_xfer *, 215 struct scb *); 216 static void ahc_freeze_devq(struct ahc_softc *, struct scsipi_periph *); 217 static void ahcallocscbs(struct ahc_softc *); 218 #if UNUSED 219 static void ahc_scb_devinfo(struct ahc_softc *, struct ahc_devinfo *, 220 struct scb *); 221 #endif 222 static void ahc_fetch_devinfo(struct ahc_softc *, struct ahc_devinfo *); 223 static void ahc_compile_devinfo(struct ahc_devinfo *, u_int, u_int, u_int, 224 char, role_t); 225 static u_int ahc_abort_wscb(struct ahc_softc *, u_int, u_int); 226 static void ahc_done(struct ahc_softc *, struct scb *); 227 static struct tmode_tstate * 228 ahc_alloc_tstate(struct ahc_softc *, u_int, char); 229 #if UNUSED 230 static void ahc_free_tstate(struct ahc_softc *, u_int, char, int); 231 #endif 232 static void ahc_handle_seqint(struct ahc_softc *, u_int); 233 static void ahc_handle_scsiint(struct ahc_softc *, u_int); 234 static void ahc_build_transfer_msg(struct ahc_softc *, 235 struct ahc_devinfo *); 236 static void ahc_setup_initiator_msgout(struct ahc_softc *, 237 struct ahc_devinfo *, 238 struct scb *); 239 static void ahc_setup_target_msgin(struct ahc_softc *, 240 struct ahc_devinfo *); 241 static void ahc_clear_msg_state(struct ahc_softc *); 242 static void ahc_handle_message_phase(struct ahc_softc *, 243 struct scsipi_periph *); 244 static int ahc_sent_msg(struct ahc_softc *, u_int, int); 245 246 static int ahc_parse_msg(struct ahc_softc *, struct scsipi_periph *, 247 struct ahc_devinfo *); 248 static void ahc_handle_ign_wide_residue(struct ahc_softc *, 249 struct ahc_devinfo *); 250 static void ahc_handle_devreset(struct ahc_softc *, struct ahc_devinfo *, 251 int, char *, int); 252 #ifdef AHC_DUMP_SEQ 253 static void ahc_dumpseq(struct ahc_softc *); 254 #endif 255 static void ahc_loadseq(struct ahc_softc *); 256 static int ahc_check_patch(struct ahc_softc *, const struct patch **, 257 int, int *); 258 static void ahc_download_instr(struct ahc_softc *, int, u_int8_t *); 259 static int ahc_match_scb(struct scb *, int, char, int, u_int, role_t); 260 #if defined(AHC_DEBUG) 261 static void ahc_print_scb(struct scb *); 262 #endif 263 static int ahc_search_qinfifo(struct ahc_softc *, int, char, int, u_int, 264 role_t, scb_flag, ahc_search_action); 265 static int ahc_reset_channel(struct ahc_softc *, char, int); 266 static int ahc_abort_scbs(struct ahc_softc *, int, char, int, u_int, 267 role_t, int); 268 static int ahc_search_disc_list(struct ahc_softc *, int, 269 char, int, u_int, int, int, int); 270 static u_int ahc_rem_scb_from_disc_list(struct ahc_softc *, u_int, u_int); 271 static void ahc_add_curscb_to_free_list(struct ahc_softc *); 272 static void ahc_clear_intstat(struct ahc_softc *); 273 static void ahc_reset_current_bus(struct ahc_softc *); 274 static const struct ahc_syncrate * 275 ahc_devlimited_syncrate(struct ahc_softc *, u_int *); 276 static const struct ahc_syncrate * 277 ahc_find_syncrate(struct ahc_softc *, u_int *, u_int); 278 static u_int ahc_find_period(struct ahc_softc *, u_int, u_int); 279 static void ahc_validate_offset(struct ahc_softc *, 280 const struct ahc_syncrate *, u_int *, int); 281 static void ahc_update_target_msg_request(struct ahc_softc *, 282 struct ahc_devinfo *, 283 struct ahc_initiator_tinfo *, 284 int, int); 285 static void ahc_set_syncrate(struct ahc_softc *, struct ahc_devinfo *, 286 const struct ahc_syncrate *, u_int, u_int, 287 u_int, int, int); 288 static void ahc_set_width(struct ahc_softc *, struct ahc_devinfo *, 289 u_int, u_int, int, int); 290 static void ahc_set_tags(struct ahc_softc *, struct ahc_devinfo *, int); 291 static void ahc_update_xfer_mode(struct ahc_softc *, struct ahc_devinfo *); 292 static void ahc_construct_sdtr(struct ahc_softc *, u_int, u_int); 293 294 static void ahc_construct_wdtr(struct ahc_softc *, u_int); 295 296 static void ahc_calc_residual(struct scb *); 297 298 static void ahc_update_pending_syncrates(struct ahc_softc *); 299 300 static void ahc_set_recoveryscb(struct ahc_softc *, struct scb *); 301 302 static void ahc_timeout (void *); 303 static __inline int sequencer_paused(struct ahc_softc *); 304 static __inline void pause_sequencer(struct ahc_softc *); 305 static __inline void unpause_sequencer(struct ahc_softc *); 306 static void restart_sequencer(struct ahc_softc *); 307 static __inline u_int ahc_index_busy_tcl(struct ahc_softc *, u_int, int); 308 309 static __inline void ahc_busy_tcl(struct ahc_softc *, struct scb *); 310 static __inline int ahc_isbusy_tcl(struct ahc_softc *, struct scb *); 311 312 static __inline void ahc_freeze_ccb(struct scb *); 313 static __inline void ahcsetccbstatus(struct scsipi_xfer *, int); 314 static void ahc_run_qoutfifo(struct ahc_softc *); 315 316 static __inline struct ahc_initiator_tinfo * 317 ahc_fetch_transinfo(struct ahc_softc *, 318 char, u_int, u_int, 319 struct tmode_tstate **); 320 static void ahcfreescb(struct ahc_softc *, struct scb *); 321 static __inline struct scb *ahcgetscb(struct ahc_softc *); 322 323 static int ahc_createdmamem(bus_dma_tag_t, int, int, bus_dmamap_t *, 324 caddr_t *, bus_addr_t *, bus_dma_segment_t *, 325 int *, const char *, const char *); 326 static void ahc_freedmamem(bus_dma_tag_t, int, bus_dmamap_t, 327 caddr_t, bus_dma_segment_t *, int); 328 static void ahcminphys(struct buf *); 329 330 static __inline void ahc_swap_hscb(struct hardware_scb *); 331 static __inline void ahc_swap_sg(struct ahc_dma_seg *); 332 static int ahc_istagged_device(struct ahc_softc *, struct scsipi_xfer *, int); 333 334 #if defined(AHC_DEBUG) && 0 335 static void ahc_dumptinfo(struct ahc_softc *, struct ahc_initiator_tinfo *); 336 #endif 337 338 static __inline void 339 ahc_swap_hscb(struct hardware_scb *hscb) 340 { 341 hscb->SG_pointer = htole32(hscb->SG_pointer); 342 hscb->data = htole32(hscb->data); 343 hscb->datalen = htole32(hscb->datalen); 344 /* 345 * No need to swap cmdpointer; it's either 0 or set to 346 * cmdstore_busaddr, which is already swapped. 347 */ 348 } 349 350 static __inline void 351 ahc_swap_sg(struct ahc_dma_seg *sg) 352 { 353 sg->addr = htole32(sg->addr); 354 sg->len = htole32(sg->len); 355 } 356 357 static void 358 ahcminphys(bp) 359 struct buf *bp; 360 { 361 /* 362 * Even though the card can transfer up to 16megs per command 363 * we are limited by the number of segments in the dma segment 364 * list that we can hold. The worst case is that all pages are 365 * discontinuous physically, hense the "page per segment" limit 366 * enforced here. 367 */ 368 if (bp->b_bcount > AHC_MAXTRANSFER_SIZE) { 369 bp->b_bcount = AHC_MAXTRANSFER_SIZE; 370 } 371 minphys(bp); 372 } 373 374 375 static __inline u_int32_t 376 ahc_hscb_busaddr(struct ahc_softc *ahc, u_int index) 377 { 378 return (ahc->scb_data->hscb_busaddr 379 + (sizeof(struct hardware_scb) * index)); 380 } 381 382 #define AHC_BUSRESET_DELAY 25 /* Reset delay in us */ 383 384 static __inline int 385 sequencer_paused(struct ahc_softc *ahc) 386 { 387 return ((ahc_inb(ahc, HCNTRL) & PAUSE) != 0); 388 } 389 390 static __inline void 391 pause_sequencer(struct ahc_softc *ahc) 392 { 393 ahc_outb(ahc, HCNTRL, ahc->pause); 394 395 /* 396 * Since the sequencer can disable pausing in a critical section, we 397 * must loop until it actually stops. 398 */ 399 while (sequencer_paused(ahc) == 0) 400 ; 401 } 402 403 static __inline void 404 unpause_sequencer(struct ahc_softc *ahc) 405 { 406 if ((ahc_inb(ahc, INTSTAT) & (SCSIINT | SEQINT | BRKADRINT)) == 0) 407 ahc_outb(ahc, HCNTRL, ahc->unpause); 408 } 409 410 /* 411 * Restart the sequencer program from address zero 412 */ 413 static void 414 restart_sequencer(struct ahc_softc *ahc) 415 { 416 u_int i; 417 418 pause_sequencer(ahc); 419 420 /* 421 * Everytime we restart the sequencer, there 422 * is the possiblitity that we have restarted 423 * within a three instruction window where an 424 * SCB has been marked free but has not made it 425 * onto the free list. Since SCSI events(bus reset, 426 * unexpected bus free) will always freeze the 427 * sequencer, we cannot close this window. To 428 * avoid losing an SCB, we reconsitute the free 429 * list every time we restart the sequencer. 430 */ 431 ahc_outb(ahc, FREE_SCBH, SCB_LIST_NULL); 432 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 433 434 ahc_outb(ahc, SCBPTR, i); 435 if (ahc_inb(ahc, SCB_TAG) == SCB_LIST_NULL) 436 ahc_add_curscb_to_free_list(ahc); 437 } 438 ahc_outb(ahc, SEQCTL, FASTMODE|SEQRESET); 439 unpause_sequencer(ahc); 440 } 441 442 static __inline u_int 443 ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl, int unbusy) 444 { 445 u_int scbid; 446 447 scbid = ahc->untagged_scbs[tcl]; 448 if (unbusy) { 449 ahc->untagged_scbs[tcl] = SCB_LIST_NULL; 450 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 451 UNTAGGEDSCB_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); 452 } 453 454 return (scbid); 455 } 456 457 static __inline void 458 ahc_busy_tcl(struct ahc_softc *ahc, struct scb *scb) 459 { 460 ahc->untagged_scbs[scb->hscb->tcl] = scb->hscb->tag; 461 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 462 UNTAGGEDSCB_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); 463 } 464 465 static __inline int 466 ahc_isbusy_tcl(struct ahc_softc *ahc, struct scb *scb) 467 { 468 return ahc->untagged_scbs[scb->hscb->tcl] != SCB_LIST_NULL; 469 } 470 471 static __inline void 472 ahc_freeze_ccb(struct scb *scb) 473 { 474 struct scsipi_xfer *xs = scb->xs; 475 476 if (!(scb->flags & SCB_FREEZE_QUEUE)) { 477 scsipi_periph_freeze(xs->xs_periph, 1); 478 scb->flags |= SCB_FREEZE_QUEUE; 479 } 480 } 481 482 static __inline void 483 ahcsetccbstatus(struct scsipi_xfer *xs, int status) 484 { 485 xs->error = status; 486 } 487 488 static __inline struct ahc_initiator_tinfo * 489 ahc_fetch_transinfo(struct ahc_softc *ahc, char channel, u_int our_id, 490 u_int remote_id, struct tmode_tstate **tstate) 491 { 492 /* 493 * Transfer data structures are stored from the perspective 494 * of the target role. Since the parameters for a connection 495 * in the initiator role to a given target are the same as 496 * when the roles are reversed, we pretend we are the target. 497 */ 498 if (channel == 'B') 499 our_id += 8; 500 *tstate = ahc->enabled_targets[our_id]; 501 return (&(*tstate)->transinfo[remote_id]); 502 } 503 504 static void 505 ahc_run_qoutfifo(struct ahc_softc *ahc) 506 { 507 struct scb *scb; 508 u_int scb_index; 509 510 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 0, 511 256, BUS_DMASYNC_POSTREAD); 512 513 while (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL) { 514 scb_index = ahc->qoutfifo[ahc->qoutfifonext]; 515 ahc->qoutfifo[ahc->qoutfifonext++] = SCB_LIST_NULL; 516 517 scb = &ahc->scb_data->scbarray[scb_index]; 518 if (scb_index >= ahc->scb_data->numscbs 519 || (scb->flags & SCB_ACTIVE) == 0) { 520 printf("%s: WARNING no command for scb %d " 521 "(cmdcmplt)\nQOUTPOS = %d\n", 522 ahc_name(ahc), scb_index, 523 ahc->qoutfifonext - 1); 524 continue; 525 } 526 527 /* 528 * Save off the residual 529 * if there is one. 530 */ 531 if (scb->hscb->residual_SG_count != 0) 532 ahc_calc_residual(scb); 533 else 534 scb->xs->resid = 0; 535 #ifdef AHC_DEBUG 536 if (ahc_debug & AHC_SHOWSCBS) { 537 scsipi_printaddr(scb->xs->xs_periph); 538 printf("run_qoutfifo: SCB %x complete\n", 539 scb->hscb->tag); 540 } 541 #endif 542 ahc_done(ahc, scb); 543 } 544 } 545 546 547 /* 548 * An scb (and hence an scb entry on the board) is put onto the 549 * free list. 550 */ 551 static void 552 ahcfreescb(struct ahc_softc *ahc, struct scb *scb) 553 { 554 struct hardware_scb *hscb; 555 int opri; 556 557 hscb = scb->hscb; 558 559 #ifdef AHC_DEBUG 560 if (ahc_debug & AHC_SHOWSCBALLOC) 561 printf("%s: free SCB tag %x\n", ahc_name(ahc), hscb->tag); 562 #endif 563 564 opri = splbio(); 565 566 if ((ahc->flags & AHC_RESOURCE_SHORTAGE) != 0 || 567 (scb->flags & SCB_RECOVERY_SCB) != 0) { 568 ahc->flags &= ~AHC_RESOURCE_SHORTAGE; 569 scsipi_channel_thaw(&ahc->sc_channel, 1); 570 if (ahc->features & AHC_TWIN) 571 scsipi_channel_thaw(&ahc->sc_channel_b, 1); 572 } 573 574 /* Clean up for the next user */ 575 scb->flags = SCB_FREE; 576 hscb->control = 0; 577 hscb->status = 0; 578 579 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, scb, links); 580 581 splx(opri); 582 } 583 584 /* 585 * Get a free scb, either one already assigned to a hardware slot 586 * on the adapter or one that will require an SCB to be paged out before 587 * use. If there are none, see if we can allocate a new SCB. Otherwise 588 * either return an error or sleep. 589 */ 590 static __inline struct scb * 591 ahcgetscb(struct ahc_softc *ahc) 592 { 593 struct scb *scbp; 594 int opri;; 595 596 opri = splbio(); 597 if ((scbp = SLIST_FIRST(&ahc->scb_data->free_scbs))) { 598 SLIST_REMOVE_HEAD(&ahc->scb_data->free_scbs, links); 599 } else { 600 ahcallocscbs(ahc); 601 scbp = SLIST_FIRST(&ahc->scb_data->free_scbs); 602 if (scbp != NULL) 603 SLIST_REMOVE_HEAD(&ahc->scb_data->free_scbs, links); 604 } 605 606 splx(opri); 607 608 #ifdef AHC_DEBUG 609 if (ahc_debug & AHC_SHOWSCBALLOC) { 610 if (scbp != NULL) 611 printf("%s: new SCB, tag %x\n", ahc_name(ahc), 612 scbp->hscb->tag); 613 else 614 printf("%s: failed to allocate new SCB\n", 615 ahc_name(ahc)); 616 } 617 #endif 618 619 return (scbp); 620 } 621 622 static int 623 ahc_createdmamem(tag, size, flags, mapp, vaddr, baddr, seg, nseg, myname, what) 624 bus_dma_tag_t tag; 625 int size; 626 int flags; 627 bus_dmamap_t *mapp; 628 caddr_t *vaddr; 629 bus_addr_t *baddr; 630 bus_dma_segment_t *seg; 631 int *nseg; 632 const char *myname, *what; 633 { 634 int error, level = 0; 635 636 if ((error = bus_dmamem_alloc(tag, size, PAGE_SIZE, 0, 637 seg, 1, nseg, BUS_DMA_NOWAIT)) != 0) { 638 printf("%s: failed to allocate DMA mem for %s, error = %d\n", 639 myname, what, error); 640 goto out; 641 } 642 level++; 643 644 if ((error = bus_dmamem_map(tag, seg, *nseg, size, vaddr, 645 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 646 printf("%s: failed to map DMA mem for %s, error = %d\n", 647 myname, what, error); 648 goto out; 649 } 650 level++; 651 652 if ((error = bus_dmamap_create(tag, size, 1, size, 0, 653 BUS_DMA_NOWAIT | flags, mapp)) != 0) { 654 printf("%s: failed to create DMA map for %s, error = %d\n", 655 myname, what, error); 656 goto out; 657 } 658 level++; 659 660 if ((error = bus_dmamap_load(tag, *mapp, *vaddr, size, NULL, 661 BUS_DMA_NOWAIT)) != 0) { 662 printf("%s: failed to load DMA map for %s, error = %d\n", 663 myname, what, error); 664 goto out; 665 } 666 667 *baddr = (*mapp)->dm_segs[0].ds_addr; 668 669 #ifdef AHC_DEBUG 670 printf("%s: dmamem for %s at busaddr %lx virt %lx nseg %d size %d\n", 671 myname, what, (unsigned long)*baddr, (unsigned long)*vaddr, 672 *nseg, size); 673 #endif 674 675 return 0; 676 out: 677 switch (level) { 678 case 3: 679 bus_dmamap_destroy(tag, *mapp); 680 /* FALLTHROUGH */ 681 case 2: 682 bus_dmamem_unmap(tag, *vaddr, size); 683 /* FALLTHROUGH */ 684 case 1: 685 bus_dmamem_free(tag, seg, *nseg); 686 break; 687 default: 688 break; 689 } 690 691 return error; 692 } 693 694 static void 695 ahc_freedmamem(tag, size, map, vaddr, seg, nseg) 696 bus_dma_tag_t tag; 697 int size; 698 bus_dmamap_t map; 699 caddr_t vaddr; 700 bus_dma_segment_t *seg; 701 int nseg; 702 { 703 704 bus_dmamap_unload(tag, map); 705 bus_dmamap_destroy(tag, map); 706 bus_dmamem_unmap(tag, vaddr, size); 707 bus_dmamem_free(tag, seg, nseg); 708 } 709 710 char * 711 ahc_name(struct ahc_softc *ahc) 712 { 713 return (ahc->sc_dev.dv_xname); 714 } 715 716 #ifdef AHC_DEBUG 717 static void 718 ahc_print_scb(struct scb *scb) 719 { 720 struct hardware_scb *hscb = scb->hscb; 721 722 printf("scb:%p tag %x control:0x%x tcl:0x%x cmdlen:%d cmdpointer:0x%lx\n", 723 scb, 724 hscb->tag, 725 hscb->control, 726 hscb->tcl, 727 hscb->cmdlen, 728 (unsigned long)le32toh(hscb->cmdpointer)); 729 printf(" datlen:%u data:0x%lx segs:0x%x segp:0x%lx\n", 730 le32toh(hscb->datalen), 731 (unsigned long)(le32toh(hscb->data)), 732 hscb->SG_count, 733 (unsigned long)(le32toh(hscb->SG_pointer))); 734 printf(" sg_addr:%lx sg_len:%lu\n", 735 (unsigned long)(le32toh(scb->sg_list[0].addr)), 736 (unsigned long)(le32toh(scb->sg_list[0].len))); 737 printf(" cdb:%x %x %x %x %x %x %x %x %x %x %x %x\n", 738 hscb->cmdstore[0], hscb->cmdstore[1], hscb->cmdstore[2], 739 hscb->cmdstore[3], hscb->cmdstore[4], hscb->cmdstore[5], 740 hscb->cmdstore[6], hscb->cmdstore[7], hscb->cmdstore[8], 741 hscb->cmdstore[9], hscb->cmdstore[10], hscb->cmdstore[11]); 742 } 743 #endif 744 745 static const struct { 746 u_int8_t errno; 747 const char *errmesg; 748 } hard_error[] = { 749 { ILLHADDR, "Illegal Host Access" }, 750 { ILLSADDR, "Illegal Sequencer Address referrenced" }, 751 { ILLOPCODE, "Illegal Opcode in sequencer program" }, 752 { SQPARERR, "Sequencer Parity Error" }, 753 { DPARERR, "Data-path Parity Error" }, 754 { MPARERR, "Scratch or SCB Memory Parity Error" }, 755 { PCIERRSTAT, "PCI Error detected" }, 756 { CIOPARERR, "CIOBUS Parity Error" }, 757 }; 758 static const int num_errors = sizeof(hard_error)/sizeof(hard_error[0]); 759 760 static const struct { 761 u_int8_t phase; 762 u_int8_t mesg_out; /* Message response to parity errors */ 763 const char *phasemsg; 764 } phase_table[] = { 765 { P_DATAOUT, MSG_NOOP, "in Data-out phase" }, 766 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" }, 767 { P_COMMAND, MSG_NOOP, "in Command phase" }, 768 { P_MESGOUT, MSG_NOOP, "in Message-out phase" }, 769 { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" }, 770 { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" }, 771 { P_BUSFREE, MSG_NOOP, "while idle" }, 772 { 0, MSG_NOOP, "in unknown phase" } 773 }; 774 static const int num_phases = (sizeof(phase_table)/sizeof(phase_table[0])) - 1; 775 776 /* 777 * Valid SCSIRATE values. (p. 3-17) 778 * Provides a mapping of transfer periods in ns to the proper value to 779 * stick in the scsiscfr reg to use that transfer rate. 780 */ 781 #define AHC_SYNCRATE_DT 0 782 #define AHC_SYNCRATE_ULTRA2 1 783 #define AHC_SYNCRATE_ULTRA 3 784 #define AHC_SYNCRATE_FAST 6 785 static const struct ahc_syncrate ahc_syncrates[] = { 786 /* ultra2 fast/ultra period rate */ 787 { 0x42, 0x000, 9, "80.0" }, 788 { 0x03, 0x000, 10, "40.0" }, 789 { 0x04, 0x000, 11, "33.0" }, 790 { 0x05, 0x100, 12, "20.0" }, 791 { 0x06, 0x110, 15, "16.0" }, 792 { 0x07, 0x120, 18, "13.4" }, 793 { 0x08, 0x000, 25, "10.0" }, 794 { 0x19, 0x010, 31, "8.0" }, 795 { 0x1a, 0x020, 37, "6.67" }, 796 { 0x1b, 0x030, 43, "5.7" }, 797 { 0x1c, 0x040, 50, "5.0" }, 798 { 0x00, 0x050, 56, "4.4" }, 799 { 0x00, 0x060, 62, "4.0" }, 800 { 0x00, 0x070, 68, "3.6" }, 801 { 0x00, 0x000, 0, NULL } 802 }; 803 804 /* 805 * Allocate a controller structure for a new device and initialize it. 806 */ 807 int 808 ahc_alloc(struct ahc_softc *ahc, bus_space_handle_t sh, bus_space_tag_t st, 809 bus_dma_tag_t parent_dmat, ahc_chip chip, ahc_feature features, 810 ahc_flag flags) 811 { 812 struct scb_data *scb_data; 813 814 scb_data = malloc(sizeof (struct scb_data), M_DEVBUF, M_NOWAIT|M_ZERO); 815 if (scb_data == NULL) { 816 printf("%s: cannot malloc softc!\n", ahc_name(ahc)); 817 return -1; 818 } 819 LIST_INIT(&ahc->pending_ccbs); 820 ahc->tag = st; 821 ahc->bsh = sh; 822 ahc->parent_dmat = parent_dmat; 823 ahc->chip = chip; 824 ahc->features = features; 825 ahc->flags = flags; 826 ahc->scb_data = scb_data; 827 828 ahc->unpause = (ahc_inb(ahc, HCNTRL) & IRQMS) | INTEN; 829 /* The IRQMS bit is only valid on VL and EISA chips */ 830 if ((ahc->chip & AHC_PCI) != 0) 831 ahc->unpause &= ~IRQMS; 832 ahc->pause = ahc->unpause | PAUSE; 833 return (0); 834 } 835 836 void 837 ahc_free(ahc) 838 struct ahc_softc *ahc; 839 { 840 ahcfiniscbdata(ahc); 841 if (ahc->init_level != 0) 842 ahc_freedmamem(ahc->parent_dmat, ahc->shared_data_size, 843 ahc->shared_data_dmamap, ahc->qoutfifo, 844 &ahc->shared_data_seg, ahc->shared_data_nseg); 845 846 if (ahc->scb_data != NULL) 847 free(ahc->scb_data, M_DEVBUF); 848 if (ahc->bus_data != NULL) 849 free(ahc->bus_data, M_DEVBUF); 850 return; 851 } 852 853 static int 854 ahcinitscbdata(struct ahc_softc *ahc) 855 { 856 struct scb_data *scb_data; 857 int i; 858 859 scb_data = ahc->scb_data; 860 SLIST_INIT(&scb_data->free_scbs); 861 SLIST_INIT(&scb_data->sg_maps); 862 863 /* Allocate SCB resources */ 864 scb_data->scbarray = 865 (struct scb *)malloc(sizeof(struct scb) * AHC_SCB_MAX, 866 M_DEVBUF, M_NOWAIT|M_ZERO); 867 if (scb_data->scbarray == NULL) 868 return (ENOMEM); 869 870 /* Determine the number of hardware SCBs and initialize them */ 871 872 scb_data->maxhscbs = ahc_probe_scbs(ahc); 873 /* SCB 0 heads the free list */ 874 ahc_outb(ahc, FREE_SCBH, 0); 875 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 876 ahc_outb(ahc, SCBPTR, i); 877 878 /* Clear the control byte. */ 879 ahc_outb(ahc, SCB_CONTROL, 0); 880 881 /* Set the next pointer */ 882 ahc_outb(ahc, SCB_NEXT, i+1); 883 884 /* Make the tag number invalid */ 885 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); 886 } 887 888 /* Make sure that the last SCB terminates the free list */ 889 ahc_outb(ahc, SCBPTR, i-1); 890 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL); 891 892 /* Ensure we clear the 0 SCB's control byte. */ 893 ahc_outb(ahc, SCBPTR, 0); 894 ahc_outb(ahc, SCB_CONTROL, 0); 895 896 scb_data->maxhscbs = i; 897 898 if (ahc->scb_data->maxhscbs == 0) 899 panic("%s: No SCB space found", ahc_name(ahc)); 900 901 /* 902 * Create our DMA tags. These tags define the kinds of device 903 * accessible memory allocations and memory mappings we will 904 * need to perform during normal operation. 905 * 906 * Unless we need to further restrict the allocation, we rely 907 * on the restrictions of the parent dmat, hence the common 908 * use of MAXADDR and MAXSIZE. 909 */ 910 911 if (ahc_createdmamem(ahc->parent_dmat, 912 AHC_SCB_MAX * sizeof(struct hardware_scb), ahc->sc_dmaflags, 913 &scb_data->hscb_dmamap, 914 (caddr_t *)&scb_data->hscbs, &scb_data->hscb_busaddr, 915 &scb_data->hscb_seg, &scb_data->hscb_nseg, ahc_name(ahc), 916 "hardware SCB structures") < 0) 917 goto error_exit; 918 919 scb_data->init_level++; 920 921 if (ahc_createdmamem(ahc->parent_dmat, 922 AHC_SCB_MAX * sizeof(struct scsipi_sense_data), ahc->sc_dmaflags, 923 &scb_data->sense_dmamap, (caddr_t *)&scb_data->sense, 924 &scb_data->sense_busaddr, &scb_data->sense_seg, 925 &scb_data->sense_nseg, ahc_name(ahc), "sense buffers") < 0) 926 goto error_exit; 927 928 scb_data->init_level++; 929 930 /* Perform initial CCB allocation */ 931 memset(scb_data->hscbs, 0, AHC_SCB_MAX * sizeof(struct hardware_scb)); 932 ahcallocscbs(ahc); 933 934 if (scb_data->numscbs == 0) { 935 printf("%s: ahc_init_scb_data - " 936 "Unable to allocate initial scbs\n", 937 ahc_name(ahc)); 938 goto error_exit; 939 } 940 941 scb_data->init_level++; 942 943 /* 944 * Note that we were successfull 945 */ 946 return 0; 947 948 error_exit: 949 950 return ENOMEM; 951 } 952 953 static void 954 ahcfiniscbdata(struct ahc_softc *ahc) 955 { 956 struct scb_data *scb_data; 957 958 scb_data = ahc->scb_data; 959 960 switch (scb_data->init_level) { 961 default: 962 case 3: 963 { 964 struct sg_map_node *sg_map; 965 966 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps))!= NULL) { 967 SLIST_REMOVE_HEAD(&scb_data->sg_maps, links); 968 ahc_freedmamem(ahc->parent_dmat, PAGE_SIZE, 969 sg_map->sg_dmamap, (caddr_t)sg_map->sg_vaddr, 970 &sg_map->sg_dmasegs, sg_map->sg_nseg); 971 free(sg_map, M_DEVBUF); 972 } 973 } 974 /*FALLTHROUGH*/ 975 case 2: 976 ahc_freedmamem(ahc->parent_dmat, 977 AHC_SCB_MAX * sizeof(struct scsipi_sense_data), 978 scb_data->sense_dmamap, (caddr_t)scb_data->sense, 979 &scb_data->sense_seg, scb_data->sense_nseg); 980 /*FALLTHROUGH*/ 981 case 1: 982 ahc_freedmamem(ahc->parent_dmat, 983 AHC_SCB_MAX * sizeof(struct hardware_scb), 984 scb_data->hscb_dmamap, (caddr_t)scb_data->hscbs, 985 &scb_data->hscb_seg, scb_data->hscb_nseg); 986 /*FALLTHROUGH*/ 987 } 988 if (scb_data->scbarray != NULL) 989 free(scb_data->scbarray, M_DEVBUF); 990 } 991 992 int 993 ahc_reset(struct ahc_softc *ahc) 994 { 995 u_int sblkctl; 996 int wait; 997 998 #ifdef AHC_DUMP_SEQ 999 if (ahc->init_level == 0) 1000 ahc_dumpseq(ahc); 1001 #endif 1002 ahc_outb(ahc, HCNTRL, CHIPRST | ahc->pause); 1003 /* 1004 * Ensure that the reset has finished 1005 */ 1006 wait = 1000; 1007 do { 1008 DELAY(1000); 1009 } while (--wait && !(ahc_inb(ahc, HCNTRL) & CHIPRSTACK)); 1010 1011 if (wait == 0) { 1012 printf("%s: WARNING - Failed chip reset! " 1013 "Trying to initialize anyway.\n", ahc_name(ahc)); 1014 } 1015 ahc_outb(ahc, HCNTRL, ahc->pause); 1016 1017 /* Determine channel configuration */ 1018 sblkctl = ahc_inb(ahc, SBLKCTL) & (SELBUSB|SELWIDE); 1019 /* No Twin Channel PCI cards */ 1020 if ((ahc->chip & AHC_PCI) != 0) 1021 sblkctl &= ~SELBUSB; 1022 switch (sblkctl) { 1023 case 0: 1024 /* Single Narrow Channel */ 1025 break; 1026 case 2: 1027 /* Wide Channel */ 1028 ahc->features |= AHC_WIDE; 1029 break; 1030 case 8: 1031 /* Twin Channel */ 1032 ahc->features |= AHC_TWIN; 1033 break; 1034 default: 1035 printf(" Unsupported adapter type. Ignoring\n"); 1036 return(-1); 1037 } 1038 1039 return (0); 1040 } 1041 1042 /* 1043 * Called when we have an active connection to a target on the bus, 1044 * this function finds the nearest syncrate to the input period limited 1045 * by the capabilities of the bus connectivity of the target. 1046 */ 1047 static const struct ahc_syncrate * 1048 ahc_devlimited_syncrate(struct ahc_softc *ahc, u_int *period) { 1049 u_int maxsync; 1050 1051 if ((ahc->features & AHC_ULTRA2) != 0) { 1052 if ((ahc_inb(ahc, SBLKCTL) & ENAB40) != 0 1053 && (ahc_inb(ahc, SSTAT2) & EXP_ACTIVE) == 0) { 1054 maxsync = AHC_SYNCRATE_ULTRA2; 1055 } else { 1056 maxsync = AHC_SYNCRATE_ULTRA; 1057 } 1058 } else if ((ahc->features & AHC_ULTRA) != 0) { 1059 maxsync = AHC_SYNCRATE_ULTRA; 1060 } else { 1061 maxsync = AHC_SYNCRATE_FAST; 1062 } 1063 return (ahc_find_syncrate(ahc, period, maxsync)); 1064 } 1065 1066 /* 1067 * Look up the valid period to SCSIRATE conversion in our table. 1068 * Return the period and offset that should be sent to the target 1069 * if this was the beginning of an SDTR. 1070 */ 1071 static const struct ahc_syncrate * 1072 ahc_find_syncrate(struct ahc_softc *ahc, u_int *period, u_int maxsync) 1073 { 1074 const struct ahc_syncrate *syncrate; 1075 1076 syncrate = &ahc_syncrates[maxsync]; 1077 while ((syncrate->rate != NULL) 1078 && ((ahc->features & AHC_ULTRA2) == 0 1079 || (syncrate->sxfr_u2 != 0))) { 1080 1081 if (*period <= syncrate->period) { 1082 /* 1083 * When responding to a target that requests 1084 * sync, the requested rate may fall between 1085 * two rates that we can output, but still be 1086 * a rate that we can receive. Because of this, 1087 * we want to respond to the target with 1088 * the same rate that it sent to us even 1089 * if the period we use to send data to it 1090 * is lower. Only lower the response period 1091 * if we must. 1092 */ 1093 if (syncrate == &ahc_syncrates[maxsync]) 1094 *period = syncrate->period; 1095 break; 1096 } 1097 syncrate++; 1098 } 1099 1100 if ((*period == 0) 1101 || (syncrate->rate == NULL) 1102 || ((ahc->features & AHC_ULTRA2) != 0 1103 && (syncrate->sxfr_u2 == 0))) { 1104 /* Use asynchronous transfers. */ 1105 *period = 0; 1106 syncrate = NULL; 1107 } 1108 return (syncrate); 1109 } 1110 1111 static u_int 1112 ahc_find_period(struct ahc_softc *ahc, u_int scsirate, u_int maxsync) 1113 { 1114 const struct ahc_syncrate *syncrate; 1115 1116 if ((ahc->features & AHC_ULTRA2) != 0) 1117 scsirate &= SXFR_ULTRA2; 1118 else 1119 scsirate &= SXFR; 1120 1121 syncrate = &ahc_syncrates[maxsync]; 1122 while (syncrate->rate != NULL) { 1123 1124 if ((ahc->features & AHC_ULTRA2) != 0) { 1125 if (syncrate->sxfr_u2 == 0) 1126 break; 1127 else if (scsirate == (syncrate->sxfr_u2 & SXFR_ULTRA2)) 1128 return (syncrate->period); 1129 } else if (scsirate == (syncrate->sxfr & SXFR)) { 1130 return (syncrate->period); 1131 } 1132 syncrate++; 1133 } 1134 return (0); /* async */ 1135 } 1136 1137 static void 1138 ahc_validate_offset(struct ahc_softc *ahc, const struct ahc_syncrate *syncrate, 1139 u_int *offset, int wide) 1140 { 1141 u_int maxoffset; 1142 1143 /* Limit offset to what we can do */ 1144 if (syncrate == NULL) { 1145 maxoffset = 0; 1146 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1147 maxoffset = MAX_OFFSET_ULTRA2; 1148 } else { 1149 if (wide) 1150 maxoffset = MAX_OFFSET_16BIT; 1151 else 1152 maxoffset = MAX_OFFSET_8BIT; 1153 } 1154 *offset = MIN(*offset, maxoffset); 1155 } 1156 1157 static void 1158 ahc_update_target_msg_request(struct ahc_softc *ahc, 1159 struct ahc_devinfo *devinfo, 1160 struct ahc_initiator_tinfo *tinfo, 1161 int force, int paused) 1162 { 1163 u_int targ_msg_req_orig; 1164 1165 targ_msg_req_orig = ahc->targ_msg_req; 1166 if (tinfo->current.period != tinfo->goal.period 1167 || tinfo->current.width != tinfo->goal.width 1168 || tinfo->current.offset != tinfo->goal.offset 1169 || (force 1170 && (tinfo->goal.period != 0 1171 || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT))) { 1172 ahc->targ_msg_req |= devinfo->target_mask; 1173 } else { 1174 ahc->targ_msg_req &= ~devinfo->target_mask; 1175 } 1176 1177 if (ahc->targ_msg_req != targ_msg_req_orig) { 1178 /* Update the message request bit for this target */ 1179 if ((ahc->features & AHC_HS_MAILBOX) != 0) { 1180 if (paused) { 1181 ahc_outb(ahc, TARGET_MSG_REQUEST, 1182 ahc->targ_msg_req & 0xFF); 1183 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 1184 (ahc->targ_msg_req >> 8) & 0xFF); 1185 } else { 1186 ahc_outb(ahc, HS_MAILBOX, 1187 0x01 << HOST_MAILBOX_SHIFT); 1188 } 1189 } else { 1190 if (!paused) 1191 pause_sequencer(ahc); 1192 1193 ahc_outb(ahc, TARGET_MSG_REQUEST, 1194 ahc->targ_msg_req & 0xFF); 1195 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 1196 (ahc->targ_msg_req >> 8) & 0xFF); 1197 1198 if (!paused) 1199 unpause_sequencer(ahc); 1200 } 1201 } 1202 } 1203 1204 static void 1205 ahc_set_syncrate(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 1206 const struct ahc_syncrate *syncrate, 1207 u_int period, u_int offset, u_int type, int paused, int done) 1208 { 1209 struct ahc_initiator_tinfo *tinfo; 1210 struct tmode_tstate *tstate; 1211 u_int old_period; 1212 u_int old_offset; 1213 int active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; 1214 1215 if (syncrate == NULL) { 1216 period = 0; 1217 offset = 0; 1218 } 1219 1220 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1221 devinfo->target, &tstate); 1222 old_period = tinfo->current.period; 1223 old_offset = tinfo->current.offset; 1224 1225 if ((type & AHC_TRANS_CUR) != 0 1226 && (old_period != period || old_offset != offset)) { 1227 u_int scsirate; 1228 1229 scsirate = tinfo->scsirate; 1230 if ((ahc->features & AHC_ULTRA2) != 0) { 1231 1232 /* XXX */ 1233 /* Force single edge until DT is fully implemented */ 1234 scsirate &= ~(SXFR_ULTRA2|SINGLE_EDGE|ENABLE_CRC); 1235 if (syncrate != NULL) 1236 scsirate |= syncrate->sxfr_u2|SINGLE_EDGE; 1237 1238 if (active) 1239 ahc_outb(ahc, SCSIOFFSET, offset); 1240 } else { 1241 1242 scsirate &= ~(SXFR|SOFS); 1243 /* 1244 * Ensure Ultra mode is set properly for 1245 * this target. 1246 */ 1247 tstate->ultraenb &= ~devinfo->target_mask; 1248 if (syncrate != NULL) { 1249 if (syncrate->sxfr & ULTRA_SXFR) { 1250 tstate->ultraenb |= 1251 devinfo->target_mask; 1252 } 1253 scsirate |= syncrate->sxfr & SXFR; 1254 scsirate |= offset & SOFS; 1255 } 1256 if (active) { 1257 u_int sxfrctl0; 1258 1259 sxfrctl0 = ahc_inb(ahc, SXFRCTL0); 1260 sxfrctl0 &= ~FAST20; 1261 if (tstate->ultraenb & devinfo->target_mask) 1262 sxfrctl0 |= FAST20; 1263 ahc_outb(ahc, SXFRCTL0, sxfrctl0); 1264 } 1265 } 1266 if (active) 1267 ahc_outb(ahc, SCSIRATE, scsirate); 1268 1269 tinfo->scsirate = scsirate; 1270 tinfo->current.period = period; 1271 tinfo->current.offset = offset; 1272 1273 /* Update the syncrates in any pending scbs */ 1274 ahc_update_pending_syncrates(ahc); 1275 } 1276 1277 if ((type & AHC_TRANS_GOAL) != 0) { 1278 tinfo->goal.period = period; 1279 tinfo->goal.offset = offset; 1280 } 1281 1282 if ((type & AHC_TRANS_USER) != 0) { 1283 tinfo->user.period = period; 1284 tinfo->user.offset = offset; 1285 } 1286 1287 ahc_update_target_msg_request(ahc, devinfo, tinfo, 1288 /*force*/FALSE, 1289 paused); 1290 } 1291 1292 static void 1293 ahc_set_width(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 1294 u_int width, u_int type, int paused, int done) 1295 { 1296 struct ahc_initiator_tinfo *tinfo; 1297 struct tmode_tstate *tstate; 1298 u_int oldwidth; 1299 int active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; 1300 1301 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1302 devinfo->target, &tstate); 1303 oldwidth = tinfo->current.width; 1304 1305 if ((type & AHC_TRANS_CUR) != 0 && oldwidth != width) { 1306 u_int scsirate; 1307 1308 scsirate = tinfo->scsirate; 1309 scsirate &= ~WIDEXFER; 1310 if (width == MSG_EXT_WDTR_BUS_16_BIT) 1311 scsirate |= WIDEXFER; 1312 1313 tinfo->scsirate = scsirate; 1314 1315 if (active) 1316 ahc_outb(ahc, SCSIRATE, scsirate); 1317 1318 tinfo->current.width = width; 1319 } 1320 1321 if ((type & AHC_TRANS_GOAL) != 0) 1322 tinfo->goal.width = width; 1323 if ((type & AHC_TRANS_USER) != 0) 1324 tinfo->user.width = width; 1325 1326 ahc_update_target_msg_request(ahc, devinfo, tinfo, 1327 /*force*/FALSE, paused); 1328 } 1329 1330 static void 1331 ahc_set_tags(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, int enable) 1332 { 1333 #ifndef AHC_NO_TAGS 1334 struct ahc_initiator_tinfo *tinfo; 1335 struct tmode_tstate *tstate; 1336 1337 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1338 devinfo->target, &tstate); 1339 1340 if (enable) { 1341 tstate->tagenable |= devinfo->target_mask; 1342 } else { 1343 tstate->tagenable &= ~devinfo->target_mask; 1344 tstate->tagdisable |= devinfo->target_mask; 1345 } 1346 #endif 1347 } 1348 1349 static void 1350 ahc_update_xfer_mode(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 1351 { 1352 struct scsipi_xfer_mode xm; 1353 struct ahc_initiator_tinfo *tinfo; 1354 struct tmode_tstate *tstate; 1355 1356 if (ahc->inited_targets[devinfo->target] != 2) 1357 return; 1358 1359 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1360 devinfo->target, &tstate); 1361 1362 xm.xm_target = devinfo->target; 1363 xm.xm_mode = 0; 1364 xm.xm_period = tinfo->current.period; 1365 xm.xm_offset = tinfo->current.offset; 1366 if (tinfo->current.width == 1) 1367 xm.xm_mode |= PERIPH_CAP_WIDE16; 1368 if (tinfo->current.period) 1369 xm.xm_mode |= PERIPH_CAP_SYNC; 1370 if (tstate->tagenable & devinfo->target_mask) 1371 xm.xm_mode |= PERIPH_CAP_TQING; 1372 scsipi_async_event( 1373 devinfo->channel == 'B' ? &ahc->sc_channel_b : &ahc->sc_channel, 1374 ASYNC_EVENT_XFER_MODE, &xm); 1375 } 1376 1377 /* 1378 * Attach all the sub-devices we can find 1379 */ 1380 int 1381 ahc_attach(struct ahc_softc *ahc) 1382 { 1383 ahc->sc_adapter.adapt_dev = &ahc->sc_dev; 1384 ahc->sc_adapter.adapt_nchannels = (ahc->features & AHC_TWIN) ? 2 : 1; 1385 if (ahc->flags & AHC_PAGESCBS) { 1386 ahc->sc_adapter.adapt_openings = AHC_SCB_MAX; 1387 ahc->sc_adapter.adapt_max_periph = 16; 1388 } else { 1389 ahc->sc_adapter.adapt_openings = ahc->scb_data->maxhscbs; 1390 if (ahc->scb_data->maxhscbs >= 16) 1391 ahc->sc_adapter.adapt_max_periph = 16; 1392 else 1393 ahc->sc_adapter.adapt_max_periph = 4; 1394 } 1395 ahc->sc_adapter.adapt_ioctl = ahc_ioctl; 1396 ahc->sc_adapter.adapt_minphys = ahcminphys; 1397 ahc->sc_adapter.adapt_request = ahc_action; 1398 1399 ahc->sc_channel.chan_adapter = &ahc->sc_adapter; 1400 ahc->sc_channel.chan_bustype = &scsi_bustype; 1401 ahc->sc_channel.chan_channel = 0; 1402 ahc->sc_channel.chan_ntargets = (ahc->features & AHC_WIDE) ? 16 : 8; 1403 ahc->sc_channel.chan_nluns = 8; 1404 ahc->sc_channel.chan_id = ahc->our_id; 1405 1406 if (ahc->features & AHC_TWIN) { 1407 ahc->sc_channel_b = ahc->sc_channel; 1408 ahc->sc_channel_b.chan_id = ahc->our_id_b; 1409 ahc->sc_channel_b.chan_channel = 1; 1410 } 1411 1412 if ((ahc->flags & AHC_CHANNEL_B_PRIMARY) == 0) { 1413 ahc->child = config_found((void *)ahc, &ahc->sc_channel, scsiprint); 1414 if (ahc->features & AHC_TWIN) 1415 ahc->child = config_found((void *)ahc, &ahc->sc_channel_b, 1416 scsiprint); 1417 } else { 1418 ahc->child = config_found((void *)ahc, &ahc->sc_channel_b, scsiprint); 1419 ahc->child = config_found((void *)ahc, &ahc->sc_channel, scsiprint); 1420 } 1421 return 1; 1422 } 1423 1424 int 1425 ahc_detach(struct ahc_softc *ahc, int flags) 1426 { 1427 int rv = 0; 1428 1429 if (ahc->child != NULL) 1430 rv = config_detach(ahc->child, flags); 1431 1432 ahc_free(ahc); 1433 1434 return (rv); 1435 } 1436 1437 int 1438 ahc_activate(struct device *self, enum devact act) 1439 { 1440 struct ahc_softc *ahc = (void *) self; 1441 int s, rv = 0; 1442 1443 s = splhigh(); 1444 switch (act) { 1445 case DVACT_ACTIVATE: 1446 rv = EOPNOTSUPP; 1447 break; 1448 1449 case DVACT_DEACTIVATE: 1450 if (ahc->child != NULL) 1451 rv = config_deactivate(ahc->child); 1452 break; 1453 } 1454 splx(s); 1455 1456 return (rv); 1457 } 1458 1459 static void 1460 ahc_fetch_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 1461 { 1462 u_int saved_tcl; 1463 role_t role; 1464 int our_id; 1465 1466 if (ahc_inb(ahc, SSTAT0) & TARGET) 1467 role = ROLE_TARGET; 1468 else 1469 role = ROLE_INITIATOR; 1470 1471 if (role == ROLE_TARGET 1472 && (ahc->features & AHC_MULTI_TID) != 0 1473 && (ahc_inb(ahc, SEQ_FLAGS) & CMDPHASE_PENDING) != 0) { 1474 /* We were selected, so pull our id from TARGIDIN */ 1475 our_id = ahc_inb(ahc, TARGIDIN) & OID; 1476 } else if ((ahc->features & AHC_ULTRA2) != 0) 1477 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 1478 else 1479 our_id = ahc_inb(ahc, SCSIID) & OID; 1480 1481 saved_tcl = ahc_inb(ahc, SAVED_TCL); 1482 ahc_compile_devinfo(devinfo, our_id, TCL_TARGET(saved_tcl), 1483 TCL_LUN(saved_tcl), TCL_CHANNEL(ahc, saved_tcl), 1484 role); 1485 } 1486 1487 static void 1488 ahc_compile_devinfo(struct ahc_devinfo *devinfo, u_int our_id, u_int target, 1489 u_int lun, char channel, role_t role) 1490 { 1491 devinfo->our_scsiid = our_id; 1492 devinfo->target = target; 1493 devinfo->lun = lun; 1494 devinfo->target_offset = target; 1495 devinfo->channel = channel; 1496 devinfo->role = role; 1497 if (channel == 'B') 1498 devinfo->target_offset += 8; 1499 devinfo->target_mask = (0x01 << devinfo->target_offset); 1500 } 1501 1502 /* 1503 * Catch an interrupt from the adapter 1504 */ 1505 int 1506 ahc_intr(void *arg) 1507 { 1508 struct ahc_softc *ahc; 1509 u_int intstat; 1510 1511 ahc = (struct ahc_softc *)arg; 1512 1513 intstat = ahc_inb(ahc, INTSTAT); 1514 1515 /* 1516 * Any interrupts to process? 1517 */ 1518 if ((intstat & INT_PEND) == 0) { 1519 if (ahc->bus_intr && ahc->bus_intr(ahc)) { 1520 #ifdef AHC_DEBUG 1521 printf("%s: bus intr: CCHADDR %x HADDR %x SEQADDR %x\n", 1522 ahc_name(ahc), 1523 ahc_inb(ahc, CCHADDR) | 1524 (ahc_inb(ahc, CCHADDR+1) << 8) 1525 | (ahc_inb(ahc, CCHADDR+2) << 16) 1526 | (ahc_inb(ahc, CCHADDR+3) << 24), 1527 ahc_inb(ahc, HADDR) | (ahc_inb(ahc, HADDR+1) << 8) 1528 | (ahc_inb(ahc, HADDR+2) << 16) 1529 | (ahc_inb(ahc, HADDR+3) << 24), 1530 ahc_inb(ahc, SEQADDR0) | 1531 (ahc_inb(ahc, SEQADDR1) << 8)); 1532 #endif 1533 return 1; 1534 } 1535 return 0; 1536 } 1537 1538 #ifdef AHC_DEBUG 1539 if (ahc_debug & AHC_SHOWINTR) { 1540 printf("%s: intstat %x\n", ahc_name(ahc), intstat); 1541 } 1542 #endif 1543 1544 if (intstat & CMDCMPLT) { 1545 ahc_outb(ahc, CLRINT, CLRCMDINT); 1546 ahc_run_qoutfifo(ahc); 1547 } 1548 if (intstat & BRKADRINT) { 1549 /* 1550 * We upset the sequencer :-( 1551 * Lookup the error message 1552 */ 1553 int i, error; 1554 1555 error = ahc_inb(ahc, ERROR); 1556 for (i = 0; error != 1 && i < num_errors; i++) 1557 error >>= 1; 1558 panic("%s: brkadrint, %s at seqaddr = 0x%x", 1559 ahc_name(ahc), hard_error[i].errmesg, 1560 ahc_inb(ahc, SEQADDR0) | 1561 (ahc_inb(ahc, SEQADDR1) << 8)); 1562 1563 /* Tell everyone that this HBA is no longer available */ 1564 ahc_abort_scbs(ahc, AHC_TARGET_WILDCARD, ALL_CHANNELS, 1565 AHC_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN, 1566 XS_DRIVER_STUFFUP); 1567 } 1568 if (intstat & SEQINT) 1569 ahc_handle_seqint(ahc, intstat); 1570 1571 if (intstat & SCSIINT) 1572 ahc_handle_scsiint(ahc, intstat); 1573 1574 return 1; 1575 } 1576 1577 static struct tmode_tstate * 1578 ahc_alloc_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel) 1579 { 1580 struct tmode_tstate *master_tstate; 1581 struct tmode_tstate *tstate; 1582 int i, s; 1583 1584 master_tstate = ahc->enabled_targets[ahc->our_id]; 1585 if (channel == 'B') { 1586 scsi_id += 8; 1587 master_tstate = ahc->enabled_targets[ahc->our_id_b + 8]; 1588 } 1589 if (ahc->enabled_targets[scsi_id] != NULL 1590 && ahc->enabled_targets[scsi_id] != master_tstate) 1591 panic("%s: ahc_alloc_tstate - Target already allocated", 1592 ahc_name(ahc)); 1593 tstate = malloc(sizeof(*tstate), M_DEVBUF, M_NOWAIT); 1594 if (tstate == NULL) 1595 return (NULL); 1596 1597 /* 1598 * If we have allocated a master tstate, copy user settings from 1599 * the master tstate (taken from SRAM or the EEPROM) for this 1600 * channel, but reset our current and goal settings to async/narrow 1601 * until an initiator talks to us. 1602 */ 1603 if (master_tstate != NULL) { 1604 memcpy(tstate, master_tstate, sizeof(*tstate)); 1605 tstate->ultraenb = 0; 1606 for (i = 0; i < 16; i++) { 1607 memset(&tstate->transinfo[i].current, 0, 1608 sizeof(tstate->transinfo[i].current)); 1609 memset(&tstate->transinfo[i].goal, 0, 1610 sizeof(tstate->transinfo[i].goal)); 1611 } 1612 } else 1613 memset(tstate, 0, sizeof(*tstate)); 1614 s = splbio(); 1615 ahc->enabled_targets[scsi_id] = tstate; 1616 splx(s); 1617 return (tstate); 1618 } 1619 1620 #if UNUSED 1621 static void 1622 ahc_free_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel, int force) 1623 { 1624 struct tmode_tstate *tstate; 1625 1626 /* Don't clean up the entry for our initiator role */ 1627 if ((ahc->flags & AHC_INITIATORMODE) != 0 1628 && ((channel == 'B' && scsi_id == ahc->our_id_b) 1629 || (channel == 'A' && scsi_id == ahc->our_id)) 1630 && force == FALSE) 1631 return; 1632 1633 if (channel == 'B') 1634 scsi_id += 8; 1635 tstate = ahc->enabled_targets[scsi_id]; 1636 if (tstate != NULL) 1637 free(tstate, M_DEVBUF); 1638 ahc->enabled_targets[scsi_id] = NULL; 1639 } 1640 #endif 1641 1642 static void 1643 ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat) 1644 { 1645 struct scb *scb; 1646 struct ahc_devinfo devinfo; 1647 1648 ahc_fetch_devinfo(ahc, &devinfo); 1649 1650 /* 1651 * Clear the upper byte that holds SEQINT status 1652 * codes and clear the SEQINT bit. We will unpause 1653 * the sequencer, if appropriate, after servicing 1654 * the request. 1655 */ 1656 ahc_outb(ahc, CLRINT, CLRSEQINT); 1657 switch (intstat & SEQINT_MASK) { 1658 case NO_MATCH: 1659 { 1660 /* Ensure we don't leave the selection hardware on */ 1661 ahc_outb(ahc, SCSISEQ, 1662 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 1663 1664 printf("%s:%c:%d: no active SCB for reconnecting " 1665 "target - issuing BUS DEVICE RESET\n", 1666 ahc_name(ahc), devinfo.channel, devinfo.target); 1667 printf("SAVED_TCL == 0x%x, ARG_1 == 0x%x, SEQ_FLAGS == 0x%x\n", 1668 ahc_inb(ahc, SAVED_TCL), ahc_inb(ahc, ARG_1), 1669 ahc_inb(ahc, SEQ_FLAGS)); 1670 ahc->msgout_buf[0] = MSG_BUS_DEV_RESET; 1671 ahc->msgout_len = 1; 1672 ahc->msgout_index = 0; 1673 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 1674 ahc_outb(ahc, MSG_OUT, HOST_MSG); 1675 ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, LASTPHASE) | ATNO); 1676 break; 1677 } 1678 case UPDATE_TMSG_REQ: 1679 ahc_outb(ahc, TARGET_MSG_REQUEST, ahc->targ_msg_req & 0xFF); 1680 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 1681 (ahc->targ_msg_req >> 8) & 0xFF); 1682 ahc_outb(ahc, HS_MAILBOX, 0); 1683 break; 1684 case SEND_REJECT: 1685 { 1686 u_int rejbyte = ahc_inb(ahc, ACCUM); 1687 printf("%s:%c:%d: Warning - unknown message received from " 1688 "target (0x%x). Rejecting\n", 1689 ahc_name(ahc), devinfo.channel, devinfo.target, rejbyte); 1690 break; 1691 } 1692 case NO_IDENT: 1693 { 1694 /* 1695 * The reconnecting target either did not send an identify 1696 * message, or did, but we didn't find and SCB to match and 1697 * before it could respond to our ATN/abort, it hit a dataphase. 1698 * The only safe thing to do is to blow it away with a bus 1699 * reset. 1700 */ 1701 int found; 1702 1703 printf("%s:%c:%d: Target did not send an IDENTIFY message. " 1704 "LASTPHASE = 0x%x, SAVED_TCL == 0x%x\n", 1705 ahc_name(ahc), devinfo.channel, devinfo.target, 1706 ahc_inb(ahc, LASTPHASE), ahc_inb(ahc, SAVED_TCL)); 1707 found = ahc_reset_channel(ahc, devinfo.channel, 1708 /*initiate reset*/TRUE); 1709 printf("%s: Issued Channel %c Bus Reset. " 1710 "%d SCBs aborted\n", ahc_name(ahc), devinfo.channel, 1711 found); 1712 return; 1713 } 1714 case BAD_PHASE: 1715 { 1716 u_int lastphase; 1717 1718 lastphase = ahc_inb(ahc, LASTPHASE); 1719 if (lastphase == P_BUSFREE) { 1720 printf("%s:%c:%d: Missed busfree. Curphase = 0x%x\n", 1721 ahc_name(ahc), devinfo.channel, devinfo.target, 1722 ahc_inb(ahc, SCSISIGI)); 1723 restart_sequencer(ahc); 1724 return; 1725 } else { 1726 printf("%s:%c:%d: unknown scsi bus phase %x. " 1727 "Attempting to continue\n", 1728 ahc_name(ahc), devinfo.channel, devinfo.target, 1729 ahc_inb(ahc, SCSISIGI)); 1730 } 1731 break; 1732 } 1733 case BAD_STATUS: 1734 { 1735 u_int scb_index; 1736 struct hardware_scb *hscb; 1737 struct scsipi_xfer *xs; 1738 /* 1739 * The sequencer will notify us when a command 1740 * has an error that would be of interest to 1741 * the kernel. This allows us to leave the sequencer 1742 * running in the common case of command completes 1743 * without error. The sequencer will already have 1744 * dma'd the SCB back up to us, so we can reference 1745 * the in kernel copy directly. 1746 */ 1747 scb_index = ahc_inb(ahc, SCB_TAG); 1748 scb = &ahc->scb_data->scbarray[scb_index]; 1749 1750 /* ahc_print_scb(scb); */ 1751 1752 /* 1753 * Set the default return value to 0 (don't 1754 * send sense). The sense code will change 1755 * this if needed. 1756 */ 1757 ahc_outb(ahc, RETURN_1, 0); 1758 if (!(scb_index < ahc->scb_data->numscbs 1759 && (scb->flags & SCB_ACTIVE) != 0)) { 1760 printf("%s:%c:%d: ahc_intr - referenced scb " 1761 "not valid during seqint 0x%x scb(%d)\n", 1762 ahc_name(ahc), devinfo.channel, 1763 devinfo.target, intstat, scb_index); 1764 goto unpause; 1765 } 1766 1767 hscb = scb->hscb; 1768 xs = scb->xs; 1769 1770 /* Don't want to clobber the original sense code */ 1771 if ((scb->flags & SCB_SENSE) != 0) { 1772 /* 1773 * Clear the SCB_SENSE Flag and have 1774 * the sequencer do a normal command 1775 * complete. 1776 */ 1777 scb->flags &= ~SCB_SENSE; 1778 ahcsetccbstatus(xs, XS_DRIVER_STUFFUP); 1779 break; 1780 } 1781 /* Freeze the queue unit the client sees the error. */ 1782 ahc_freeze_devq(ahc, xs->xs_periph); 1783 ahc_freeze_ccb(scb); 1784 xs->status = hscb->status; 1785 switch (hscb->status) { 1786 case SCSI_STATUS_OK: 1787 printf("%s: Interrupted for status of 0???\n", 1788 ahc_name(ahc)); 1789 break; 1790 case SCSI_STATUS_CMD_TERMINATED: 1791 case SCSI_STATUS_CHECK_COND: 1792 #if defined(AHC_DEBUG) 1793 if (ahc_debug & AHC_SHOWSENSE) { 1794 scsipi_printaddr(xs->xs_periph); 1795 printf("Check Status, resid %d datalen %d\n", 1796 xs->resid, xs->datalen); 1797 } 1798 #endif 1799 1800 if (xs->error == XS_NOERROR && 1801 !(scb->flags & SCB_SENSE)) { 1802 struct ahc_dma_seg *sg; 1803 struct scsipi_sense *sc; 1804 struct ahc_initiator_tinfo *tinfo; 1805 struct tmode_tstate *tstate; 1806 1807 sg = scb->sg_list; 1808 sc = (struct scsipi_sense *)(&hscb->cmdstore); 1809 /* 1810 * Save off the residual if there is one. 1811 */ 1812 if (hscb->residual_SG_count != 0) 1813 ahc_calc_residual(scb); 1814 else 1815 xs->resid = 0; 1816 1817 #ifdef AHC_DEBUG 1818 if (ahc_debug & AHC_SHOWSENSE) { 1819 scsipi_printaddr(xs->xs_periph); 1820 printf("Sending Sense\n"); 1821 } 1822 #endif 1823 sg->addr = ahc->scb_data->sense_busaddr + 1824 (hscb->tag*sizeof(struct scsipi_sense_data)); 1825 sg->len = sizeof (struct scsipi_sense_data); 1826 1827 sc->opcode = REQUEST_SENSE; 1828 sc->byte2 = SCB_LUN(scb) << 5; 1829 sc->unused[0] = 0; 1830 sc->unused[1] = 0; 1831 sc->length = sg->len; 1832 sc->control = 0; 1833 1834 /* 1835 * Would be nice to preserve DISCENB here, 1836 * but due to the way we page SCBs, we can't. 1837 */ 1838 hscb->control = 0; 1839 1840 /* 1841 * This request sense could be because the 1842 * the device lost power or in some other 1843 * way has lost our transfer negotiations. 1844 * Renegotiate if appropriate. Unit attention 1845 * errors will be reported before any data 1846 * phases occur. 1847 */ 1848 ahc_calc_residual(scb); 1849 #if defined(AHC_DEBUG) 1850 if (ahc_debug & AHC_SHOWSENSE) { 1851 scsipi_printaddr(xs->xs_periph); 1852 printf("Sense: datalen %d resid %d" 1853 "chan %d id %d targ %d\n", 1854 xs->datalen, xs->resid, 1855 devinfo.channel, devinfo.our_scsiid, 1856 devinfo.target); 1857 } 1858 #endif 1859 if (xs->datalen > 0 && 1860 xs->resid == xs->datalen) { 1861 tinfo = ahc_fetch_transinfo(ahc, 1862 devinfo.channel, 1863 devinfo.our_scsiid, 1864 devinfo.target, 1865 &tstate); 1866 ahc_update_target_msg_request(ahc, 1867 &devinfo, 1868 tinfo, 1869 /*force*/TRUE, 1870 /*paused*/TRUE); 1871 } 1872 hscb->status = 0; 1873 hscb->SG_count = 1; 1874 hscb->SG_pointer = scb->sg_list_phys; 1875 hscb->data = sg->addr; 1876 hscb->datalen = sg->len; 1877 hscb->cmdpointer = hscb->cmdstore_busaddr; 1878 hscb->cmdlen = sizeof(*sc); 1879 scb->sg_count = hscb->SG_count; 1880 ahc_swap_hscb(hscb); 1881 ahc_swap_sg(scb->sg_list); 1882 scb->flags |= SCB_SENSE; 1883 /* 1884 * Ensure the target is busy since this 1885 * will be an untagged request. 1886 */ 1887 ahc_busy_tcl(ahc, scb); 1888 ahc_outb(ahc, RETURN_1, SEND_SENSE); 1889 1890 /* 1891 * Ensure we have enough time to actually 1892 * retrieve the sense. 1893 */ 1894 if (!(scb->xs->xs_control & XS_CTL_POLL)) { 1895 callout_reset(&scb->xs->xs_callout, 1896 5 * hz, ahc_timeout, scb); 1897 } 1898 } 1899 break; 1900 case SCSI_STATUS_QUEUE_FULL: 1901 case SCSI_STATUS_BUSY: 1902 xs->error = XS_BUSY; 1903 break; 1904 } 1905 break; 1906 } 1907 case TRACE_POINT: 1908 { 1909 printf("SSTAT2 = 0x%x DFCNTRL = 0x%x\n", ahc_inb(ahc, SSTAT2), 1910 ahc_inb(ahc, DFCNTRL)); 1911 printf("SSTAT3 = 0x%x DSTATUS = 0x%x\n", ahc_inb(ahc, SSTAT3), 1912 ahc_inb(ahc, DFSTATUS)); 1913 printf("SSTAT0 = 0x%x, SCB_DATACNT = 0x%x\n", 1914 ahc_inb(ahc, SSTAT0), 1915 ahc_inb(ahc, SCB_DATACNT)); 1916 break; 1917 } 1918 case HOST_MSG_LOOP: 1919 { 1920 /* 1921 * The sequencer has encountered a message phase 1922 * that requires host assistance for completion. 1923 * While handling the message phase(s), we will be 1924 * notified by the sequencer after each byte is 1925 * transferred so we can track bus phases. 1926 * 1927 * If this is the first time we've seen a HOST_MSG_LOOP, 1928 * initialize the state of the host message loop. 1929 */ 1930 if (ahc->msg_type == MSG_TYPE_NONE) { 1931 u_int bus_phase; 1932 1933 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 1934 if (bus_phase != P_MESGIN 1935 && bus_phase != P_MESGOUT) { 1936 printf("ahc_intr: HOST_MSG_LOOP bad " 1937 "phase 0x%x\n", 1938 bus_phase); 1939 /* 1940 * Probably transitioned to bus free before 1941 * we got here. Just punt the message. 1942 */ 1943 ahc_clear_intstat(ahc); 1944 restart_sequencer(ahc); 1945 } 1946 1947 if (devinfo.role == ROLE_INITIATOR) { 1948 struct scb *scb; 1949 u_int scb_index; 1950 1951 scb_index = ahc_inb(ahc, SCB_TAG); 1952 scb = &ahc->scb_data->scbarray[scb_index]; 1953 1954 if (bus_phase == P_MESGOUT) 1955 ahc_setup_initiator_msgout(ahc, 1956 &devinfo, 1957 scb); 1958 else { 1959 ahc->msg_type = 1960 MSG_TYPE_INITIATOR_MSGIN; 1961 ahc->msgin_index = 0; 1962 } 1963 } else { 1964 if (bus_phase == P_MESGOUT) { 1965 ahc->msg_type = 1966 MSG_TYPE_TARGET_MSGOUT; 1967 ahc->msgin_index = 0; 1968 } else 1969 /* XXX Ever executed??? */ 1970 ahc_setup_target_msgin(ahc, &devinfo); 1971 } 1972 } 1973 1974 /* Pass a NULL path so that handlers generate their own */ 1975 ahc_handle_message_phase(ahc, /*path*/NULL); 1976 break; 1977 } 1978 case PERR_DETECTED: 1979 { 1980 /* 1981 * If we've cleared the parity error interrupt 1982 * but the sequencer still believes that SCSIPERR 1983 * is true, it must be that the parity error is 1984 * for the currently presented byte on the bus, 1985 * and we are not in a phase (data-in) where we will 1986 * eventually ack this byte. Ack the byte and 1987 * throw it away in the hope that the target will 1988 * take us to message out to deliver the appropriate 1989 * error message. 1990 */ 1991 if ((intstat & SCSIINT) == 0 1992 && (ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0) { 1993 u_int curphase; 1994 1995 /* 1996 * The hardware will only let you ack bytes 1997 * if the expected phase in SCSISIGO matches 1998 * the current phase. Make sure this is 1999 * currently the case. 2000 */ 2001 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 2002 ahc_outb(ahc, LASTPHASE, curphase); 2003 ahc_outb(ahc, SCSISIGO, curphase); 2004 ahc_inb(ahc, SCSIDATL); 2005 } 2006 break; 2007 } 2008 case DATA_OVERRUN: 2009 { 2010 /* 2011 * When the sequencer detects an overrun, it 2012 * places the controller in "BITBUCKET" mode 2013 * and allows the target to complete its transfer. 2014 * Unfortunately, none of the counters get updated 2015 * when the controller is in this mode, so we have 2016 * no way of knowing how large the overrun was. 2017 */ 2018 u_int scbindex = ahc_inb(ahc, SCB_TAG); 2019 u_int lastphase = ahc_inb(ahc, LASTPHASE); 2020 int i; 2021 2022 scb = &ahc->scb_data->scbarray[scbindex]; 2023 for (i = 0; i < num_phases; i++) { 2024 if (lastphase == phase_table[i].phase) 2025 break; 2026 } 2027 scsipi_printaddr(scb->xs->xs_periph); 2028 printf("data overrun detected %s." 2029 " Tag == 0x%x.\n", 2030 phase_table[i].phasemsg, 2031 scb->hscb->tag); 2032 scsipi_printaddr(scb->xs->xs_periph); 2033 printf("%s seen Data Phase. Length = %d. NumSGs = %d.\n", 2034 ahc_inb(ahc, SEQ_FLAGS) & DPHASE ? "Have" : "Haven't", 2035 scb->xs->datalen, scb->sg_count); 2036 if (scb->sg_count > 0) { 2037 for (i = 0; i < scb->sg_count; i++) { 2038 printf("sg[%d] - Addr 0x%x : Length %d\n", 2039 i, 2040 le32toh(scb->sg_list[i].addr), 2041 le32toh(scb->sg_list[i].len)); 2042 } 2043 } 2044 /* 2045 * Set this and it will take affect when the 2046 * target does a command complete. 2047 */ 2048 ahc_freeze_devq(ahc, scb->xs->xs_periph); 2049 ahcsetccbstatus(scb->xs, XS_DRIVER_STUFFUP); 2050 ahc_freeze_ccb(scb); 2051 break; 2052 } 2053 case TRACEPOINT: 2054 { 2055 printf("TRACEPOINT: RETURN_1 = %d\n", ahc_inb(ahc, RETURN_1)); 2056 printf("TRACEPOINT: RETURN_2 = %d\n", ahc_inb(ahc, RETURN_2)); 2057 printf("TRACEPOINT: ARG_1 = %d\n", ahc_inb(ahc, ARG_1)); 2058 printf("TRACEPOINT: ARG_2 = %d\n", ahc_inb(ahc, ARG_2)); 2059 printf("TRACEPOINT: CCHADDR = %x\n", 2060 ahc_inb(ahc, CCHADDR) | (ahc_inb(ahc, CCHADDR+1) << 8) 2061 | (ahc_inb(ahc, CCHADDR+2) << 16) 2062 | (ahc_inb(ahc, CCHADDR+3) << 24)); 2063 #if 0 2064 printf("SSTAT1 == 0x%x\n", ahc_inb(ahc, SSTAT1)); 2065 printf("SSTAT0 == 0x%x\n", ahc_inb(ahc, SSTAT0)); 2066 printf(", SCSISIGI == 0x%x\n", ahc_inb(ahc, SCSISIGI)); 2067 printf("TRACEPOINT: CCHCNT = %d, SG_COUNT = %d\n", 2068 ahc_inb(ahc, CCHCNT), ahc_inb(ahc, SG_COUNT)); 2069 printf("TRACEPOINT: SCB_TAG = %d\n", ahc_inb(ahc, SCB_TAG)); 2070 printf("TRACEPOINT1: CCHADDR = %d, CCHCNT = %d, SCBPTR = %d\n", 2071 ahc_inb(ahc, CCHADDR) 2072 | (ahc_inb(ahc, CCHADDR+1) << 8) 2073 | (ahc_inb(ahc, CCHADDR+2) << 16) 2074 | (ahc_inb(ahc, CCHADDR+3) << 24), 2075 ahc_inb(ahc, CCHCNT) 2076 | (ahc_inb(ahc, CCHCNT+1) << 8) 2077 | (ahc_inb(ahc, CCHCNT+2) << 16), 2078 ahc_inb(ahc, SCBPTR)); 2079 printf("TRACEPOINT: WAITING_SCBH = %d\n", ahc_inb(ahc, WAITING_SCBH)); 2080 printf("TRACEPOINT: SCB_TAG = %d\n", ahc_inb(ahc, SCB_TAG)); 2081 #ifdef DDB 2082 cpu_Debugger(); 2083 #endif 2084 #endif 2085 break; 2086 } 2087 #if NOT_YET 2088 /* XXX Fill these in later */ 2089 case MESG_BUFFER_BUSY: 2090 break; 2091 case MSGIN_PHASEMIS: 2092 break; 2093 #endif 2094 default: 2095 printf("ahc_intr: seqint, " 2096 "intstat == 0x%x, scsisigi = 0x%x\n", 2097 intstat, ahc_inb(ahc, SCSISIGI)); 2098 break; 2099 } 2100 2101 unpause: 2102 /* 2103 * The sequencer is paused immediately on 2104 * a SEQINT, so we should restart it when 2105 * we're done. 2106 */ 2107 unpause_sequencer(ahc); 2108 } 2109 2110 static void 2111 ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat) 2112 { 2113 u_int scb_index; 2114 u_int status; 2115 struct scb *scb; 2116 char cur_channel; 2117 char intr_channel; 2118 2119 if ((ahc->features & AHC_TWIN) != 0 2120 && ((ahc_inb(ahc, SBLKCTL) & SELBUSB) != 0)) 2121 cur_channel = 'B'; 2122 else 2123 cur_channel = 'A'; 2124 intr_channel = cur_channel; 2125 2126 status = ahc_inb(ahc, SSTAT1); 2127 if (status == 0) { 2128 if ((ahc->features & AHC_TWIN) != 0) { 2129 /* Try the other channel */ 2130 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB); 2131 status = ahc_inb(ahc, SSTAT1); 2132 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB); 2133 intr_channel = (cur_channel == 'A') ? 'B' : 'A'; 2134 } 2135 if (status == 0) { 2136 printf("%s: Spurious SCSI interrupt\n", ahc_name(ahc)); 2137 return; 2138 } 2139 } 2140 2141 scb_index = ahc_inb(ahc, SCB_TAG); 2142 if (scb_index < ahc->scb_data->numscbs) { 2143 scb = &ahc->scb_data->scbarray[scb_index]; 2144 if ((scb->flags & SCB_ACTIVE) == 0 2145 || (ahc_inb(ahc, SEQ_FLAGS) & IDENTIFY_SEEN) == 0) 2146 scb = NULL; 2147 } else 2148 scb = NULL; 2149 2150 if ((status & SCSIRSTI) != 0) { 2151 printf("%s: Someone reset channel %c\n", 2152 ahc_name(ahc), intr_channel); 2153 ahc_reset_channel(ahc, intr_channel, /* Initiate Reset */FALSE); 2154 } else if ((status & SCSIPERR) != 0) { 2155 /* 2156 * Determine the bus phase and queue an appropriate message. 2157 * SCSIPERR is latched true as soon as a parity error 2158 * occurs. If the sequencer acked the transfer that 2159 * caused the parity error and the currently presented 2160 * transfer on the bus has correct parity, SCSIPERR will 2161 * be cleared by CLRSCSIPERR. Use this to determine if 2162 * we should look at the last phase the sequencer recorded, 2163 * or the current phase presented on the bus. 2164 */ 2165 u_int mesg_out; 2166 u_int curphase; 2167 u_int errorphase; 2168 u_int lastphase; 2169 int i; 2170 2171 lastphase = ahc_inb(ahc, LASTPHASE); 2172 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 2173 ahc_outb(ahc, CLRSINT1, CLRSCSIPERR); 2174 /* 2175 * For all phases save DATA, the sequencer won't 2176 * automatically ack a byte that has a parity error 2177 * in it. So the only way that the current phase 2178 * could be 'data-in' is if the parity error is for 2179 * an already acked byte in the data phase. During 2180 * synchronous data-in transfers, we may actually 2181 * ack bytes before latching the current phase in 2182 * LASTPHASE, leading to the discrepancy between 2183 * curphase and lastphase. 2184 */ 2185 if ((ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0 2186 || curphase == P_DATAIN) 2187 errorphase = curphase; 2188 else 2189 errorphase = lastphase; 2190 2191 for (i = 0; i < num_phases; i++) { 2192 if (errorphase == phase_table[i].phase) 2193 break; 2194 } 2195 mesg_out = phase_table[i].mesg_out; 2196 if (scb != NULL) 2197 scsipi_printaddr(scb->xs->xs_periph); 2198 else 2199 printf("%s:%c:%d: ", ahc_name(ahc), 2200 intr_channel, 2201 TCL_TARGET(ahc_inb(ahc, SAVED_TCL))); 2202 2203 printf("parity error detected %s. " 2204 "SEQADDR(0x%x) SCSIRATE(0x%x)\n", 2205 phase_table[i].phasemsg, 2206 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8), 2207 ahc_inb(ahc, SCSIRATE)); 2208 2209 /* 2210 * We've set the hardware to assert ATN if we 2211 * get a parity error on "in" phases, so all we 2212 * need to do is stuff the message buffer with 2213 * the appropriate message. "In" phases have set 2214 * mesg_out to something other than MSG_NOP. 2215 */ 2216 if (mesg_out != MSG_NOOP) { 2217 if (ahc->msg_type != MSG_TYPE_NONE) 2218 ahc->send_msg_perror = TRUE; 2219 else 2220 ahc_outb(ahc, MSG_OUT, mesg_out); 2221 } 2222 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2223 unpause_sequencer(ahc); 2224 } else if ((status & BUSFREE) != 0 2225 && (ahc_inb(ahc, SIMODE1) & ENBUSFREE) != 0) { 2226 /* 2227 * First look at what phase we were last in. 2228 * If its message out, chances are pretty good 2229 * that the busfree was in response to one of 2230 * our abort requests. 2231 */ 2232 u_int lastphase = ahc_inb(ahc, LASTPHASE); 2233 u_int saved_tcl = ahc_inb(ahc, SAVED_TCL); 2234 u_int target = TCL_TARGET(saved_tcl); 2235 u_int initiator_role_id = TCL_SCSI_ID(ahc, saved_tcl); 2236 char channel = TCL_CHANNEL(ahc, saved_tcl); 2237 int printerror = 1; 2238 2239 ahc_outb(ahc, SCSISEQ, 2240 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 2241 if (lastphase == P_MESGOUT) { 2242 u_int message; 2243 u_int tag; 2244 2245 message = ahc->msgout_buf[ahc->msgout_index - 1]; 2246 tag = SCB_LIST_NULL; 2247 switch (message) { 2248 case MSG_ABORT_TAG: 2249 tag = scb->hscb->tag; 2250 /* FALLTRHOUGH */ 2251 case MSG_ABORT: 2252 scsipi_printaddr(scb->xs->xs_periph); 2253 printf("SCB %x - Abort %s Completed.\n", 2254 scb->hscb->tag, tag == SCB_LIST_NULL ? 2255 "" : "Tag"); 2256 ahc_abort_scbs(ahc, target, channel, 2257 TCL_LUN(saved_tcl), tag, 2258 ROLE_INITIATOR, 2259 XS_DRIVER_STUFFUP); 2260 printerror = 0; 2261 break; 2262 case MSG_BUS_DEV_RESET: 2263 { 2264 struct ahc_devinfo devinfo; 2265 2266 if (scb != NULL && 2267 (scb->xs->xs_control & XS_CTL_RESET) 2268 && ahc_match_scb(scb, target, channel, 2269 TCL_LUN(saved_tcl), 2270 SCB_LIST_NULL, 2271 ROLE_INITIATOR)) { 2272 ahcsetccbstatus(scb->xs, XS_NOERROR); 2273 } 2274 ahc_compile_devinfo(&devinfo, 2275 initiator_role_id, 2276 target, 2277 TCL_LUN(saved_tcl), 2278 channel, 2279 ROLE_INITIATOR); 2280 ahc_handle_devreset(ahc, &devinfo, 2281 XS_RESET, 2282 "Bus Device Reset", 2283 /*verbose_level*/0); 2284 printerror = 0; 2285 break; 2286 } 2287 default: 2288 break; 2289 } 2290 } 2291 if (printerror != 0) { 2292 int i; 2293 2294 if (scb != NULL) { 2295 u_int tag; 2296 2297 if ((scb->hscb->control & TAG_ENB) != 0) 2298 tag = scb->hscb->tag; 2299 else 2300 tag = SCB_LIST_NULL; 2301 ahc_abort_scbs(ahc, target, channel, 2302 SCB_LUN(scb), tag, 2303 ROLE_INITIATOR, 2304 XS_DRIVER_STUFFUP); 2305 scsipi_printaddr(scb->xs->xs_periph); 2306 } else { 2307 /* 2308 * We had not fully identified this connection, 2309 * so we cannot abort anything. 2310 */ 2311 printf("%s: ", ahc_name(ahc)); 2312 } 2313 for (i = 0; i < num_phases; i++) { 2314 if (lastphase == phase_table[i].phase) 2315 break; 2316 } 2317 printf("Unexpected busfree %s\n" 2318 "SEQADDR == 0x%x\n", 2319 phase_table[i].phasemsg, ahc_inb(ahc, SEQADDR0) 2320 | (ahc_inb(ahc, SEQADDR1) << 8)); 2321 } 2322 ahc_clear_msg_state(ahc); 2323 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 2324 ahc_outb(ahc, CLRSINT1, CLRBUSFREE|CLRSCSIPERR); 2325 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2326 restart_sequencer(ahc); 2327 } else if ((status & SELTO) != 0) { 2328 u_int scbptr; 2329 2330 scbptr = ahc_inb(ahc, WAITING_SCBH); 2331 ahc_outb(ahc, SCBPTR, scbptr); 2332 scb_index = ahc_inb(ahc, SCB_TAG); 2333 2334 if (scb_index < ahc->scb_data->numscbs) { 2335 scb = &ahc->scb_data->scbarray[scb_index]; 2336 if ((scb->flags & SCB_ACTIVE) == 0) 2337 scb = NULL; 2338 } else 2339 scb = NULL; 2340 2341 if (scb == NULL) { 2342 printf("%s: ahc_intr - referenced scb not " 2343 "valid during SELTO scb(%d, %d)\n", 2344 ahc_name(ahc), scbptr, scb_index); 2345 } else { 2346 u_int tag; 2347 2348 tag = SCB_LIST_NULL; 2349 if ((scb->hscb->control & TAG_ENB) != 0) 2350 tag = scb->hscb->tag; 2351 2352 ahc_abort_scbs(ahc, SCB_TARGET(scb), SCB_CHANNEL(scb), 2353 SCB_LUN(scb), tag, 2354 ROLE_INITIATOR, XS_SELTIMEOUT); 2355 } 2356 /* Stop the selection */ 2357 ahc_outb(ahc, SCSISEQ, 0); 2358 2359 /* No more pending messages */ 2360 ahc_clear_msg_state(ahc); 2361 2362 /* 2363 * Although the driver does not care about the 2364 * 'Selection in Progress' status bit, the busy 2365 * LED does. SELINGO is only cleared by a sucessful 2366 * selection, so we must manually clear it to ensure 2367 * the LED turns off just incase no future successful 2368 * selections occur (e.g. no devices on the bus). 2369 */ 2370 ahc_outb(ahc, CLRSINT0, CLRSELINGO); 2371 2372 /* Clear interrupt state */ 2373 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR); 2374 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2375 restart_sequencer(ahc); 2376 } else { 2377 scsipi_printaddr(scb->xs->xs_periph); 2378 printf("Unknown SCSIINT. Status = 0x%x\n", status); 2379 ahc_outb(ahc, CLRSINT1, status); 2380 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2381 unpause_sequencer(ahc); 2382 } 2383 } 2384 2385 static void 2386 ahc_build_transfer_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2387 { 2388 /* 2389 * We need to initiate transfer negotiations. 2390 * If our current and goal settings are identical, 2391 * we want to renegotiate due to a check condition. 2392 */ 2393 struct ahc_initiator_tinfo *tinfo; 2394 struct tmode_tstate *tstate; 2395 int dowide; 2396 int dosync; 2397 2398 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 2399 devinfo->target, &tstate); 2400 dowide = tinfo->current.width != tinfo->goal.width; 2401 dosync = tinfo->current.period != tinfo->goal.period; 2402 2403 if (!dowide && !dosync) { 2404 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT; 2405 dosync = tinfo->goal.period != 0; 2406 } 2407 2408 if (dowide) { 2409 ahc_construct_wdtr(ahc, tinfo->goal.width); 2410 } else if (dosync) { 2411 const struct ahc_syncrate *rate; 2412 u_int period; 2413 u_int offset; 2414 2415 period = tinfo->goal.period; 2416 rate = ahc_devlimited_syncrate(ahc, &period); 2417 offset = tinfo->goal.offset; 2418 ahc_validate_offset(ahc, rate, &offset, 2419 tinfo->current.width); 2420 ahc_construct_sdtr(ahc, period, offset); 2421 } else { 2422 panic("ahc_intr: AWAITING_MSG for negotiation, " 2423 "but no negotiation needed"); 2424 } 2425 } 2426 2427 static void 2428 ahc_setup_initiator_msgout(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2429 struct scb *scb) 2430 { 2431 /* 2432 * To facilitate adding multiple messages together, 2433 * each routine should increment the index and len 2434 * variables instead of setting them explicitly. 2435 */ 2436 ahc->msgout_index = 0; 2437 ahc->msgout_len = 0; 2438 2439 if ((scb->flags & SCB_DEVICE_RESET) == 0 2440 && ahc_inb(ahc, MSG_OUT) == MSG_IDENTIFYFLAG) { 2441 u_int identify_msg; 2442 2443 identify_msg = MSG_IDENTIFYFLAG | SCB_LUN(scb); 2444 if ((scb->hscb->control & DISCENB) != 0) 2445 identify_msg |= MSG_IDENTIFY_DISCFLAG; 2446 ahc->msgout_buf[ahc->msgout_index++] = identify_msg; 2447 ahc->msgout_len++; 2448 2449 if ((scb->hscb->control & TAG_ENB) != 0) { 2450 ahc->msgout_buf[ahc->msgout_index++] = 2451 scb->xs->xs_tag_type; 2452 ahc->msgout_buf[ahc->msgout_index++] = scb->hscb->tag; 2453 ahc->msgout_len += 2; 2454 } 2455 } 2456 2457 if (scb->flags & SCB_DEVICE_RESET) { 2458 ahc->msgout_buf[ahc->msgout_index++] = MSG_BUS_DEV_RESET; 2459 ahc->msgout_len++; 2460 scsipi_printaddr(scb->xs->xs_periph); 2461 printf("Bus Device Reset Message Sent\n"); 2462 } else if (scb->flags & SCB_ABORT) { 2463 if ((scb->hscb->control & TAG_ENB) != 0) 2464 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT_TAG; 2465 else 2466 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT; 2467 ahc->msgout_len++; 2468 scsipi_printaddr(scb->xs->xs_periph); 2469 printf("Abort Message Sent\n"); 2470 } else if ((ahc->targ_msg_req & devinfo->target_mask) != 0) { 2471 ahc_build_transfer_msg(ahc, devinfo); 2472 } else { 2473 printf("ahc_intr: AWAITING_MSG for an SCB that " 2474 "does not have a waiting message"); 2475 panic("SCB = %d, SCB Control = %x, MSG_OUT = %x " 2476 "SCB flags = %x", scb->hscb->tag, scb->hscb->control, 2477 ahc_inb(ahc, MSG_OUT), scb->flags); 2478 } 2479 2480 /* 2481 * Clear the MK_MESSAGE flag from the SCB so we aren't 2482 * asked to send this message again. 2483 */ 2484 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) & ~MK_MESSAGE); 2485 ahc->msgout_index = 0; 2486 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2487 } 2488 2489 static void 2490 ahc_setup_target_msgin(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2491 { 2492 /* 2493 * To facilitate adding multiple messages together, 2494 * each routine should increment the index and len 2495 * variables instead of setting them explicitly. 2496 */ 2497 ahc->msgout_index = 0; 2498 ahc->msgout_len = 0; 2499 2500 if ((ahc->targ_msg_req & devinfo->target_mask) != 0) 2501 ahc_build_transfer_msg(ahc, devinfo); 2502 else 2503 panic("ahc_intr: AWAITING target message with no message"); 2504 2505 ahc->msgout_index = 0; 2506 ahc->msg_type = MSG_TYPE_TARGET_MSGIN; 2507 } 2508 2509 static int 2510 ahc_handle_msg_reject(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2511 { 2512 /* 2513 * What we care about here is if we had an 2514 * outstanding SDTR or WDTR message for this 2515 * target. If we did, this is a signal that 2516 * the target is refusing negotiation. 2517 */ 2518 struct scb *scb; 2519 u_int scb_index; 2520 u_int last_msg; 2521 int response = 0; 2522 2523 scb_index = ahc_inb(ahc, SCB_TAG); 2524 scb = &ahc->scb_data->scbarray[scb_index]; 2525 2526 /* Might be necessary */ 2527 last_msg = ahc_inb(ahc, LAST_MSG); 2528 2529 if (ahc_sent_msg(ahc, MSG_EXT_WDTR, /*full*/FALSE)) { 2530 struct ahc_initiator_tinfo *tinfo; 2531 struct tmode_tstate *tstate; 2532 2533 #ifdef AHC_DEBUG_NEG 2534 /* note 8bit xfers */ 2535 printf("%s:%c:%d: refuses WIDE negotiation. Using " 2536 "8bit transfers\n", ahc_name(ahc), 2537 devinfo->channel, devinfo->target); 2538 #endif 2539 ahc_set_width(ahc, devinfo, 2540 MSG_EXT_WDTR_BUS_8_BIT, 2541 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 2542 /*paused*/TRUE, /*done*/TRUE); 2543 /* 2544 * No need to clear the sync rate. If the target 2545 * did not accept the command, our syncrate is 2546 * unaffected. If the target started the negotiation, 2547 * but rejected our response, we already cleared the 2548 * sync rate before sending our WDTR. 2549 */ 2550 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, 2551 devinfo->our_scsiid, 2552 devinfo->target, &tstate); 2553 if (tinfo->goal.period) { 2554 u_int period; 2555 2556 /* Start the sync negotiation */ 2557 period = tinfo->goal.period; 2558 ahc_devlimited_syncrate(ahc, &period); 2559 ahc->msgout_index = 0; 2560 ahc->msgout_len = 0; 2561 ahc_construct_sdtr(ahc, period, tinfo->goal.offset); 2562 ahc->msgout_index = 0; 2563 response = 1; 2564 } else 2565 ahc_update_xfer_mode(ahc, devinfo); 2566 } else if (ahc_sent_msg(ahc, MSG_EXT_SDTR, /*full*/FALSE)) { 2567 /* note asynch xfers and clear flag */ 2568 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, /*period*/0, 2569 /*offset*/0, AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 2570 /*paused*/TRUE, /*done*/TRUE); 2571 #ifdef AHC_DEBUG_NEG 2572 printf("%s:%c:%d: refuses synchronous negotiation. " 2573 "Using asynchronous transfers\n", 2574 ahc_name(ahc), 2575 devinfo->channel, devinfo->target); 2576 #endif 2577 ahc_update_xfer_mode(ahc, devinfo); 2578 } else if ((scb->hscb->control & TAG_ENB) != 0) { 2579 printf("%s:%c:%d: refuses tagged commands. Performing " 2580 "non-tagged I/O\n", ahc_name(ahc), 2581 devinfo->channel, devinfo->target); 2582 2583 ahc_set_tags(ahc, devinfo, FALSE); 2584 ahc_update_xfer_mode(ahc, devinfo); 2585 2586 /* 2587 * Resend the identify for this CCB as the target 2588 * may believe that the selection is invalid otherwise. 2589 */ 2590 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) 2591 & ~MSG_SIMPLE_Q_TAG); 2592 scb->hscb->control &= ~MSG_SIMPLE_Q_TAG; 2593 ahc_outb(ahc, MSG_OUT, MSG_IDENTIFYFLAG); 2594 ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, SCSISIGO) | ATNO); 2595 2596 /* 2597 * Requeue all tagged commands for this target 2598 * currently in our posession so they can be 2599 * converted to untagged commands. 2600 */ 2601 ahc_search_qinfifo(ahc, SCB_TARGET(scb), SCB_CHANNEL(scb), 2602 SCB_LUN(scb), /*tag*/SCB_LIST_NULL, 2603 ROLE_INITIATOR, SCB_REQUEUE, 2604 SEARCH_COMPLETE); 2605 } else { 2606 /* 2607 * Otherwise, we ignore it. 2608 */ 2609 printf("%s:%c:%d: Message reject for %x -- ignored\n", 2610 ahc_name(ahc), devinfo->channel, devinfo->target, 2611 last_msg); 2612 } 2613 return (response); 2614 } 2615 2616 static void 2617 ahc_clear_msg_state(struct ahc_softc *ahc) 2618 { 2619 ahc->msgout_len = 0; 2620 ahc->msgin_index = 0; 2621 ahc->msg_type = MSG_TYPE_NONE; 2622 ahc_outb(ahc, MSG_OUT, MSG_NOOP); 2623 } 2624 2625 static void 2626 ahc_handle_message_phase(struct ahc_softc *ahc, struct scsipi_periph *periph) 2627 { 2628 struct ahc_devinfo devinfo; 2629 u_int bus_phase; 2630 int end_session; 2631 2632 ahc_fetch_devinfo(ahc, &devinfo); 2633 end_session = FALSE; 2634 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 2635 2636 reswitch: 2637 switch (ahc->msg_type) { 2638 case MSG_TYPE_INITIATOR_MSGOUT: 2639 { 2640 int lastbyte; 2641 int phasemis; 2642 int msgdone; 2643 2644 if (ahc->msgout_len == 0) 2645 panic("REQINIT interrupt with no active message"); 2646 2647 phasemis = bus_phase != P_MESGOUT; 2648 if (phasemis) { 2649 if (bus_phase == P_MESGIN) { 2650 /* 2651 * Change gears and see if 2652 * this messages is of interest to 2653 * us or should be passed back to 2654 * the sequencer. 2655 */ 2656 ahc_outb(ahc, CLRSINT1, CLRATNO); 2657 ahc->send_msg_perror = FALSE; 2658 ahc->msg_type = MSG_TYPE_INITIATOR_MSGIN; 2659 ahc->msgin_index = 0; 2660 goto reswitch; 2661 } 2662 end_session = TRUE; 2663 break; 2664 } 2665 2666 if (ahc->send_msg_perror) { 2667 ahc_outb(ahc, CLRSINT1, CLRATNO); 2668 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2669 ahc_outb(ahc, SCSIDATL, MSG_PARITY_ERROR); 2670 break; 2671 } 2672 2673 msgdone = ahc->msgout_index == ahc->msgout_len; 2674 if (msgdone) { 2675 /* 2676 * The target has requested a retry. 2677 * Re-assert ATN, reset our message index to 2678 * 0, and try again. 2679 */ 2680 ahc->msgout_index = 0; 2681 ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, SCSISIGO) | ATNO); 2682 } 2683 2684 lastbyte = ahc->msgout_index == (ahc->msgout_len - 1); 2685 if (lastbyte) { 2686 /* Last byte is signified by dropping ATN */ 2687 ahc_outb(ahc, CLRSINT1, CLRATNO); 2688 } 2689 2690 /* 2691 * Clear our interrupt status and present 2692 * the next byte on the bus. 2693 */ 2694 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2695 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]); 2696 break; 2697 } 2698 case MSG_TYPE_INITIATOR_MSGIN: 2699 { 2700 int phasemis; 2701 int message_done; 2702 2703 phasemis = bus_phase != P_MESGIN; 2704 2705 if (phasemis) { 2706 ahc->msgin_index = 0; 2707 if (bus_phase == P_MESGOUT 2708 && (ahc->send_msg_perror == TRUE 2709 || (ahc->msgout_len != 0 2710 && ahc->msgout_index == 0))) { 2711 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2712 goto reswitch; 2713 } 2714 end_session = TRUE; 2715 break; 2716 } 2717 2718 /* Pull the byte in without acking it */ 2719 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIBUSL); 2720 2721 message_done = ahc_parse_msg(ahc, periph, &devinfo); 2722 2723 if (message_done) { 2724 /* 2725 * Clear our incoming message buffer in case there 2726 * is another message following this one. 2727 */ 2728 ahc->msgin_index = 0; 2729 2730 /* 2731 * If this message illicited a response, 2732 * assert ATN so the target takes us to the 2733 * message out phase. 2734 */ 2735 if (ahc->msgout_len != 0) 2736 ahc_outb(ahc, SCSISIGO, 2737 ahc_inb(ahc, SCSISIGO) | ATNO); 2738 } else 2739 ahc->msgin_index++; 2740 2741 /* Ack the byte */ 2742 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2743 ahc_inb(ahc, SCSIDATL); 2744 break; 2745 } 2746 case MSG_TYPE_TARGET_MSGIN: 2747 { 2748 int msgdone; 2749 int msgout_request; 2750 2751 if (ahc->msgout_len == 0) 2752 panic("Target MSGIN with no active message"); 2753 2754 /* 2755 * If we interrupted a mesgout session, the initiator 2756 * will not know this until our first REQ. So, we 2757 * only honor mesgout requests after we've sent our 2758 * first byte. 2759 */ 2760 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0 2761 && ahc->msgout_index > 0) 2762 msgout_request = TRUE; 2763 else 2764 msgout_request = FALSE; 2765 2766 if (msgout_request) { 2767 2768 /* 2769 * Change gears and see if 2770 * this messages is of interest to 2771 * us or should be passed back to 2772 * the sequencer. 2773 */ 2774 ahc->msg_type = MSG_TYPE_TARGET_MSGOUT; 2775 ahc_outb(ahc, SCSISIGO, P_MESGOUT | BSYO); 2776 ahc->msgin_index = 0; 2777 /* Dummy read to REQ for first byte */ 2778 ahc_inb(ahc, SCSIDATL); 2779 ahc_outb(ahc, SXFRCTL0, 2780 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2781 break; 2782 } 2783 2784 msgdone = ahc->msgout_index == ahc->msgout_len; 2785 if (msgdone) { 2786 ahc_outb(ahc, SXFRCTL0, 2787 ahc_inb(ahc, SXFRCTL0) & ~SPIOEN); 2788 end_session = TRUE; 2789 break; 2790 } 2791 2792 /* 2793 * Present the next byte on the bus. 2794 */ 2795 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2796 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]); 2797 break; 2798 } 2799 case MSG_TYPE_TARGET_MSGOUT: 2800 { 2801 int lastbyte; 2802 int msgdone; 2803 2804 /* 2805 * The initiator signals that this is 2806 * the last byte by dropping ATN. 2807 */ 2808 lastbyte = (ahc_inb(ahc, SCSISIGI) & ATNI) == 0; 2809 2810 /* 2811 * Read the latched byte, but turn off SPIOEN first 2812 * so that we don't inadvertantly cause a REQ for the 2813 * next byte. 2814 */ 2815 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) & ~SPIOEN); 2816 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIDATL); 2817 msgdone = ahc_parse_msg(ahc, periph, &devinfo); 2818 if (msgdone == MSGLOOP_TERMINATED) { 2819 /* 2820 * The message is *really* done in that it caused 2821 * us to go to bus free. The sequencer has already 2822 * been reset at this point, so pull the ejection 2823 * handle. 2824 */ 2825 return; 2826 } 2827 2828 ahc->msgin_index++; 2829 2830 /* 2831 * XXX Read spec about initiator dropping ATN too soon 2832 * and use msgdone to detect it. 2833 */ 2834 if (msgdone == MSGLOOP_MSGCOMPLETE) { 2835 ahc->msgin_index = 0; 2836 2837 /* 2838 * If this message illicited a response, transition 2839 * to the Message in phase and send it. 2840 */ 2841 if (ahc->msgout_len != 0) { 2842 ahc_outb(ahc, SCSISIGO, P_MESGIN | BSYO); 2843 ahc_outb(ahc, SXFRCTL0, 2844 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2845 ahc->msg_type = MSG_TYPE_TARGET_MSGIN; 2846 ahc->msgin_index = 0; 2847 break; 2848 } 2849 } 2850 2851 if (lastbyte) 2852 end_session = TRUE; 2853 else { 2854 /* Ask for the next byte. */ 2855 ahc_outb(ahc, SXFRCTL0, 2856 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2857 } 2858 2859 break; 2860 } 2861 default: 2862 panic("Unknown REQINIT message type"); 2863 } 2864 2865 if (end_session) { 2866 ahc_clear_msg_state(ahc); 2867 ahc_outb(ahc, RETURN_1, EXIT_MSG_LOOP); 2868 } else 2869 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP); 2870 } 2871 2872 /* 2873 * See if we sent a particular extended message to the target. 2874 * If "full" is true, the target saw the full message. 2875 * If "full" is false, the target saw at least the first 2876 * byte of the message. 2877 */ 2878 static int 2879 ahc_sent_msg(struct ahc_softc *ahc, u_int msgtype, int full) 2880 { 2881 int found; 2882 int index; 2883 2884 found = FALSE; 2885 index = 0; 2886 2887 while (index < ahc->msgout_len) { 2888 if (ahc->msgout_buf[index] == MSG_EXTENDED) { 2889 2890 /* Found a candidate */ 2891 if (ahc->msgout_buf[index+2] == msgtype) { 2892 u_int end_index; 2893 2894 end_index = index + 1 2895 + ahc->msgout_buf[index + 1]; 2896 if (full) { 2897 if (ahc->msgout_index > end_index) 2898 found = TRUE; 2899 } else if (ahc->msgout_index > index) 2900 found = TRUE; 2901 } 2902 break; 2903 } else if (ahc->msgout_buf[index] >= MSG_SIMPLE_Q_TAG 2904 && ahc->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) { 2905 2906 /* Skip tag type and tag id or residue param*/ 2907 index += 2; 2908 } else { 2909 /* Single byte message */ 2910 index++; 2911 } 2912 } 2913 return (found); 2914 } 2915 2916 static int 2917 ahc_parse_msg(struct ahc_softc *ahc, struct scsipi_periph *periph, 2918 struct ahc_devinfo *devinfo) 2919 { 2920 struct ahc_initiator_tinfo *tinfo; 2921 struct tmode_tstate *tstate; 2922 int reject; 2923 int done; 2924 int response; 2925 u_int targ_scsirate; 2926 2927 done = MSGLOOP_IN_PROG; 2928 response = FALSE; 2929 reject = FALSE; 2930 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 2931 devinfo->target, &tstate); 2932 targ_scsirate = tinfo->scsirate; 2933 2934 /* 2935 * Parse as much of the message as is available, 2936 * rejecting it if we don't support it. When 2937 * the entire message is available and has been 2938 * handled, return MSGLOOP_MSGCOMPLETE, indicating 2939 * that we have parsed an entire message. 2940 * 2941 * In the case of extended messages, we accept the length 2942 * byte outright and perform more checking once we know the 2943 * extended message type. 2944 */ 2945 switch (ahc->msgin_buf[0]) { 2946 case MSG_MESSAGE_REJECT: 2947 response = ahc_handle_msg_reject(ahc, devinfo); 2948 /* FALLTHROUGH */ 2949 case MSG_NOOP: 2950 done = MSGLOOP_MSGCOMPLETE; 2951 break; 2952 case MSG_IGN_WIDE_RESIDUE: 2953 { 2954 /* Wait for the whole message */ 2955 if (ahc->msgin_index >= 1) { 2956 if (ahc->msgin_buf[1] != 1 2957 || tinfo->current.width == MSG_EXT_WDTR_BUS_8_BIT) { 2958 reject = TRUE; 2959 done = MSGLOOP_MSGCOMPLETE; 2960 } else 2961 ahc_handle_ign_wide_residue(ahc, devinfo); 2962 } 2963 break; 2964 } 2965 case MSG_EXTENDED: 2966 { 2967 /* Wait for enough of the message to begin validation */ 2968 if (ahc->msgin_index < 2) 2969 break; 2970 switch (ahc->msgin_buf[2]) { 2971 case MSG_EXT_SDTR: 2972 { 2973 const struct ahc_syncrate *syncrate; 2974 u_int period; 2975 u_int offset; 2976 u_int saved_offset; 2977 2978 if (ahc->msgin_buf[1] != MSG_EXT_SDTR_LEN) { 2979 reject = TRUE; 2980 break; 2981 } 2982 2983 /* 2984 * Wait until we have both args before validating 2985 * and acting on this message. 2986 * 2987 * Add one to MSG_EXT_SDTR_LEN to account for 2988 * the extended message preamble. 2989 */ 2990 if (ahc->msgin_index < (MSG_EXT_SDTR_LEN + 1)) 2991 break; 2992 2993 period = ahc->msgin_buf[3]; 2994 saved_offset = offset = ahc->msgin_buf[4]; 2995 syncrate = ahc_devlimited_syncrate(ahc, &period); 2996 ahc_validate_offset(ahc, syncrate, &offset, 2997 targ_scsirate & WIDEXFER); 2998 ahc_set_syncrate(ahc, devinfo, 2999 syncrate, period, offset, 3000 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3001 /*paused*/TRUE, /*done*/TRUE); 3002 ahc_update_xfer_mode(ahc, devinfo); 3003 3004 /* 3005 * See if we initiated Sync Negotiation 3006 * and didn't have to fall down to async 3007 * transfers. 3008 */ 3009 if (ahc_sent_msg(ahc, MSG_EXT_SDTR, /*full*/TRUE)) { 3010 /* We started it */ 3011 if (saved_offset != offset) { 3012 /* Went too low - force async */ 3013 reject = TRUE; 3014 } 3015 } else { 3016 /* 3017 * Send our own SDTR in reply 3018 */ 3019 ahc->msgout_index = 0; 3020 ahc->msgout_len = 0; 3021 ahc_construct_sdtr(ahc, period, offset); 3022 ahc->msgout_index = 0; 3023 response = TRUE; 3024 } 3025 done = MSGLOOP_MSGCOMPLETE; 3026 break; 3027 } 3028 case MSG_EXT_WDTR: 3029 { 3030 u_int bus_width; 3031 u_int sending_reply; 3032 3033 sending_reply = FALSE; 3034 if (ahc->msgin_buf[1] != MSG_EXT_WDTR_LEN) { 3035 reject = TRUE; 3036 break; 3037 } 3038 3039 /* 3040 * Wait until we have our arg before validating 3041 * and acting on this message. 3042 * 3043 * Add one to MSG_EXT_WDTR_LEN to account for 3044 * the extended message preamble. 3045 */ 3046 if (ahc->msgin_index < (MSG_EXT_WDTR_LEN + 1)) 3047 break; 3048 3049 bus_width = ahc->msgin_buf[3]; 3050 if (ahc_sent_msg(ahc, MSG_EXT_WDTR, /*full*/TRUE)) { 3051 /* 3052 * Don't send a WDTR back to the 3053 * target, since we asked first. 3054 */ 3055 switch (bus_width){ 3056 default: 3057 /* 3058 * How can we do anything greater 3059 * than 16bit transfers on a 16bit 3060 * bus? 3061 */ 3062 reject = TRUE; 3063 printf("%s: target %d requested %dBit " 3064 "transfers. Rejecting...\n", 3065 ahc_name(ahc), devinfo->target, 3066 8 * (0x01 << bus_width)); 3067 /* FALLTHROUGH */ 3068 case MSG_EXT_WDTR_BUS_8_BIT: 3069 bus_width = MSG_EXT_WDTR_BUS_8_BIT; 3070 break; 3071 case MSG_EXT_WDTR_BUS_16_BIT: 3072 break; 3073 } 3074 } else { 3075 /* 3076 * Send our own WDTR in reply 3077 */ 3078 switch (bus_width) { 3079 default: 3080 if (ahc->features & AHC_WIDE) { 3081 /* Respond Wide */ 3082 bus_width = 3083 MSG_EXT_WDTR_BUS_16_BIT; 3084 break; 3085 } 3086 /* FALLTHROUGH */ 3087 case MSG_EXT_WDTR_BUS_8_BIT: 3088 bus_width = MSG_EXT_WDTR_BUS_8_BIT; 3089 break; 3090 } 3091 ahc->msgout_index = 0; 3092 ahc->msgout_len = 0; 3093 ahc_construct_wdtr(ahc, bus_width); 3094 ahc->msgout_index = 0; 3095 response = TRUE; 3096 sending_reply = TRUE; 3097 } 3098 ahc_set_width(ahc, devinfo, bus_width, 3099 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3100 /*paused*/TRUE, /*done*/TRUE); 3101 3102 /* After a wide message, we are async */ 3103 ahc_set_syncrate(ahc, devinfo, 3104 /*syncrate*/NULL, /*period*/0, 3105 /*offset*/0, AHC_TRANS_ACTIVE, 3106 /*paused*/TRUE, /*done*/FALSE); 3107 if (sending_reply == FALSE && reject == FALSE) { 3108 3109 if (tinfo->goal.period) { 3110 const struct ahc_syncrate *rate; 3111 u_int period; 3112 u_int offset; 3113 3114 /* Start the sync negotiation */ 3115 period = tinfo->goal.period; 3116 rate = ahc_devlimited_syncrate(ahc, 3117 &period); 3118 offset = tinfo->goal.offset; 3119 ahc_validate_offset(ahc, rate, &offset, 3120 tinfo->current.width); 3121 ahc->msgout_index = 0; 3122 ahc->msgout_len = 0; 3123 ahc_construct_sdtr(ahc, period, offset); 3124 ahc->msgout_index = 0; 3125 response = TRUE; 3126 } else 3127 ahc_update_xfer_mode(ahc, devinfo); 3128 } 3129 done = MSGLOOP_MSGCOMPLETE; 3130 break; 3131 } 3132 default: 3133 /* Unknown extended message. Reject it. */ 3134 reject = TRUE; 3135 break; 3136 } 3137 break; 3138 } 3139 case MSG_BUS_DEV_RESET: 3140 ahc_handle_devreset(ahc, devinfo, 3141 XS_RESET, "Bus Device Reset Received", 3142 /*verbose_level*/0); 3143 restart_sequencer(ahc); 3144 done = MSGLOOP_TERMINATED; 3145 break; 3146 case MSG_ABORT_TAG: 3147 case MSG_ABORT: 3148 case MSG_CLEAR_QUEUE: 3149 /* Target mode messages */ 3150 if (devinfo->role != ROLE_TARGET) { 3151 reject = TRUE; 3152 break; 3153 } 3154 #if AHC_TARGET_MODE 3155 ahc_abort_scbs(ahc, devinfo->target, devinfo->channel, 3156 devinfo->lun, 3157 ahc->msgin_buf[0] == MSG_ABORT_TAG 3158 ? SCB_LIST_NULL 3159 : ahc_inb(ahc, INITIATOR_TAG), 3160 ROLE_TARGET, XS_DRIVER_STUFFUP); 3161 3162 tstate = ahc->enabled_targets[devinfo->our_scsiid]; 3163 if (tstate != NULL) { 3164 struct tmode_lstate* lstate; 3165 3166 lstate = tstate->enabled_luns[devinfo->lun]; 3167 if (lstate != NULL) { 3168 ahc_queue_lstate_event(ahc, lstate, 3169 devinfo->our_scsiid, 3170 ahc->msgin_buf[0], 3171 /*arg*/0); 3172 ahc_send_lstate_events(ahc, lstate); 3173 } 3174 } 3175 done = MSGLOOP_MSGCOMPLETE; 3176 #else 3177 panic("ahc: got target mode message"); 3178 #endif 3179 break; 3180 case MSG_TERM_IO_PROC: 3181 default: 3182 reject = TRUE; 3183 break; 3184 } 3185 3186 if (reject) { 3187 /* 3188 * Setup to reject the message. 3189 */ 3190 ahc->msgout_index = 0; 3191 ahc->msgout_len = 1; 3192 ahc->msgout_buf[0] = MSG_MESSAGE_REJECT; 3193 done = MSGLOOP_MSGCOMPLETE; 3194 response = TRUE; 3195 } 3196 3197 if (done != MSGLOOP_IN_PROG && !response) 3198 /* Clear the outgoing message buffer */ 3199 ahc->msgout_len = 0; 3200 3201 return (done); 3202 } 3203 3204 static void 3205 ahc_handle_ign_wide_residue(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 3206 { 3207 u_int scb_index; 3208 struct scb *scb; 3209 3210 scb_index = ahc_inb(ahc, SCB_TAG); 3211 scb = &ahc->scb_data->scbarray[scb_index]; 3212 if ((ahc_inb(ahc, SEQ_FLAGS) & DPHASE) == 0 3213 || !(scb->xs->xs_control & XS_CTL_DATA_IN)) { 3214 /* 3215 * Ignore the message if we haven't 3216 * seen an appropriate data phase yet. 3217 */ 3218 } else { 3219 /* 3220 * If the residual occurred on the last 3221 * transfer and the transfer request was 3222 * expected to end on an odd count, do 3223 * nothing. Otherwise, subtract a byte 3224 * and update the residual count accordingly. 3225 */ 3226 u_int resid_sgcnt; 3227 3228 resid_sgcnt = ahc_inb(ahc, SCB_RESID_SGCNT); 3229 if (resid_sgcnt == 0 3230 && ahc_inb(ahc, DATA_COUNT_ODD) == 1) { 3231 /* 3232 * If the residual occurred on the last 3233 * transfer and the transfer request was 3234 * expected to end on an odd count, do 3235 * nothing. 3236 */ 3237 } else { 3238 u_int data_cnt; 3239 u_int32_t data_addr; 3240 u_int sg_index; 3241 3242 data_cnt = (ahc_inb(ahc, SCB_RESID_DCNT + 2) << 16) 3243 | (ahc_inb(ahc, SCB_RESID_DCNT + 1) << 8) 3244 | (ahc_inb(ahc, SCB_RESID_DCNT)); 3245 3246 data_addr = (ahc_inb(ahc, SHADDR + 3) << 24) 3247 | (ahc_inb(ahc, SHADDR + 2) << 16) 3248 | (ahc_inb(ahc, SHADDR + 1) << 8) 3249 | (ahc_inb(ahc, SHADDR)); 3250 3251 data_cnt += 1; 3252 data_addr -= 1; 3253 3254 sg_index = scb->sg_count - resid_sgcnt; 3255 3256 if (sg_index != 0 3257 && (le32toh(scb->sg_list[sg_index].len) < data_cnt)) { 3258 u_int32_t sg_addr; 3259 3260 sg_index--; 3261 data_cnt = 1; 3262 data_addr = le32toh(scb->sg_list[sg_index].addr) 3263 + le32toh(scb->sg_list[sg_index].len) 3264 - 1; 3265 3266 /* 3267 * The physical address base points to the 3268 * second entry as it is always used for 3269 * calculating the "next S/G pointer". 3270 */ 3271 sg_addr = scb->sg_list_phys 3272 + (sg_index* sizeof(*scb->sg_list)); 3273 ahc_outb(ahc, SG_NEXT + 3, sg_addr >> 24); 3274 ahc_outb(ahc, SG_NEXT + 2, sg_addr >> 16); 3275 ahc_outb(ahc, SG_NEXT + 1, sg_addr >> 8); 3276 ahc_outb(ahc, SG_NEXT, sg_addr); 3277 } 3278 3279 ahc_outb(ahc, SCB_RESID_DCNT + 2, data_cnt >> 16); 3280 ahc_outb(ahc, SCB_RESID_DCNT + 1, data_cnt >> 8); 3281 ahc_outb(ahc, SCB_RESID_DCNT, data_cnt); 3282 3283 ahc_outb(ahc, SHADDR + 3, data_addr >> 24); 3284 ahc_outb(ahc, SHADDR + 2, data_addr >> 16); 3285 ahc_outb(ahc, SHADDR + 1, data_addr >> 8); 3286 ahc_outb(ahc, SHADDR, data_addr); 3287 } 3288 } 3289 } 3290 3291 static void 3292 ahc_handle_devreset(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 3293 int status, char *message, 3294 int verbose_level) 3295 { 3296 int found; 3297 3298 found = ahc_abort_scbs(ahc, devinfo->target, devinfo->channel, 3299 AHC_LUN_WILDCARD, SCB_LIST_NULL, devinfo->role, 3300 status); 3301 3302 /* 3303 * Go back to async/narrow transfers and renegotiate. 3304 * ahc_set_width and ahc_set_syncrate can cope with NULL 3305 * paths. 3306 */ 3307 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT, 3308 AHC_TRANS_CUR, /*paused*/TRUE, /*done*/FALSE); 3309 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, 3310 /*period*/0, /*offset*/0, AHC_TRANS_CUR, 3311 /*paused*/TRUE, /*done*/FALSE); 3312 ahc_update_xfer_mode(ahc, devinfo); 3313 3314 if (message != NULL && (verbose_level <= 0)) 3315 printf("%s: %s on %c:%d. %d SCBs aborted\n", ahc_name(ahc), 3316 message, devinfo->channel, devinfo->target, found); 3317 } 3318 3319 /* 3320 * We have an scb which has been processed by the 3321 * adaptor, now we look to see how the operation 3322 * went. 3323 */ 3324 static void 3325 ahc_done(struct ahc_softc *ahc, struct scb *scb) 3326 { 3327 struct scsipi_xfer *xs; 3328 struct scsipi_periph *periph; 3329 int requeue = 0; 3330 int target; 3331 3332 3333 xs = scb->xs; 3334 periph = xs->xs_periph; 3335 LIST_REMOVE(scb, plinks); 3336 3337 callout_stop(&scb->xs->xs_callout); 3338 3339 #ifdef AHC_DEBUG 3340 if (ahc_debug & AHC_SHOWCMDS) { 3341 scsipi_printaddr(periph); 3342 printf("ahc_done opcode %d tag %x\n", xs->cmdstore.opcode, 3343 scb->hscb->tag); 3344 } 3345 #endif 3346 3347 target = periph->periph_target; 3348 3349 if (xs->datalen) { 3350 int op; 3351 3352 if (xs->xs_control & XS_CTL_DATA_IN) 3353 op = BUS_DMASYNC_POSTREAD; 3354 else 3355 op = BUS_DMASYNC_POSTWRITE; 3356 bus_dmamap_sync(ahc->parent_dmat, scb->dmamap, 0, 3357 scb->dmamap->dm_mapsize, op); 3358 bus_dmamap_unload(ahc->parent_dmat, scb->dmamap); 3359 } 3360 3361 /* 3362 * Unbusy this target/channel/lun. 3363 * XXX if we are holding two commands per lun, 3364 * send the next command. 3365 */ 3366 if (!(scb->hscb->control & TAG_ENB)) 3367 ahc_index_busy_tcl(ahc, scb->hscb->tcl, /*unbusy*/TRUE); 3368 3369 /* 3370 * If the recovery SCB completes, we have to be 3371 * out of our timeout. 3372 */ 3373 if ((scb->flags & SCB_RECOVERY_SCB) != 0) { 3374 3375 struct scb *scbp; 3376 3377 /* 3378 * We were able to complete the command successfully, 3379 * so reinstate the timeouts for all other pending 3380 * commands. 3381 */ 3382 scbp = ahc->pending_ccbs.lh_first; 3383 while (scbp != NULL) { 3384 struct scsipi_xfer *txs = scbp->xs; 3385 3386 if (!(txs->xs_control & XS_CTL_POLL)) { 3387 callout_reset(&scbp->xs->xs_callout, 3388 mstohz(scbp->xs->timeout), 3389 ahc_timeout, scbp); 3390 } 3391 scbp = LIST_NEXT(scbp, plinks); 3392 } 3393 3394 /* 3395 * Ensure that we didn't put a second instance of this 3396 * SCB into the QINFIFO. 3397 */ 3398 ahc_search_qinfifo(ahc, SCB_TARGET(scb), SCB_CHANNEL(scb), 3399 SCB_LUN(scb), scb->hscb->tag, 3400 ROLE_INITIATOR, /*status*/0, 3401 SEARCH_REMOVE); 3402 if (xs->error != XS_NOERROR) 3403 ahcsetccbstatus(xs, XS_TIMEOUT); 3404 scsipi_printaddr(xs->xs_periph); 3405 printf("no longer in timeout, status = %x\n", xs->status); 3406 } 3407 3408 if (xs->error != XS_NOERROR) { 3409 /* Don't clobber any existing error state */ 3410 } else if ((scb->flags & SCB_SENSE) != 0) { 3411 /* 3412 * We performed autosense retrieval. 3413 * 3414 * zero the sense data before having 3415 * the drive fill it. The SCSI spec mandates 3416 * that any untransferred data should be 3417 * assumed to be zero. Complete the 'bounce' 3418 * of sense information through buffers accessible 3419 * via bus-space by copying it into the clients 3420 * csio. 3421 */ 3422 memset(&xs->sense.scsi_sense, 0, sizeof(xs->sense.scsi_sense)); 3423 memcpy(&xs->sense.scsi_sense, 3424 &ahc->scb_data->sense[scb->hscb->tag], 3425 le32toh(scb->sg_list->len)); 3426 xs->error = XS_SENSE; 3427 } 3428 if (scb->flags & SCB_FREEZE_QUEUE) { 3429 scsipi_periph_thaw(periph, 1); 3430 scb->flags &= ~SCB_FREEZE_QUEUE; 3431 } 3432 3433 requeue = scb->flags & SCB_REQUEUE; 3434 ahcfreescb(ahc, scb); 3435 3436 if (requeue) { 3437 xs->error = XS_REQUEUE; 3438 } 3439 scsipi_done(xs); 3440 } 3441 3442 /* 3443 * Determine the number of SCBs available on the controller 3444 */ 3445 int 3446 ahc_probe_scbs(struct ahc_softc *ahc) { 3447 int i; 3448 3449 for (i = 0; i < AHC_SCB_MAX; i++) { 3450 ahc_outb(ahc, SCBPTR, i); 3451 ahc_outb(ahc, SCB_CONTROL, i); 3452 if (ahc_inb(ahc, SCB_CONTROL) != i) 3453 break; 3454 ahc_outb(ahc, SCBPTR, 0); 3455 if (ahc_inb(ahc, SCB_CONTROL) != 0) 3456 break; 3457 } 3458 return (i); 3459 } 3460 3461 /* 3462 * Start the board, ready for normal operation 3463 */ 3464 int 3465 ahc_init(struct ahc_softc *ahc) 3466 { 3467 int max_targ = 15; 3468 int i; 3469 int term; 3470 u_int scsi_conf; 3471 u_int scsiseq_template; 3472 u_int ultraenb; 3473 u_int discenable; 3474 u_int tagenable; 3475 size_t driver_data_size; 3476 u_int32_t physaddr; 3477 3478 #ifdef AHC_PRINT_SRAM 3479 printf("Scratch Ram:"); 3480 for (i = 0x20; i < 0x5f; i++) { 3481 if (((i % 8) == 0) && (i != 0)) { 3482 printf ("\n "); 3483 } 3484 printf (" 0x%x", ahc_inb(ahc, i)); 3485 } 3486 if ((ahc->features & AHC_MORE_SRAM) != 0) { 3487 for (i = 0x70; i < 0x7f; i++) { 3488 if (((i % 8) == 0) && (i != 0)) { 3489 printf ("\n "); 3490 } 3491 printf (" 0x%x", ahc_inb(ahc, i)); 3492 } 3493 } 3494 printf ("\n"); 3495 #endif 3496 3497 /* 3498 * Assume we have a board at this stage and it has been reset. 3499 */ 3500 if ((ahc->flags & AHC_USEDEFAULTS) != 0) 3501 ahc->our_id = ahc->our_id_b = 7; 3502 3503 /* 3504 * Default to allowing initiator operations. 3505 */ 3506 ahc->flags |= AHC_INITIATORMODE; 3507 3508 /* 3509 * DMA tag for our command fifos and other data in system memory 3510 * the card's sequencer must be able to access. For initiator 3511 * roles, we need to allocate space for the qinfifo, qoutfifo, 3512 * and untagged_scb arrays each of which are composed of 256 3513 * 1 byte elements. When providing for the target mode role, 3514 * we additionally must provide space for the incoming target 3515 * command fifo. 3516 */ 3517 driver_data_size = 3 * 256 * sizeof(u_int8_t); 3518 3519 if (ahc_createdmamem(ahc->parent_dmat, driver_data_size, 3520 ahc->sc_dmaflags, 3521 &ahc->shared_data_dmamap, (caddr_t *)&ahc->qoutfifo, 3522 &ahc->shared_data_busaddr, &ahc->shared_data_seg, 3523 &ahc->shared_data_nseg, ahc_name(ahc), "shared data") < 0) 3524 return (ENOMEM); 3525 3526 ahc->init_level++; 3527 3528 /* Allocate SCB data now that parent_dmat is initialized */ 3529 if (ahc->scb_data->maxhscbs == 0) 3530 if (ahcinitscbdata(ahc) != 0) 3531 return (ENOMEM); 3532 3533 ahc->qinfifo = &ahc->qoutfifo[256]; 3534 ahc->untagged_scbs = &ahc->qinfifo[256]; 3535 /* There are no untagged SCBs active yet. */ 3536 for (i = 0; i < 256; i++) 3537 ahc->untagged_scbs[i] = SCB_LIST_NULL; 3538 3539 /* All of our queues are empty */ 3540 for (i = 0; i < 256; i++) 3541 ahc->qoutfifo[i] = SCB_LIST_NULL; 3542 3543 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 0, 3544 driver_data_size, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3545 3546 /* 3547 * Allocate a tstate to house information for our 3548 * initiator presence on the bus as well as the user 3549 * data for any target mode initiator. 3550 */ 3551 if (ahc_alloc_tstate(ahc, ahc->our_id, 'A') == NULL) { 3552 printf("%s: unable to allocate tmode_tstate. " 3553 "Failing attach\n", ahc_name(ahc)); 3554 return (-1); 3555 } 3556 3557 if ((ahc->features & AHC_TWIN) != 0) { 3558 if (ahc_alloc_tstate(ahc, ahc->our_id_b, 'B') == NULL) { 3559 printf("%s: unable to allocate tmode_tstate. " 3560 "Failing attach\n", ahc_name(ahc)); 3561 return (-1); 3562 } 3563 printf("Twin Channel, A SCSI Id=%d, B SCSI Id=%d, primary %c, ", 3564 ahc->our_id, ahc->our_id_b, 3565 ahc->flags & AHC_CHANNEL_B_PRIMARY? 'B': 'A'); 3566 } else { 3567 if ((ahc->features & AHC_WIDE) != 0) { 3568 printf("Wide "); 3569 } else { 3570 printf("Single "); 3571 } 3572 printf("Channel %c, SCSI Id=%d, ", ahc->channel, ahc->our_id); 3573 } 3574 3575 ahc_outb(ahc, SEQ_FLAGS, 0); 3576 3577 if (ahc->scb_data->maxhscbs < AHC_SCB_MAX) { 3578 ahc->flags |= AHC_PAGESCBS; 3579 printf("%d/%d SCBs\n", ahc->scb_data->maxhscbs, AHC_SCB_MAX); 3580 } else { 3581 ahc->flags &= ~AHC_PAGESCBS; 3582 printf("%d SCBs\n", ahc->scb_data->maxhscbs); 3583 } 3584 3585 #ifdef AHC_DEBUG 3586 if (ahc_debug & AHC_SHOWMISC) { 3587 printf("%s: hardware scb %lu bytes; kernel scb %lu bytes; " 3588 "ahc_dma %lu bytes\n", 3589 ahc_name(ahc), 3590 (unsigned long) sizeof(struct hardware_scb), 3591 (unsigned long) sizeof(struct scb), 3592 (unsigned long) sizeof(struct ahc_dma_seg)); 3593 } 3594 #endif /* AHC_DEBUG */ 3595 3596 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1, for both channels*/ 3597 if (ahc->features & AHC_TWIN) { 3598 3599 /* 3600 * The device is gated to channel B after a chip reset, 3601 * so set those values first 3602 */ 3603 term = (ahc->flags & AHC_TERM_ENB_B) != 0 ? STPWEN : 0; 3604 if ((ahc->features & AHC_ULTRA2) != 0) 3605 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id_b); 3606 else 3607 ahc_outb(ahc, SCSIID, ahc->our_id_b); 3608 scsi_conf = ahc_inb(ahc, SCSICONF + 1); 3609 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL)) 3610 |term|ENSTIMER|ACTNEGEN); 3611 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 3612 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN); 3613 3614 if ((scsi_conf & RESET_SCSI) != 0 3615 && (ahc->flags & AHC_INITIATORMODE) != 0) 3616 ahc->flags |= AHC_RESET_BUS_B; 3617 3618 /* Select Channel A */ 3619 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB); 3620 } 3621 term = (ahc->flags & AHC_TERM_ENB_A) != 0 ? STPWEN : 0; 3622 if ((ahc->features & AHC_ULTRA2) != 0) 3623 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id); 3624 else 3625 ahc_outb(ahc, SCSIID, ahc->our_id); 3626 scsi_conf = ahc_inb(ahc, SCSICONF); 3627 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL)) 3628 |term 3629 |ENSTIMER|ACTNEGEN); 3630 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 3631 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN); 3632 3633 if ((scsi_conf & RESET_SCSI) != 0 3634 && (ahc->flags & AHC_INITIATORMODE) != 0) 3635 ahc->flags |= AHC_RESET_BUS_A; 3636 3637 /* 3638 * Look at the information that board initialization or 3639 * the board bios has left us. 3640 */ 3641 ultraenb = 0; 3642 tagenable = ALL_TARGETS_MASK; 3643 3644 /* Grab the disconnection disable table and invert it for our needs */ 3645 if (ahc->flags & AHC_USEDEFAULTS) { 3646 printf("%s: Host Adapter Bios disabled. Using default SCSI " 3647 "device parameters\n", ahc_name(ahc)); 3648 ahc->flags |= AHC_EXTENDED_TRANS_A|AHC_EXTENDED_TRANS_B| 3649 AHC_TERM_ENB_A|AHC_TERM_ENB_B; 3650 discenable = ALL_TARGETS_MASK; 3651 if ((ahc->features & AHC_ULTRA) != 0) 3652 ultraenb = ALL_TARGETS_MASK; 3653 } else { 3654 discenable = ~((ahc_inb(ahc, DISC_DSB + 1) << 8) 3655 | ahc_inb(ahc, DISC_DSB)); 3656 if ((ahc->features & (AHC_ULTRA|AHC_ULTRA2)) != 0) 3657 ultraenb = (ahc_inb(ahc, ULTRA_ENB + 1) << 8) 3658 | ahc_inb(ahc, ULTRA_ENB); 3659 } 3660 3661 if ((ahc->features & (AHC_WIDE|AHC_TWIN)) == 0) 3662 max_targ = 7; 3663 3664 for (i = 0; i <= max_targ; i++) { 3665 struct ahc_initiator_tinfo *tinfo; 3666 struct tmode_tstate *tstate; 3667 u_int our_id; 3668 u_int target_id; 3669 char channel; 3670 3671 channel = 'A'; 3672 our_id = ahc->our_id; 3673 target_id = i; 3674 if (i > 7 && (ahc->features & AHC_TWIN) != 0) { 3675 channel = 'B'; 3676 our_id = ahc->our_id_b; 3677 target_id = i % 8; 3678 } 3679 tinfo = ahc_fetch_transinfo(ahc, channel, our_id, 3680 target_id, &tstate); 3681 /* Default to async narrow across the board */ 3682 memset(tinfo, 0, sizeof(*tinfo)); 3683 if (ahc->flags & AHC_USEDEFAULTS) { 3684 if ((ahc->features & AHC_WIDE) != 0) 3685 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 3686 3687 /* 3688 * These will be truncated when we determine the 3689 * connection type we have with the target. 3690 */ 3691 tinfo->user.period = ahc_syncrates->period; 3692 tinfo->user.offset = ~0; 3693 } else { 3694 u_int scsirate; 3695 u_int16_t mask; 3696 3697 /* Take the settings leftover in scratch RAM. */ 3698 scsirate = ahc_inb(ahc, TARG_SCSIRATE + i); 3699 mask = (0x01 << i); 3700 if ((ahc->features & AHC_ULTRA2) != 0) { 3701 u_int offset; 3702 u_int maxsync; 3703 3704 if ((scsirate & SOFS) == 0x0F) { 3705 /* 3706 * Haven't negotiated yet, 3707 * so the format is different. 3708 */ 3709 scsirate = (scsirate & SXFR) >> 4 3710 | (ultraenb & mask) 3711 ? 0x08 : 0x0 3712 | (scsirate & WIDEXFER); 3713 offset = MAX_OFFSET_ULTRA2; 3714 } else 3715 offset = ahc_inb(ahc, TARG_OFFSET + i); 3716 maxsync = AHC_SYNCRATE_ULTRA2; 3717 if ((ahc->features & AHC_DT) != 0) 3718 maxsync = AHC_SYNCRATE_DT; 3719 tinfo->user.period = 3720 ahc_find_period(ahc, scsirate, maxsync); 3721 if (offset == 0) 3722 tinfo->user.period = 0; 3723 else 3724 tinfo->user.offset = ~0; 3725 } else if ((scsirate & SOFS) != 0) { 3726 tinfo->user.period = 3727 ahc_find_period(ahc, scsirate, 3728 (ultraenb & mask) 3729 ? AHC_SYNCRATE_ULTRA 3730 : AHC_SYNCRATE_FAST); 3731 if (tinfo->user.period != 0) 3732 tinfo->user.offset = ~0; 3733 } 3734 if ((scsirate & WIDEXFER) != 0 3735 && (ahc->features & AHC_WIDE) != 0) 3736 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 3737 } 3738 tinfo->goal = tinfo->user; /* force negotiation */ 3739 tstate->ultraenb = ultraenb; 3740 tstate->discenable = discenable; 3741 tstate->tagenable = 0; /* Wait until the XPT says its okay */ 3742 tstate->tagdisable = 0; 3743 } 3744 ahc->user_discenable = discenable; 3745 ahc->user_tagenable = tagenable; 3746 3747 /* 3748 * Tell the sequencer where it can find our arrays in memory. 3749 */ 3750 physaddr = ahc->scb_data->hscb_busaddr; 3751 ahc_outb(ahc, HSCB_ADDR, physaddr & 0xFF); 3752 ahc_outb(ahc, HSCB_ADDR + 1, (physaddr >> 8) & 0xFF); 3753 ahc_outb(ahc, HSCB_ADDR + 2, (physaddr >> 16) & 0xFF); 3754 ahc_outb(ahc, HSCB_ADDR + 3, (physaddr >> 24) & 0xFF); 3755 3756 physaddr = ahc->shared_data_busaddr; 3757 ahc_outb(ahc, SCBID_ADDR, physaddr & 0xFF); 3758 ahc_outb(ahc, SCBID_ADDR + 1, (physaddr >> 8) & 0xFF); 3759 ahc_outb(ahc, SCBID_ADDR + 2, (physaddr >> 16) & 0xFF); 3760 ahc_outb(ahc, SCBID_ADDR + 3, (physaddr >> 24) & 0xFF); 3761 3762 /* Target mode incomding command fifo */ 3763 physaddr += 3 * 256 * sizeof(u_int8_t); 3764 ahc_outb(ahc, TMODE_CMDADDR, physaddr & 0xFF); 3765 ahc_outb(ahc, TMODE_CMDADDR + 1, (physaddr >> 8) & 0xFF); 3766 ahc_outb(ahc, TMODE_CMDADDR + 2, (physaddr >> 16) & 0xFF); 3767 ahc_outb(ahc, TMODE_CMDADDR + 3, (physaddr >> 24) & 0xFF); 3768 3769 /* 3770 * Initialize the group code to command length table. 3771 * This overrides the values in TARG_SCSIRATE, so only 3772 * setup the table after we have processed that information. 3773 */ 3774 ahc_outb(ahc, CMDSIZE_TABLE, 5); 3775 ahc_outb(ahc, CMDSIZE_TABLE + 1, 9); 3776 ahc_outb(ahc, CMDSIZE_TABLE + 2, 9); 3777 ahc_outb(ahc, CMDSIZE_TABLE + 3, 0); 3778 ahc_outb(ahc, CMDSIZE_TABLE + 4, 15); 3779 ahc_outb(ahc, CMDSIZE_TABLE + 5, 11); 3780 ahc_outb(ahc, CMDSIZE_TABLE + 6, 0); 3781 ahc_outb(ahc, CMDSIZE_TABLE + 7, 0); 3782 3783 /* Tell the sequencer of our initial queue positions */ 3784 ahc_outb(ahc, KERNEL_QINPOS, 0); 3785 ahc_outb(ahc, QINPOS, 0); 3786 ahc_outb(ahc, QOUTPOS, 0); 3787 3788 #ifdef AHC_DEBUG 3789 if (ahc_debug & AHC_SHOWMISC) 3790 printf("DISCENABLE == 0x%x\nULTRAENB == 0x%x\n", 3791 discenable, ultraenb); 3792 #endif 3793 3794 /* Don't have any special messages to send to targets */ 3795 ahc_outb(ahc, TARGET_MSG_REQUEST, 0); 3796 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 0); 3797 3798 /* 3799 * Use the built in queue management registers 3800 * if they are available. 3801 */ 3802 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 3803 ahc_outb(ahc, QOFF_CTLSTA, SCB_QSIZE_256); 3804 ahc_outb(ahc, SDSCB_QOFF, 0); 3805 ahc_outb(ahc, SNSCB_QOFF, 0); 3806 ahc_outb(ahc, HNSCB_QOFF, 0); 3807 } 3808 3809 3810 /* We don't have any waiting selections */ 3811 ahc_outb(ahc, WAITING_SCBH, SCB_LIST_NULL); 3812 3813 /* Our disconnection list is empty too */ 3814 ahc_outb(ahc, DISCONNECTED_SCBH, SCB_LIST_NULL); 3815 3816 /* Message out buffer starts empty */ 3817 ahc_outb(ahc, MSG_OUT, MSG_NOOP); 3818 3819 /* 3820 * Setup the allowed SCSI Sequences based on operational mode. 3821 * If we are a target, we'll enable select in operations once 3822 * we've had a lun enabled. 3823 */ 3824 scsiseq_template = ENSELO|ENAUTOATNO|ENAUTOATNP; 3825 if ((ahc->flags & AHC_INITIATORMODE) != 0) 3826 scsiseq_template |= ENRSELI; 3827 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq_template); 3828 3829 /* 3830 * Load the Sequencer program and Enable the adapter 3831 * in "fast" mode. 3832 */ 3833 #ifdef AHC_DEBUG 3834 printf("%s: Downloading Sequencer Program...", 3835 ahc_name(ahc)); 3836 #endif 3837 3838 ahc_loadseq(ahc); 3839 3840 /* We have to wait until after any system dumps... */ 3841 shutdownhook_establish(ahc_shutdown, ahc); 3842 3843 return (0); 3844 } 3845 3846 static int 3847 ahc_ioctl(struct scsipi_channel *channel, u_long cmd, caddr_t addr, int flag, 3848 struct proc *p) 3849 { 3850 struct ahc_softc *ahc = (void *)channel->chan_adapter->adapt_dev; 3851 int s, ret = ENOTTY; 3852 3853 switch (cmd) { 3854 case SCBUSIORESET: 3855 s = splbio(); 3856 ahc_reset_channel(ahc, channel->chan_channel == 1 ? 'B' : 'A', 3857 TRUE); 3858 splx(s); 3859 ret = 0; 3860 break; 3861 default: 3862 break; 3863 } 3864 3865 return ret; 3866 } 3867 3868 3869 /* 3870 * XXX fvdl the busy_tcl checks and settings should only be done 3871 * for the non-tagged queueing case, but we don't do tagged queueing 3872 * yet, so.. 3873 */ 3874 static void 3875 ahc_action(struct scsipi_channel *chan, scsipi_adapter_req_t req, void *arg) 3876 { 3877 struct scsipi_xfer *xs; 3878 struct scsipi_periph *periph; 3879 struct ahc_softc *ahc = (void *)chan->chan_adapter->adapt_dev; 3880 struct scb *scb; 3881 struct hardware_scb *hscb; 3882 struct ahc_initiator_tinfo *tinfo; 3883 struct tmode_tstate *tstate; 3884 u_int target_id; 3885 u_int our_id; 3886 int s, tcl; 3887 u_int16_t mask; 3888 char channel; 3889 3890 switch (req) { 3891 case ADAPTER_REQ_RUN_XFER: 3892 xs = arg; 3893 periph = xs->xs_periph; 3894 3895 SC_DEBUG(xs->xs_periph, SCSIPI_DB3, ("ahc_action\n")); 3896 3897 /* must protect the queue */ 3898 s = splbio(); 3899 3900 tcl = XS_TCL(ahc, xs); 3901 3902 if (!ahc_istagged_device(ahc, xs, 0) && 3903 ahc_index_busy_tcl(ahc, tcl, FALSE) != SCB_LIST_NULL) { 3904 panic("ahc_action: not tagged and device busy"); 3905 } 3906 3907 3908 target_id = periph->periph_target; 3909 our_id = SIM_SCSI_ID(ahc, periph); 3910 3911 /* 3912 * get an scb to use. 3913 */ 3914 if ((scb = ahcgetscb(ahc)) == NULL) { 3915 xs->error = XS_RESOURCE_SHORTAGE; 3916 scsipi_done(xs); 3917 splx(s); 3918 return; 3919 } 3920 3921 tcl = XS_TCL(ahc, xs); 3922 3923 #ifdef DIAGNOSTIC 3924 if (!ahc_istagged_device(ahc, xs, 0) && 3925 ahc_index_busy_tcl(ahc, tcl, FALSE) != SCB_LIST_NULL) 3926 panic("ahc: queuing for busy target"); 3927 #endif 3928 3929 scb->xs = xs; 3930 hscb = scb->hscb; 3931 hscb->tcl = tcl; 3932 3933 if (xs->xs_tag_type) { 3934 #ifdef DIAGNOSTIC 3935 if (ahc_istagged_device(ahc, xs, 0) == 0) 3936 panic("ahc_action: taggged command for untagged device"); 3937 #endif 3938 scb->hscb->control |= TAG_ENB; 3939 } else 3940 ahc_busy_tcl(ahc, scb); 3941 3942 splx(s); 3943 3944 channel = SIM_CHANNEL(ahc, periph); 3945 if (ahc->inited_channels[channel - 'A'] == 0) { 3946 if ((channel == 'A' && 3947 (ahc->flags & AHC_RESET_BUS_A)) || 3948 (channel == 'B' && 3949 (ahc->flags & AHC_RESET_BUS_B))) { 3950 s = splbio(); 3951 ahc_reset_channel(ahc, channel, TRUE); 3952 splx(s); 3953 } 3954 ahc->inited_channels[channel - 'A'] = 1; 3955 } 3956 3957 /* 3958 * Put all the arguments for the xfer in the scb 3959 */ 3960 3961 mask = SCB_TARGET_MASK(scb); 3962 tinfo = ahc_fetch_transinfo(ahc, 3963 SIM_CHANNEL(ahc, periph), 3964 our_id, target_id, &tstate); 3965 if (ahc->inited_targets[target_id] == 0) { 3966 struct ahc_devinfo devinfo; 3967 s = splbio(); 3968 ahc_compile_devinfo(&devinfo, our_id, target_id, 3969 periph->periph_lun, 3970 SIM_CHANNEL(ahc, periph), 3971 ROLE_INITIATOR); 3972 ahc_update_target_msg_request(ahc, &devinfo, tinfo, 3973 TRUE, FALSE); 3974 ahc->inited_targets[target_id] = 1; 3975 splx(s); 3976 } 3977 hscb->scsirate = tinfo->scsirate; 3978 hscb->scsioffset = tinfo->current.offset; 3979 if ((tstate->ultraenb & mask) != 0) 3980 hscb->control |= ULTRAENB; 3981 3982 if ((tstate->discenable & mask) != 0) 3983 hscb->control |= DISCENB; 3984 3985 if (xs->xs_control & XS_CTL_RESET) { 3986 hscb->cmdpointer = 0; 3987 scb->flags |= SCB_DEVICE_RESET; 3988 hscb->control |= MK_MESSAGE; 3989 ahc_execute_scb(scb, NULL, 0); 3990 } 3991 3992 ahc_setup_data(ahc, xs, scb); 3993 return; 3994 case ADAPTER_REQ_GROW_RESOURCES: 3995 /* XXX not supported */ 3996 return; 3997 case ADAPTER_REQ_SET_XFER_MODE: 3998 { 3999 struct scsipi_xfer_mode *xm = arg; 4000 struct ahc_devinfo devinfo; 4001 int target_id, our_id; 4002 char channel; 4003 4004 target_id = xm->xm_target; 4005 our_id = chan->chan_id; 4006 channel = (chan->chan_channel == 1) ? 'B' : 'A'; 4007 s = splbio(); 4008 tinfo = ahc_fetch_transinfo(ahc, channel, our_id, target_id, 4009 &tstate); 4010 ahc_compile_devinfo(&devinfo, our_id, target_id, 4011 0, channel, ROLE_INITIATOR); 4012 ahc->inited_targets[target_id] = 2; 4013 if (xm->xm_mode & PERIPH_CAP_TQING && 4014 (tstate->tagdisable & devinfo.target_mask) == 0) { 4015 ahc_set_tags(ahc, &devinfo, TRUE); 4016 } 4017 splx(s); 4018 ahc_update_xfer_mode(ahc, &devinfo); 4019 } 4020 } 4021 } 4022 4023 static void 4024 ahc_execute_scb(void *arg, bus_dma_segment_t *dm_segs, int nsegments) 4025 { 4026 struct scb *scb; 4027 struct scsipi_xfer *xs; 4028 struct ahc_softc *ahc; 4029 int s; 4030 4031 scb = (struct scb *)arg; 4032 xs = scb->xs; 4033 ahc = (void *)xs->xs_periph->periph_channel->chan_adapter->adapt_dev; 4034 4035 4036 if (nsegments != 0) { 4037 struct ahc_dma_seg *sg; 4038 bus_dma_segment_t *end_seg; 4039 int op; 4040 4041 end_seg = dm_segs + nsegments; 4042 4043 /* Copy the first SG into the data pointer area */ 4044 scb->hscb->data = dm_segs->ds_addr; 4045 scb->hscb->datalen = dm_segs->ds_len; 4046 4047 /* Copy the segments into our SG list */ 4048 sg = scb->sg_list; 4049 while (dm_segs < end_seg) { 4050 sg->addr = dm_segs->ds_addr; 4051 sg->len = dm_segs->ds_len; 4052 ahc_swap_sg(sg); 4053 sg++; 4054 dm_segs++; 4055 } 4056 4057 /* Note where to find the SG entries in bus space */ 4058 scb->hscb->SG_pointer = scb->sg_list_phys; 4059 4060 if (xs->xs_control & XS_CTL_DATA_IN) 4061 op = BUS_DMASYNC_PREREAD; 4062 else 4063 op = BUS_DMASYNC_PREWRITE; 4064 4065 bus_dmamap_sync(ahc->parent_dmat, scb->dmamap, 0, 4066 scb->dmamap->dm_mapsize, op); 4067 4068 } else { 4069 scb->hscb->SG_pointer = 0; 4070 scb->hscb->data = 0; 4071 scb->hscb->datalen = 0; 4072 } 4073 4074 scb->sg_count = scb->hscb->SG_count = nsegments; 4075 4076 s = splbio(); 4077 4078 /* 4079 * Last time we need to check if this SCB needs to 4080 * be aborted. 4081 */ 4082 if (xs->xs_status & XS_STS_DONE) { 4083 if (!ahc_istagged_device(ahc, xs, 0)) 4084 ahc_index_busy_tcl(ahc, scb->hscb->tcl, TRUE); 4085 if (nsegments != 0) 4086 bus_dmamap_unload(ahc->parent_dmat, scb->dmamap); 4087 ahcfreescb(ahc, scb); 4088 splx(s); 4089 return; 4090 } 4091 4092 #ifdef DIAGNOSTIC 4093 if (scb->sg_count > 255) 4094 panic("ahc bad sg_count"); 4095 #endif 4096 4097 ahc_swap_hscb(scb->hscb); 4098 4099 LIST_INSERT_HEAD(&ahc->pending_ccbs, scb, plinks); 4100 4101 scb->flags |= SCB_ACTIVE; 4102 4103 if (!(xs->xs_control & XS_CTL_POLL)) 4104 callout_reset(&scb->xs->xs_callout, mstohz(xs->timeout), 4105 ahc_timeout, scb); 4106 4107 if ((scb->flags & SCB_TARGET_IMMEDIATE) != 0) { 4108 #if 0 4109 printf("Continueing Immediate Command %d:%d\n", 4110 xs->xs_periph->periph_target, 4111 xs->xs_periph->periph_lun); 4112 #endif 4113 pause_sequencer(ahc); 4114 if ((ahc->flags & AHC_PAGESCBS) == 0) 4115 ahc_outb(ahc, SCBPTR, scb->hscb->tag); 4116 ahc_outb(ahc, SCB_TAG, scb->hscb->tag); 4117 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP); 4118 unpause_sequencer(ahc); 4119 } else { 4120 4121 #if 0 4122 printf("tag %x at qpos %u vaddr %p paddr 0x%lx\n", 4123 scb->hscb->tag, ahc->qinfifonext, 4124 &ahc->qinfifo[ahc->qinfifonext], 4125 ahc->shared_data_busaddr + 1024 + ahc->qinfifonext); 4126 #endif 4127 4128 ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag; 4129 4130 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 4131 QINFIFO_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); 4132 4133 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4134 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 4135 } else { 4136 pause_sequencer(ahc); 4137 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 4138 unpause_sequencer(ahc); 4139 } 4140 } 4141 4142 #ifdef AHC_DEBUG 4143 if (ahc_debug & AHC_SHOWCMDS) { 4144 scsi_print_addr(xs->xs_periph); 4145 printf("opcode %d tag %x len %d flags %x control %x fpos %u" 4146 " rate %x\n", 4147 xs->cmdstore.opcode, scb->hscb->tag, scb->hscb->datalen, 4148 scb->flags, scb->hscb->control, ahc->qinfifonext, 4149 scb->hscb->scsirate); 4150 } 4151 #endif 4152 4153 if (!(xs->xs_control & XS_CTL_POLL)) { 4154 splx(s); 4155 return; 4156 } 4157 /* 4158 * If we can't use interrupts, poll for completion 4159 */ 4160 SC_DEBUG(xs->xs_periph, SCSIPI_DB3, ("cmd_poll\n")); 4161 do { 4162 if (ahc_poll(ahc, xs->timeout)) { 4163 if (!(xs->xs_control & XS_CTL_SILENT)) 4164 printf("cmd fail\n"); 4165 ahc_timeout(scb); 4166 break; 4167 } 4168 } while (!(xs->xs_status & XS_STS_DONE)); 4169 splx(s); 4170 return; 4171 } 4172 4173 static int 4174 ahc_poll(struct ahc_softc *ahc, int wait) 4175 { 4176 while (--wait) { 4177 DELAY(1000); 4178 if (ahc_inb(ahc, INTSTAT) & INT_PEND) 4179 break; 4180 } 4181 4182 if (wait == 0) { 4183 printf("%s: board is not responding\n", ahc_name(ahc)); 4184 return (EIO); 4185 } 4186 4187 ahc_intr((void *)ahc); 4188 return (0); 4189 } 4190 4191 static void 4192 ahc_setup_data(struct ahc_softc *ahc, struct scsipi_xfer *xs, 4193 struct scb *scb) 4194 { 4195 struct hardware_scb *hscb; 4196 4197 hscb = scb->hscb; 4198 xs->resid = xs->status = 0; 4199 4200 hscb->cmdlen = xs->cmdlen; 4201 memcpy(hscb->cmdstore, xs->cmd, xs->cmdlen); 4202 hscb->cmdpointer = hscb->cmdstore_busaddr; 4203 4204 /* Only use S/G if there is a transfer */ 4205 if (xs->datalen) { 4206 int error; 4207 4208 error = bus_dmamap_load(ahc->parent_dmat, 4209 scb->dmamap, xs->data, 4210 xs->datalen, NULL, 4211 ((xs->xs_control & XS_CTL_NOSLEEP) ? 4212 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | 4213 BUS_DMA_STREAMING | 4214 ((xs->xs_control & XS_CTL_DATA_IN) ? 4215 BUS_DMA_READ : BUS_DMA_WRITE)); 4216 if (error) { 4217 #ifdef AHC_DEBUG 4218 printf("%s: in ahc_setup_data(): bus_dmamap_load() " 4219 "= %d\n", 4220 ahc_name(ahc), 4221 error); 4222 #endif 4223 if (!ahc_istagged_device(ahc, xs, 0)) 4224 ahc_index_busy_tcl(ahc, hscb->tcl, TRUE); 4225 xs->error = XS_RESOURCE_SHORTAGE; /* XXX fvdl */ 4226 scsipi_done(xs); 4227 return; 4228 } 4229 ahc_execute_scb(scb, 4230 scb->dmamap->dm_segs, 4231 scb->dmamap->dm_nsegs); 4232 } else { 4233 ahc_execute_scb(scb, NULL, 0); 4234 } 4235 } 4236 4237 static void 4238 ahc_freeze_devq(struct ahc_softc *ahc, struct scsipi_periph *periph) 4239 { 4240 int target; 4241 char channel; 4242 int lun; 4243 4244 target = periph->periph_target; 4245 lun = periph->periph_lun; 4246 channel = periph->periph_channel->chan_channel; 4247 4248 ahc_search_qinfifo(ahc, target, channel, lun, 4249 /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN, 4250 SCB_REQUEUE, SEARCH_COMPLETE); 4251 } 4252 4253 static void 4254 ahcallocscbs(struct ahc_softc *ahc) 4255 { 4256 struct scb_data *scb_data; 4257 struct scb *next_scb; 4258 struct sg_map_node *sg_map; 4259 bus_addr_t physaddr; 4260 struct ahc_dma_seg *segs; 4261 int newcount; 4262 int i; 4263 4264 scb_data = ahc->scb_data; 4265 if (scb_data->numscbs >= AHC_SCB_MAX) 4266 /* Can't allocate any more */ 4267 return; 4268 4269 next_scb = &scb_data->scbarray[scb_data->numscbs]; 4270 4271 sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT); 4272 4273 if (sg_map == NULL) 4274 return; 4275 4276 if (ahc_createdmamem(ahc->parent_dmat, PAGE_SIZE, ahc->sc_dmaflags, 4277 &sg_map->sg_dmamap, 4278 (caddr_t *)&sg_map->sg_vaddr, &sg_map->sg_physaddr, 4279 &sg_map->sg_dmasegs, &sg_map->sg_nseg, ahc_name(ahc), 4280 "SG space") < 0) { 4281 free(sg_map, M_DEVBUF); 4282 return; 4283 } 4284 4285 SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links); 4286 4287 segs = sg_map->sg_vaddr; 4288 physaddr = sg_map->sg_physaddr; 4289 4290 newcount = (PAGE_SIZE / (AHC_NSEG * sizeof(struct ahc_dma_seg))); 4291 for (i = 0; scb_data->numscbs < AHC_SCB_MAX && i < newcount; i++) { 4292 int error; 4293 4294 next_scb->sg_list = segs; 4295 /* 4296 * The sequencer always starts with the second entry. 4297 * The first entry is embedded in the scb. 4298 */ 4299 next_scb->sg_list_phys = physaddr + sizeof(struct ahc_dma_seg); 4300 next_scb->flags = SCB_FREE; 4301 error = bus_dmamap_create(ahc->parent_dmat, 4302 AHC_MAXTRANSFER_SIZE, AHC_NSEG, MAXBSIZE, 0, 4303 BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW|ahc->sc_dmaflags, 4304 &next_scb->dmamap); 4305 if (error != 0) 4306 break; 4307 next_scb->hscb = &scb_data->hscbs[scb_data->numscbs]; 4308 next_scb->hscb->tag = ahc->scb_data->numscbs; 4309 next_scb->hscb->cmdstore_busaddr = 4310 ahc_hscb_busaddr(ahc, next_scb->hscb->tag) 4311 + offsetof(struct hardware_scb, cmdstore); 4312 next_scb->hscb->cmdstore_busaddr = 4313 htole32(next_scb->hscb->cmdstore_busaddr); 4314 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, next_scb, links); 4315 segs += AHC_NSEG; 4316 physaddr += (AHC_NSEG * sizeof(struct ahc_dma_seg)); 4317 next_scb++; 4318 ahc->scb_data->numscbs++; 4319 } 4320 #ifdef AHC_DEBUG 4321 if (ahc_debug & AHC_SHOWSCBALLOC) 4322 printf("%s: allocated %d new SCBs count now %d\n", 4323 ahc_name(ahc), i - 1, ahc->scb_data->numscbs); 4324 #endif 4325 } 4326 4327 #ifdef AHC_DUMP_SEQ 4328 static void 4329 ahc_dumpseq(struct ahc_softc* ahc) 4330 { 4331 int i; 4332 int max_prog; 4333 4334 if ((ahc->chip & AHC_BUS_MASK) < AHC_PCI) 4335 max_prog = 448; 4336 else if ((ahc->features & AHC_ULTRA2) != 0) 4337 max_prog = 768; 4338 else 4339 max_prog = 512; 4340 4341 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 4342 ahc_outb(ahc, SEQADDR0, 0); 4343 ahc_outb(ahc, SEQADDR1, 0); 4344 for (i = 0; i < max_prog; i++) { 4345 u_int8_t ins_bytes[4]; 4346 4347 ahc_insb(ahc, SEQRAM, ins_bytes, 4); 4348 printf("0x%08x\n", ins_bytes[0] << 24 4349 | ins_bytes[1] << 16 4350 | ins_bytes[2] << 8 4351 | ins_bytes[3]); 4352 } 4353 } 4354 #endif 4355 4356 static void 4357 ahc_loadseq(struct ahc_softc *ahc) 4358 { 4359 const struct patch *cur_patch; 4360 int i; 4361 int downloaded; 4362 int skip_addr; 4363 u_int8_t download_consts[4]; 4364 4365 /* Setup downloadable constant table */ 4366 #if 0 4367 /* No downloaded constants are currently defined. */ 4368 download_consts[TMODE_NUMCMDS] = ahc->num_targetcmds; 4369 #endif 4370 4371 cur_patch = patches; 4372 downloaded = 0; 4373 skip_addr = 0; 4374 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 4375 ahc_outb(ahc, SEQADDR0, 0); 4376 ahc_outb(ahc, SEQADDR1, 0); 4377 4378 for (i = 0; i < sizeof(seqprog)/4; i++) { 4379 if (ahc_check_patch(ahc, &cur_patch, i, &skip_addr) == 0) { 4380 /* 4381 * Don't download this instruction as it 4382 * is in a patch that was removed. 4383 */ 4384 continue; 4385 } 4386 ahc_download_instr(ahc, i, download_consts); 4387 downloaded++; 4388 } 4389 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE); 4390 restart_sequencer(ahc); 4391 4392 #ifdef AHC_DEBUG 4393 printf(" %d instructions downloaded\n", downloaded); 4394 #endif 4395 } 4396 4397 static int 4398 ahc_check_patch(struct ahc_softc *ahc, const struct patch **start_patch, 4399 int start_instr, int *skip_addr) 4400 { 4401 const struct patch *cur_patch; 4402 const struct patch *last_patch; 4403 int num_patches; 4404 4405 num_patches = sizeof(patches)/sizeof(struct patch); 4406 last_patch = &patches[num_patches]; 4407 cur_patch = *start_patch; 4408 4409 while (cur_patch < last_patch && start_instr == cur_patch->begin) { 4410 4411 if (cur_patch->patch_func(ahc) == 0) { 4412 4413 /* Start rejecting code */ 4414 *skip_addr = start_instr + cur_patch->skip_instr; 4415 cur_patch += cur_patch->skip_patch; 4416 } else { 4417 /* Accepted this patch. Advance to the next 4418 * one and wait for our intruction pointer to 4419 * hit this point. 4420 */ 4421 cur_patch++; 4422 } 4423 } 4424 4425 *start_patch = cur_patch; 4426 if (start_instr < *skip_addr) 4427 /* Still skipping */ 4428 return (0); 4429 4430 return (1); 4431 } 4432 4433 static void 4434 ahc_download_instr(struct ahc_softc *ahc, int instrptr, u_int8_t *dconsts) 4435 { 4436 union ins_formats instr; 4437 struct ins_format1 *fmt1_ins; 4438 struct ins_format3 *fmt3_ins; 4439 u_int opcode; 4440 4441 /* Structure copy */ 4442 memcpy(&instr, &seqprog[instrptr * 4], sizeof instr); 4443 4444 instr.integer = le32toh(instr.integer); 4445 4446 fmt1_ins = &instr.format1; 4447 fmt3_ins = NULL; 4448 4449 /* Pull the opcode */ 4450 opcode = instr.format1.opcode; 4451 switch (opcode) { 4452 case AIC_OP_JMP: 4453 case AIC_OP_JC: 4454 case AIC_OP_JNC: 4455 case AIC_OP_CALL: 4456 case AIC_OP_JNE: 4457 case AIC_OP_JNZ: 4458 case AIC_OP_JE: 4459 case AIC_OP_JZ: 4460 { 4461 const struct patch *cur_patch; 4462 int address_offset; 4463 u_int address; 4464 int skip_addr; 4465 int i; 4466 4467 fmt3_ins = &instr.format3; 4468 address_offset = 0; 4469 address = fmt3_ins->address; 4470 cur_patch = patches; 4471 skip_addr = 0; 4472 4473 for (i = 0; i < address;) { 4474 4475 ahc_check_patch(ahc, &cur_patch, i, &skip_addr); 4476 4477 if (skip_addr > i) { 4478 int end_addr; 4479 4480 end_addr = MIN(address, skip_addr); 4481 address_offset += end_addr - i; 4482 i = skip_addr; 4483 } else { 4484 i++; 4485 } 4486 } 4487 address -= address_offset; 4488 fmt3_ins->address = address; 4489 /* FALLTHROUGH */ 4490 } 4491 case AIC_OP_OR: 4492 case AIC_OP_AND: 4493 case AIC_OP_XOR: 4494 case AIC_OP_ADD: 4495 case AIC_OP_ADC: 4496 case AIC_OP_BMOV: 4497 if (fmt1_ins->parity != 0) { 4498 fmt1_ins->immediate = dconsts[fmt1_ins->immediate]; 4499 } 4500 fmt1_ins->parity = 0; 4501 /* FALLTHROUGH */ 4502 case AIC_OP_ROL: 4503 if ((ahc->features & AHC_ULTRA2) != 0) { 4504 int i, count; 4505 4506 /* Calculate odd parity for the instruction */ 4507 for (i = 0, count = 0; i < 31; i++) { 4508 u_int32_t mask; 4509 4510 mask = 0x01 << i; 4511 if ((instr.integer & mask) != 0) 4512 count++; 4513 } 4514 if ((count & 0x01) == 0) 4515 instr.format1.parity = 1; 4516 } else { 4517 /* Compress the instruction for older sequencers */ 4518 if (fmt3_ins != NULL) { 4519 instr.integer = 4520 fmt3_ins->immediate 4521 | (fmt3_ins->source << 8) 4522 | (fmt3_ins->address << 16) 4523 | (fmt3_ins->opcode << 25); 4524 } else { 4525 instr.integer = 4526 fmt1_ins->immediate 4527 | (fmt1_ins->source << 8) 4528 | (fmt1_ins->destination << 16) 4529 | (fmt1_ins->ret << 24) 4530 | (fmt1_ins->opcode << 25); 4531 } 4532 } 4533 instr.integer = htole32(instr.integer); 4534 ahc_outsb(ahc, SEQRAM, instr.bytes, 4); 4535 break; 4536 default: 4537 panic("Unknown opcode encountered in seq program"); 4538 break; 4539 } 4540 } 4541 4542 static void 4543 ahc_set_recoveryscb(struct ahc_softc *ahc, struct scb *scb) 4544 { 4545 4546 if ((scb->flags & SCB_RECOVERY_SCB) == 0) { 4547 struct scb *scbp; 4548 4549 scb->flags |= SCB_RECOVERY_SCB; 4550 4551 /* 4552 * Take all queued, but not sent SCBs out of the equation. 4553 * Also ensure that no new CCBs are queued to us while we 4554 * try to fix this problem. 4555 */ 4556 scsipi_channel_freeze(&ahc->sc_channel, 1); 4557 if (ahc->features & AHC_TWIN) 4558 scsipi_channel_freeze(&ahc->sc_channel_b, 1); 4559 4560 /* 4561 * Go through all of our pending SCBs and remove 4562 * any scheduled timeouts for them. We will reschedule 4563 * them after we've successfully fixed this problem. 4564 */ 4565 scbp = ahc->pending_ccbs.lh_first; 4566 while (scbp != NULL) { 4567 callout_stop(&scbp->xs->xs_callout); 4568 scbp = scbp->plinks.le_next; 4569 } 4570 } 4571 } 4572 4573 static void 4574 ahc_timeout(void *arg) 4575 { 4576 struct scb *scb; 4577 struct ahc_softc *ahc; 4578 int s, found; 4579 u_int last_phase; 4580 int target; 4581 int lun; 4582 int i; 4583 char channel; 4584 4585 scb = (struct scb *)arg; 4586 ahc = 4587 (void *)scb->xs->xs_periph->periph_channel->chan_adapter->adapt_dev; 4588 4589 s = splbio(); 4590 4591 /* 4592 * Ensure that the card doesn't do anything 4593 * behind our back. Also make sure that we 4594 * didn't "just" miss an interrupt that would 4595 * affect this timeout. 4596 */ 4597 do { 4598 ahc_intr(ahc); 4599 pause_sequencer(ahc); 4600 } while (ahc_inb(ahc, INTSTAT) & INT_PEND); 4601 4602 if ((scb->flags & SCB_ACTIVE) == 0) { 4603 /* Previous timeout took care of me already */ 4604 printf("Timedout SCB handled by another timeout\n"); 4605 unpause_sequencer(ahc); 4606 splx(s); 4607 return; 4608 } 4609 4610 target = SCB_TARGET(scb); 4611 channel = SCB_CHANNEL(scb); 4612 lun = SCB_LUN(scb); 4613 4614 scsipi_printaddr(scb->xs->xs_periph); 4615 printf("SCB %x - timed out ", scb->hscb->tag); 4616 /* 4617 * Take a snapshot of the bus state and print out 4618 * some information so we can track down driver bugs. 4619 */ 4620 last_phase = ahc_inb(ahc, LASTPHASE); 4621 4622 for (i = 0; i < num_phases; i++) { 4623 if (last_phase == phase_table[i].phase) 4624 break; 4625 } 4626 printf("%s", phase_table[i].phasemsg); 4627 4628 printf(", SEQADDR == 0x%x\n", 4629 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8)); 4630 printf("SCSIRATE == 0x%x\n", ahc_inb(ahc, SCSIRATE)); 4631 4632 #ifdef AHC_DEBUG 4633 ahc_print_scb(scb); 4634 #endif 4635 4636 #if 0 4637 printf("SSTAT1 == 0x%x\n", ahc_inb(ahc, SSTAT1)); 4638 printf("SSTAT3 == 0x%x\n", ahc_inb(ahc, SSTAT3)); 4639 printf("SCSIPHASE == 0x%x\n", ahc_inb(ahc, SCSIPHASE)); 4640 printf("SCSIOFFSET == 0x%x\n", ahc_inb(ahc, SCSIOFFSET)); 4641 printf("SEQ_FLAGS == 0x%x\n", ahc_inb(ahc, SEQ_FLAGS)); 4642 printf("SCB_DATAPTR == 0x%x\n", ahc_inb(ahc, SCB_DATAPTR) 4643 | ahc_inb(ahc, SCB_DATAPTR + 1) << 8 4644 | ahc_inb(ahc, SCB_DATAPTR + 2) << 16 4645 | ahc_inb(ahc, SCB_DATAPTR + 3) << 24); 4646 printf("SCB_DATACNT == 0x%x\n", ahc_inb(ahc, SCB_DATACNT) 4647 | ahc_inb(ahc, SCB_DATACNT + 1) << 8 4648 | ahc_inb(ahc, SCB_DATACNT + 2) << 16); 4649 printf("SCB_SGCOUNT == 0x%x\n", ahc_inb(ahc, SCB_SGCOUNT)); 4650 printf("CCSCBCTL == 0x%x\n", ahc_inb(ahc, CCSCBCTL)); 4651 printf("CCSCBCNT == 0x%x\n", ahc_inb(ahc, CCSCBCNT)); 4652 printf("DFCNTRL == 0x%x\n", ahc_inb(ahc, DFCNTRL)); 4653 printf("DFSTATUS == 0x%x\n", ahc_inb(ahc, DFSTATUS)); 4654 printf("CCHCNT == 0x%x\n", ahc_inb(ahc, CCHCNT)); 4655 if (scb->sg_count > 0) { 4656 for (i = 0; i < scb->sg_count; i++) { 4657 printf("sg[%d] - Addr 0x%x : Length %d\n", 4658 i, 4659 le32toh(scb->sg_list[i].addr), 4660 le32toh(scb->sg_list[i].len)); 4661 } 4662 } 4663 #endif 4664 if (scb->flags & (SCB_DEVICE_RESET|SCB_ABORT)) { 4665 /* 4666 * Been down this road before. 4667 * Do a full bus reset. 4668 */ 4669 bus_reset: 4670 ahcsetccbstatus(scb->xs, XS_TIMEOUT); 4671 found = ahc_reset_channel(ahc, channel, /*Initiate Reset*/TRUE); 4672 printf("%s: Issued Channel %c Bus Reset. " 4673 "%d SCBs aborted\n", ahc_name(ahc), channel, found); 4674 } else { 4675 /* 4676 * If we are a target, transition to bus free and report 4677 * the timeout. 4678 * 4679 * The target/initiator that is holding up the bus may not 4680 * be the same as the one that triggered this timeout 4681 * (different commands have different timeout lengths). 4682 * If the bus is idle and we are actiing as the initiator 4683 * for this request, queue a BDR message to the timed out 4684 * target. Otherwise, if the timed out transaction is 4685 * active: 4686 * Initiator transaction: 4687 * Stuff the message buffer with a BDR message and assert 4688 * ATN in the hopes that the target will let go of the bus 4689 * and go to the mesgout phase. If this fails, we'll 4690 * get another timeout 2 seconds later which will attempt 4691 * a bus reset. 4692 * 4693 * Target transaction: 4694 * Transition to BUS FREE and report the error. 4695 * It's good to be the target! 4696 */ 4697 u_int active_scb_index; 4698 4699 active_scb_index = ahc_inb(ahc, SCB_TAG); 4700 4701 if (last_phase != P_BUSFREE 4702 && (active_scb_index < ahc->scb_data->numscbs)) { 4703 struct scb *active_scb; 4704 4705 /* 4706 * If the active SCB is not from our device, 4707 * assume that another device is hogging the bus 4708 * and wait for it's timeout to expire before 4709 * taking additional action. 4710 */ 4711 active_scb = &ahc->scb_data->scbarray[active_scb_index]; 4712 if (active_scb->hscb->tcl != scb->hscb->tcl) { 4713 u_int newtimeout; 4714 4715 scsipi_printaddr(scb->xs->xs_periph); 4716 printf("Other SCB Timeout%s", 4717 (scb->flags & SCB_OTHERTCL_TIMEOUT) != 0 4718 ? " again\n" : "\n"); 4719 scb->flags |= SCB_OTHERTCL_TIMEOUT; 4720 newtimeout = MAX(active_scb->xs->timeout, 4721 scb->xs->timeout); 4722 callout_reset(&scb->xs->xs_callout, 4723 mstohz(newtimeout), ahc_timeout, scb); 4724 splx(s); 4725 return; 4726 } 4727 4728 /* It's us */ 4729 if ((scb->hscb->control & TARGET_SCB) != 0) { 4730 4731 /* 4732 * Send back any queued up transactions 4733 * and properly record the error condition. 4734 */ 4735 ahc_freeze_devq(ahc, scb->xs->xs_periph); 4736 ahcsetccbstatus(scb->xs, XS_TIMEOUT); 4737 ahc_freeze_ccb(scb); 4738 ahc_done(ahc, scb); 4739 4740 /* Will clear us from the bus */ 4741 restart_sequencer(ahc); 4742 splx(s); 4743 return; 4744 } 4745 4746 ahc_set_recoveryscb(ahc, active_scb); 4747 ahc_outb(ahc, MSG_OUT, MSG_BUS_DEV_RESET); 4748 ahc_outb(ahc, SCSISIGO, last_phase|ATNO); 4749 scsipi_printaddr(active_scb->xs->xs_periph); 4750 printf("BDR message in message buffer\n"); 4751 active_scb->flags |= SCB_DEVICE_RESET; 4752 callout_reset(&active_scb->xs->xs_callout, 4753 2 * hz, ahc_timeout, active_scb); 4754 unpause_sequencer(ahc); 4755 } else { 4756 int disconnected; 4757 4758 /* XXX Shouldn't panic. Just punt instead */ 4759 if ((scb->hscb->control & TARGET_SCB) != 0) 4760 panic("Timed-out target SCB but bus idle"); 4761 4762 if (last_phase != P_BUSFREE 4763 && (ahc_inb(ahc, SSTAT0) & TARGET) != 0) { 4764 /* XXX What happened to the SCB? */ 4765 /* Hung target selection. Goto busfree */ 4766 printf("%s: Hung target selection\n", 4767 ahc_name(ahc)); 4768 restart_sequencer(ahc); 4769 splx(s); 4770 return; 4771 } 4772 4773 if (ahc_search_qinfifo(ahc, target, channel, lun, 4774 scb->hscb->tag, ROLE_INITIATOR, 4775 /*status*/0, SEARCH_COUNT) > 0) { 4776 disconnected = FALSE; 4777 } else { 4778 disconnected = TRUE; 4779 } 4780 4781 if (disconnected) { 4782 u_int active_scb; 4783 4784 ahc_set_recoveryscb(ahc, scb); 4785 /* 4786 * Simply set the MK_MESSAGE control bit. 4787 */ 4788 scb->hscb->control |= MK_MESSAGE; 4789 scb->flags |= SCB_QUEUED_MSG 4790 | SCB_DEVICE_RESET; 4791 4792 /* 4793 * Mark the cached copy of this SCB in the 4794 * disconnected list too, so that a reconnect 4795 * at this point causes a BDR or abort. 4796 */ 4797 active_scb = ahc_inb(ahc, SCBPTR); 4798 if (ahc_search_disc_list(ahc, target, 4799 channel, lun, 4800 scb->hscb->tag, 4801 /*stop_on_first*/TRUE, 4802 /*remove*/FALSE, 4803 /*save_state*/FALSE)) { 4804 u_int scb_control; 4805 4806 scb_control = ahc_inb(ahc, SCB_CONTROL); 4807 scb_control |= MK_MESSAGE; 4808 ahc_outb(ahc, SCB_CONTROL, scb_control); 4809 } 4810 ahc_outb(ahc, SCBPTR, active_scb); 4811 ahc_index_busy_tcl(ahc, scb->hscb->tcl, 4812 /*unbusy*/TRUE); 4813 4814 /* 4815 * Actually re-queue this SCB in case we can 4816 * select the device before it reconnects. 4817 * Clear out any entries in the QINFIFO first 4818 * so we are the next SCB for this target 4819 * to run. 4820 */ 4821 ahc_search_qinfifo(ahc, SCB_TARGET(scb), 4822 channel, SCB_LUN(scb), 4823 SCB_LIST_NULL, 4824 ROLE_INITIATOR, 4825 SCB_REQUEUE, 4826 SEARCH_COMPLETE); 4827 scsipi_printaddr(scb->xs->xs_periph); 4828 printf("Queuing a BDR SCB\n"); 4829 ahc->qinfifo[ahc->qinfifonext++] = 4830 scb->hscb->tag; 4831 4832 bus_dmamap_sync(ahc->parent_dmat, 4833 ahc->shared_data_dmamap, 4834 QINFIFO_OFFSET * 256, 256, 4835 BUS_DMASYNC_PREWRITE); 4836 4837 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4838 ahc_outb(ahc, HNSCB_QOFF, 4839 ahc->qinfifonext); 4840 } else { 4841 ahc_outb(ahc, KERNEL_QINPOS, 4842 ahc->qinfifonext); 4843 } 4844 callout_reset(&scb->xs->xs_callout, 2 * hz, 4845 ahc_timeout, scb); 4846 unpause_sequencer(ahc); 4847 } else { 4848 /* Go "immediatly" to the bus reset */ 4849 /* This shouldn't happen */ 4850 ahc_set_recoveryscb(ahc, scb); 4851 scsipi_printaddr(scb->xs->xs_periph); 4852 printf("SCB %x: Immediate reset. " 4853 "Flags = 0x%x\n", scb->hscb->tag, 4854 scb->flags); 4855 goto bus_reset; 4856 } 4857 } 4858 } 4859 splx(s); 4860 } 4861 4862 static int 4863 ahc_search_qinfifo(struct ahc_softc *ahc, int target, char channel, 4864 int lun, u_int tag, role_t role, scb_flag status, 4865 ahc_search_action action) 4866 { 4867 struct scb *scbp; 4868 u_int8_t qinpos; 4869 u_int8_t qintail; 4870 int found; 4871 4872 qinpos = ahc_inb(ahc, QINPOS); 4873 qintail = ahc->qinfifonext; 4874 found = 0; 4875 4876 /* 4877 * Start with an empty queue. Entries that are not chosen 4878 * for removal will be re-added to the queue as we go. 4879 */ 4880 ahc->qinfifonext = qinpos; 4881 4882 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 4883 QINFIFO_OFFSET * 256, 256, BUS_DMASYNC_POSTREAD); 4884 4885 while (qinpos != qintail) { 4886 scbp = &ahc->scb_data->scbarray[ahc->qinfifo[qinpos]]; 4887 if (ahc_match_scb(scbp, target, channel, lun, tag, role)) { 4888 /* 4889 * We found an scb that needs to be removed. 4890 */ 4891 switch (action) { 4892 case SEARCH_COMPLETE: 4893 if (!(scbp->xs->xs_status & XS_STS_DONE)) { 4894 scbp->flags |= status; 4895 scbp->xs->error = XS_NOERROR; 4896 } 4897 ahc_freeze_ccb(scbp); 4898 ahc_done(ahc, scbp); 4899 break; 4900 case SEARCH_COUNT: 4901 ahc->qinfifo[ahc->qinfifonext++] = 4902 scbp->hscb->tag; 4903 break; 4904 case SEARCH_REMOVE: 4905 break; 4906 } 4907 found++; 4908 } else { 4909 ahc->qinfifo[ahc->qinfifonext++] = scbp->hscb->tag; 4910 } 4911 qinpos++; 4912 } 4913 4914 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 4915 QINFIFO_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); 4916 4917 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4918 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 4919 } else { 4920 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 4921 } 4922 4923 return (found); 4924 } 4925 4926 /* 4927 * Abort all SCBs that match the given description (target/channel/lun/tag), 4928 * setting their status to the passed in status if the status has not already 4929 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer 4930 * is paused before it is called. 4931 */ 4932 static int 4933 ahc_abort_scbs(struct ahc_softc *ahc, int target, char channel, 4934 int lun, u_int tag, role_t role, int status) 4935 { 4936 struct scb *scbp; 4937 u_int active_scb; 4938 int i; 4939 int found; 4940 4941 /* restore this when we're done */ 4942 active_scb = ahc_inb(ahc, SCBPTR); 4943 4944 found = ahc_search_qinfifo(ahc, target, channel, lun, SCB_LIST_NULL, 4945 role, SCB_REQUEUE, SEARCH_COMPLETE); 4946 4947 /* 4948 * Search waiting for selection list. 4949 */ 4950 { 4951 u_int8_t next, prev; 4952 4953 next = ahc_inb(ahc, WAITING_SCBH); /* Start at head of list. */ 4954 prev = SCB_LIST_NULL; 4955 4956 while (next != SCB_LIST_NULL) { 4957 u_int8_t scb_index; 4958 4959 ahc_outb(ahc, SCBPTR, next); 4960 scb_index = ahc_inb(ahc, SCB_TAG); 4961 if (scb_index >= ahc->scb_data->numscbs) { 4962 panic("Waiting List inconsistency. " 4963 "SCB index == %d, yet numscbs == %d.", 4964 scb_index, ahc->scb_data->numscbs); 4965 } 4966 scbp = &ahc->scb_data->scbarray[scb_index]; 4967 if (ahc_match_scb(scbp, target, channel, 4968 lun, SCB_LIST_NULL, role)) { 4969 4970 next = ahc_abort_wscb(ahc, next, prev); 4971 } else { 4972 4973 prev = next; 4974 next = ahc_inb(ahc, SCB_NEXT); 4975 } 4976 } 4977 } 4978 /* 4979 * Go through the disconnected list and remove any entries we 4980 * have queued for completion, 0'ing their control byte too. 4981 * We save the active SCB and restore it ourselves, so there 4982 * is no reason for this search to restore it too. 4983 */ 4984 ahc_search_disc_list(ahc, target, channel, lun, tag, 4985 /*stop_on_first*/FALSE, /*remove*/TRUE, 4986 /*save_state*/FALSE); 4987 4988 /* 4989 * Go through the hardware SCB array looking for commands that 4990 * were active but not on any list. 4991 */ 4992 for(i = 0; i < ahc->scb_data->maxhscbs; i++) { 4993 u_int scbid; 4994 4995 ahc_outb(ahc, SCBPTR, i); 4996 scbid = ahc_inb(ahc, SCB_TAG); 4997 scbp = &ahc->scb_data->scbarray[scbid]; 4998 if (scbid < ahc->scb_data->numscbs 4999 && ahc_match_scb(scbp, target, channel, lun, tag, role)) 5000 ahc_add_curscb_to_free_list(ahc); 5001 } 5002 5003 /* 5004 * Go through the pending CCB list and look for 5005 * commands for this target that are still active. 5006 * These are other tagged commands that were 5007 * disconnected when the reset occurred. 5008 */ 5009 { 5010 struct scb *scb; 5011 5012 scb = ahc->pending_ccbs.lh_first; 5013 while (scb != NULL) { 5014 scbp = scb; 5015 scb = scb->plinks.le_next; 5016 if (ahc_match_scb(scbp, target, channel, 5017 lun, tag, role)) { 5018 if (!(scbp->xs->xs_status & XS_STS_DONE)) 5019 ahcsetccbstatus(scbp->xs, status); 5020 ahc_freeze_ccb(scbp); 5021 ahc_done(ahc, scbp); 5022 found++; 5023 } 5024 } 5025 } 5026 ahc_outb(ahc, SCBPTR, active_scb); 5027 return found; 5028 } 5029 5030 static int 5031 ahc_search_disc_list(struct ahc_softc *ahc, int target, char channel, 5032 int lun, u_int tag, int stop_on_first, int remove, 5033 int save_state) 5034 { 5035 struct scb *scbp; 5036 u_int next; 5037 u_int prev; 5038 u_int count; 5039 u_int active_scb; 5040 5041 count = 0; 5042 next = ahc_inb(ahc, DISCONNECTED_SCBH); 5043 prev = SCB_LIST_NULL; 5044 5045 if (save_state) { 5046 /* restore this when we're done */ 5047 active_scb = ahc_inb(ahc, SCBPTR); 5048 } else 5049 /* Silence compiler */ 5050 active_scb = SCB_LIST_NULL; 5051 5052 while (next != SCB_LIST_NULL) { 5053 u_int scb_index; 5054 5055 ahc_outb(ahc, SCBPTR, next); 5056 scb_index = ahc_inb(ahc, SCB_TAG); 5057 if (scb_index >= ahc->scb_data->numscbs) { 5058 panic("Disconnected List inconsistency. " 5059 "SCB index == %d, yet numscbs == %d.", 5060 scb_index, ahc->scb_data->numscbs); 5061 } 5062 scbp = &ahc->scb_data->scbarray[scb_index]; 5063 if (ahc_match_scb(scbp, target, channel, lun, 5064 tag, ROLE_INITIATOR)) { 5065 count++; 5066 if (remove) { 5067 next = 5068 ahc_rem_scb_from_disc_list(ahc, prev, next); 5069 } else { 5070 prev = next; 5071 next = ahc_inb(ahc, SCB_NEXT); 5072 } 5073 if (stop_on_first) 5074 break; 5075 } else { 5076 prev = next; 5077 next = ahc_inb(ahc, SCB_NEXT); 5078 } 5079 } 5080 if (save_state) 5081 ahc_outb(ahc, SCBPTR, active_scb); 5082 return (count); 5083 } 5084 5085 static u_int 5086 ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, u_int prev, u_int scbptr) 5087 { 5088 u_int next; 5089 5090 ahc_outb(ahc, SCBPTR, scbptr); 5091 next = ahc_inb(ahc, SCB_NEXT); 5092 5093 ahc_outb(ahc, SCB_CONTROL, 0); 5094 5095 ahc_add_curscb_to_free_list(ahc); 5096 5097 if (prev != SCB_LIST_NULL) { 5098 ahc_outb(ahc, SCBPTR, prev); 5099 ahc_outb(ahc, SCB_NEXT, next); 5100 } else 5101 ahc_outb(ahc, DISCONNECTED_SCBH, next); 5102 5103 return (next); 5104 } 5105 5106 static void 5107 ahc_add_curscb_to_free_list(struct ahc_softc *ahc) 5108 { 5109 /* Invalidate the tag so that ahc_find_scb doesn't think it's active */ 5110 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); 5111 5112 ahc_outb(ahc, SCB_NEXT, ahc_inb(ahc, FREE_SCBH)); 5113 ahc_outb(ahc, FREE_SCBH, ahc_inb(ahc, SCBPTR)); 5114 } 5115 5116 /* 5117 * Manipulate the waiting for selection list and return the 5118 * scb that follows the one that we remove. 5119 */ 5120 static u_int 5121 ahc_abort_wscb(struct ahc_softc *ahc, u_int scbpos, u_int prev) 5122 { 5123 u_int curscb, next; 5124 5125 /* 5126 * Select the SCB we want to abort and 5127 * pull the next pointer out of it. 5128 */ 5129 curscb = ahc_inb(ahc, SCBPTR); 5130 ahc_outb(ahc, SCBPTR, scbpos); 5131 next = ahc_inb(ahc, SCB_NEXT); 5132 5133 /* Clear the necessary fields */ 5134 ahc_outb(ahc, SCB_CONTROL, 0); 5135 5136 ahc_add_curscb_to_free_list(ahc); 5137 5138 /* update the waiting list */ 5139 if (prev == SCB_LIST_NULL) { 5140 /* First in the list */ 5141 ahc_outb(ahc, WAITING_SCBH, next); 5142 5143 /* 5144 * Ensure we aren't attempting to perform 5145 * selection for this entry. 5146 */ 5147 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO)); 5148 } else { 5149 /* 5150 * Select the scb that pointed to us 5151 * and update its next pointer. 5152 */ 5153 ahc_outb(ahc, SCBPTR, prev); 5154 ahc_outb(ahc, SCB_NEXT, next); 5155 } 5156 5157 /* 5158 * Point us back at the original scb position. 5159 */ 5160 ahc_outb(ahc, SCBPTR, curscb); 5161 return next; 5162 } 5163 5164 static void 5165 ahc_clear_intstat(struct ahc_softc *ahc) 5166 { 5167 /* Clear any interrupt conditions this may have caused */ 5168 ahc_outb(ahc, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO); 5169 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI 5170 |CLRBUSFREE|CLRSCSIPERR|CLRPHASECHG| 5171 CLRREQINIT); 5172 ahc_outb(ahc, CLRINT, CLRSCSIINT); 5173 } 5174 5175 static void 5176 ahc_reset_current_bus(struct ahc_softc *ahc) 5177 { 5178 u_int8_t scsiseq; 5179 5180 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENSCSIRST); 5181 scsiseq = ahc_inb(ahc, SCSISEQ); 5182 ahc_outb(ahc, SCSISEQ, scsiseq | SCSIRSTO); 5183 DELAY(AHC_BUSRESET_DELAY); 5184 /* Turn off the bus reset */ 5185 ahc_outb(ahc, SCSISEQ, scsiseq & ~SCSIRSTO); 5186 5187 ahc_clear_intstat(ahc); 5188 5189 /* Re-enable reset interrupts */ 5190 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) | ENSCSIRST); 5191 } 5192 5193 static int 5194 ahc_reset_channel(struct ahc_softc *ahc, char channel, int initiate_reset) 5195 { 5196 u_int initiator, target, max_scsiid; 5197 u_int sblkctl; 5198 u_int our_id; 5199 int found; 5200 int restart_needed; 5201 char cur_channel; 5202 5203 ahc->pending_device = NULL; 5204 5205 pause_sequencer(ahc); 5206 5207 /* 5208 * Run our command complete fifos to ensure that we perform 5209 * completion processing on any commands that 'completed' 5210 * before the reset occurred. 5211 */ 5212 ahc_run_qoutfifo(ahc); 5213 5214 /* 5215 * Reset the bus if we are initiating this reset 5216 */ 5217 sblkctl = ahc_inb(ahc, SBLKCTL); 5218 cur_channel = 'A'; 5219 if ((ahc->features & AHC_TWIN) != 0 5220 && ((sblkctl & SELBUSB) != 0)) 5221 cur_channel = 'B'; 5222 if (cur_channel != channel) { 5223 /* Case 1: Command for another bus is active 5224 * Stealthily reset the other bus without 5225 * upsetting the current bus. 5226 */ 5227 ahc_outb(ahc, SBLKCTL, sblkctl ^ SELBUSB); 5228 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 5229 ahc_outb(ahc, SCSISEQ, 5230 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 5231 if (initiate_reset) 5232 ahc_reset_current_bus(ahc); 5233 ahc_clear_intstat(ahc); 5234 ahc_outb(ahc, SBLKCTL, sblkctl); 5235 restart_needed = FALSE; 5236 } else { 5237 /* Case 2: A command from this bus is active or we're idle */ 5238 ahc_clear_msg_state(ahc); 5239 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 5240 ahc_outb(ahc, SCSISEQ, 5241 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 5242 if (initiate_reset) 5243 ahc_reset_current_bus(ahc); 5244 ahc_clear_intstat(ahc); 5245 5246 /* 5247 * Since we are going to restart the sequencer, avoid 5248 * a race in the sequencer that could cause corruption 5249 * of our Q pointers by starting over from index 0. 5250 */ 5251 ahc->qoutfifonext = 0; 5252 if ((ahc->features & AHC_QUEUE_REGS) != 0) 5253 ahc_outb(ahc, SDSCB_QOFF, 0); 5254 else 5255 ahc_outb(ahc, QOUTPOS, 0); 5256 restart_needed = TRUE; 5257 } 5258 5259 /* 5260 * Clean up all the state information for the 5261 * pending transactions on this bus. 5262 */ 5263 found = ahc_abort_scbs(ahc, AHC_TARGET_WILDCARD, channel, 5264 AHC_LUN_WILDCARD, SCB_LIST_NULL, 5265 ROLE_UNKNOWN, XS_RESET); 5266 if (channel == 'B') { 5267 our_id = ahc->our_id_b; 5268 } else { 5269 our_id = ahc->our_id; 5270 } 5271 5272 max_scsiid = (ahc->features & AHC_WIDE) ? 15 : 7; 5273 5274 /* 5275 * Revert to async/narrow transfers until we renegotiate. 5276 */ 5277 for (target = 0; target <= max_scsiid; target++) { 5278 5279 if (ahc->enabled_targets[target] == NULL) 5280 continue; 5281 for (initiator = 0; initiator <= max_scsiid; initiator++) { 5282 struct ahc_devinfo devinfo; 5283 5284 ahc_compile_devinfo(&devinfo, target, initiator, 5285 AHC_LUN_WILDCARD, 5286 channel, ROLE_UNKNOWN); 5287 ahc_set_width(ahc, &devinfo, 5288 MSG_EXT_WDTR_BUS_8_BIT, 5289 AHC_TRANS_CUR, /*paused*/TRUE, FALSE); 5290 ahc_set_syncrate(ahc, &devinfo, 5291 /*syncrate*/NULL, /*period*/0, 5292 /*offset*/0, AHC_TRANS_CUR, 5293 /*paused*/TRUE, FALSE); 5294 ahc_update_xfer_mode(ahc, &devinfo); 5295 } 5296 } 5297 5298 if (restart_needed) 5299 restart_sequencer(ahc); 5300 else 5301 unpause_sequencer(ahc); 5302 return found; 5303 } 5304 5305 static int 5306 ahc_match_scb(struct scb *scb, int target, char channel, 5307 int lun, u_int tag, role_t role) 5308 { 5309 int targ = SCB_TARGET(scb); 5310 char chan = SCB_CHANNEL(scb); 5311 int slun = SCB_LUN(scb); 5312 int match; 5313 5314 match = ((chan == channel) || (channel == ALL_CHANNELS)); 5315 if (match != 0) 5316 match = ((targ == target) || (target == AHC_TARGET_WILDCARD)); 5317 if (match != 0) 5318 match = ((lun == slun) || (lun == AHC_LUN_WILDCARD)); 5319 5320 return match; 5321 } 5322 5323 static void 5324 ahc_construct_sdtr(struct ahc_softc *ahc, u_int period, u_int offset) 5325 { 5326 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 5327 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR_LEN; 5328 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR; 5329 ahc->msgout_buf[ahc->msgout_index++] = period; 5330 ahc->msgout_buf[ahc->msgout_index++] = offset; 5331 ahc->msgout_len += 5; 5332 } 5333 5334 static void 5335 ahc_construct_wdtr(struct ahc_softc *ahc, u_int bus_width) 5336 { 5337 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 5338 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR_LEN; 5339 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR; 5340 ahc->msgout_buf[ahc->msgout_index++] = bus_width; 5341 ahc->msgout_len += 4; 5342 } 5343 5344 static void 5345 ahc_calc_residual(struct scb *scb) 5346 { 5347 struct hardware_scb *hscb; 5348 5349 hscb = scb->hscb; 5350 5351 /* 5352 * If the disconnected flag is still set, this is bogus 5353 * residual information left over from a sequencer 5354 * pagin/pageout, so ignore this case. 5355 */ 5356 if ((scb->hscb->control & DISCONNECTED) == 0) { 5357 u_int32_t resid; 5358 int resid_sgs; 5359 int sg; 5360 5361 /* 5362 * Remainder of the SG where the transfer 5363 * stopped. 5364 */ 5365 resid = (hscb->residual_data_count[2] << 16) 5366 | (hscb->residual_data_count[1] <<8) 5367 | (hscb->residual_data_count[0]); 5368 5369 /* 5370 * Add up the contents of all residual 5371 * SG segments that are after the SG where 5372 * the transfer stopped. 5373 */ 5374 resid_sgs = scb->hscb->residual_SG_count - 1/*current*/; 5375 sg = scb->sg_count - resid_sgs; 5376 while (resid_sgs > 0) { 5377 5378 resid += le32toh(scb->sg_list[sg].len); 5379 sg++; 5380 resid_sgs--; 5381 } 5382 scb->xs->resid = resid; 5383 } 5384 5385 /* 5386 * Clean out the residual information in this SCB for its 5387 * next consumer. 5388 */ 5389 hscb->residual_SG_count = 0; 5390 5391 #ifdef AHC_DEBUG 5392 if (ahc_debug & AHC_SHOWMISC) { 5393 scsipi_printaddr(scb->xs->xs_periph); 5394 printf("Handled Residual of %ld bytes\n" ,(long)scb->xs->resid); 5395 } 5396 #endif 5397 } 5398 5399 static void 5400 ahc_update_pending_syncrates(struct ahc_softc *ahc) 5401 { 5402 struct scb *scb; 5403 int pending_ccb_count; 5404 int i; 5405 u_int saved_scbptr; 5406 5407 /* 5408 * Traverse the pending SCB list and ensure that all of the 5409 * SCBs there have the proper settings. 5410 */ 5411 scb = LIST_FIRST(&ahc->pending_ccbs); 5412 pending_ccb_count = 0; 5413 while (scb != NULL) { 5414 struct ahc_devinfo devinfo; 5415 struct scsipi_xfer *xs; 5416 struct scb *pending_scb; 5417 struct hardware_scb *pending_hscb; 5418 struct ahc_initiator_tinfo *tinfo; 5419 struct tmode_tstate *tstate; 5420 u_int our_id, remote_id; 5421 5422 xs = scb->xs; 5423 pending_scb = scb; 5424 pending_hscb = pending_scb->hscb; 5425 our_id = SCB_IS_SCSIBUS_B(pending_scb) 5426 ? ahc->our_id_b : ahc->our_id; 5427 remote_id = xs->xs_periph->periph_target; 5428 ahc_compile_devinfo(&devinfo, our_id, remote_id, 5429 SCB_LUN(pending_scb), 5430 SCB_CHANNEL(pending_scb), 5431 ROLE_UNKNOWN); 5432 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel, 5433 our_id, remote_id, &tstate); 5434 pending_hscb->control &= ~ULTRAENB; 5435 if ((tstate->ultraenb & devinfo.target_mask) != 0) 5436 pending_hscb->control |= ULTRAENB; 5437 pending_hscb->scsirate = tinfo->scsirate; 5438 pending_hscb->scsioffset = tinfo->current.offset; 5439 pending_ccb_count++; 5440 scb = LIST_NEXT(scb, plinks); 5441 } 5442 5443 if (pending_ccb_count == 0) 5444 return; 5445 5446 saved_scbptr = ahc_inb(ahc, SCBPTR); 5447 /* Ensure that the hscbs down on the card match the new information */ 5448 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 5449 u_int scb_tag; 5450 5451 ahc_outb(ahc, SCBPTR, i); 5452 scb_tag = ahc_inb(ahc, SCB_TAG); 5453 if (scb_tag != SCB_LIST_NULL) { 5454 struct ahc_devinfo devinfo; 5455 struct scb *pending_scb; 5456 struct scsipi_xfer *xs; 5457 struct hardware_scb *pending_hscb; 5458 struct ahc_initiator_tinfo *tinfo; 5459 struct tmode_tstate *tstate; 5460 u_int our_id, remote_id; 5461 u_int control; 5462 5463 pending_scb = &ahc->scb_data->scbarray[scb_tag]; 5464 if (pending_scb->flags == SCB_FREE) 5465 continue; 5466 pending_hscb = pending_scb->hscb; 5467 xs = pending_scb->xs; 5468 our_id = SCB_IS_SCSIBUS_B(pending_scb) 5469 ? ahc->our_id_b : ahc->our_id; 5470 remote_id = xs->xs_periph->periph_target; 5471 ahc_compile_devinfo(&devinfo, our_id, remote_id, 5472 SCB_LUN(pending_scb), 5473 SCB_CHANNEL(pending_scb), 5474 ROLE_UNKNOWN); 5475 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel, 5476 our_id, remote_id, &tstate); 5477 control = ahc_inb(ahc, SCB_CONTROL); 5478 control &= ~ULTRAENB; 5479 if ((tstate->ultraenb & devinfo.target_mask) != 0) 5480 control |= ULTRAENB; 5481 ahc_outb(ahc, SCB_CONTROL, control); 5482 ahc_outb(ahc, SCB_SCSIRATE, tinfo->scsirate); 5483 ahc_outb(ahc, SCB_SCSIOFFSET, tinfo->current.offset); 5484 } 5485 } 5486 ahc_outb(ahc, SCBPTR, saved_scbptr); 5487 } 5488 5489 #if UNUSED 5490 static void 5491 ahc_dump_targcmd(struct target_cmd *cmd) 5492 { 5493 u_int8_t *byte; 5494 u_int8_t *last_byte; 5495 int i; 5496 5497 byte = &cmd->initiator_channel; 5498 /* Debugging info for received commands */ 5499 last_byte = &cmd[1].initiator_channel; 5500 5501 i = 0; 5502 while (byte < last_byte) { 5503 if (i == 0) 5504 printf("\t"); 5505 printf("%#x", *byte++); 5506 i++; 5507 if (i == 8) { 5508 printf("\n"); 5509 i = 0; 5510 } else { 5511 printf(", "); 5512 } 5513 } 5514 } 5515 #endif 5516 5517 static void 5518 ahc_shutdown(void *arg) 5519 { 5520 struct ahc_softc *ahc; 5521 int i; 5522 u_int sxfrctl1_a, sxfrctl1_b; 5523 5524 ahc = (struct ahc_softc *)arg; 5525 5526 pause_sequencer(ahc); 5527 5528 /* 5529 * Preserve the value of the SXFRCTL1 register for all channels. 5530 * It contains settings that affect termination and we don't want 5531 * to disturb the integrity of the bus during shutdown in case 5532 * we are in a multi-initiator setup. 5533 */ 5534 sxfrctl1_b = 0; 5535 if ((ahc->features & AHC_TWIN) != 0) { 5536 u_int sblkctl; 5537 5538 sblkctl = ahc_inb(ahc, SBLKCTL); 5539 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); 5540 sxfrctl1_b = ahc_inb(ahc, SXFRCTL1); 5541 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); 5542 } 5543 5544 sxfrctl1_a = ahc_inb(ahc, SXFRCTL1); 5545 5546 /* This will reset most registers to 0, but not all */ 5547 ahc_reset(ahc); 5548 5549 if ((ahc->features & AHC_TWIN) != 0) { 5550 u_int sblkctl; 5551 5552 sblkctl = ahc_inb(ahc, SBLKCTL); 5553 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); 5554 ahc_outb(ahc, SXFRCTL1, sxfrctl1_b); 5555 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); 5556 } 5557 ahc_outb(ahc, SXFRCTL1, sxfrctl1_a); 5558 5559 ahc_outb(ahc, SCSISEQ, 0); 5560 ahc_outb(ahc, SXFRCTL0, 0); 5561 ahc_outb(ahc, DSPCISTATUS, 0); 5562 5563 for (i = TARG_SCSIRATE; i < HA_274_BIOSCTRL; i++) 5564 ahc_outb(ahc, i, 0); 5565 } 5566 5567 #if defined(AHC_DEBUG) && 0 5568 static void 5569 ahc_dumptinfo(struct ahc_softc *ahc, struct ahc_initiator_tinfo *tinfo) 5570 { 5571 printf("%s: tinfo: rate %u\n", ahc_name(ahc), tinfo->scsirate); 5572 5573 printf("\tcurrent:\n"); 5574 printf("\t\twidth %u period %u offset %u flags %x\n", 5575 tinfo->current.width, tinfo->current.period, 5576 tinfo->current.offset, tinfo->current.ppr_flags); 5577 5578 printf("\tgoal:\n"); 5579 printf("\t\twidth %u period %u offset %u flags %x\n", 5580 tinfo->goal.width, tinfo->goal.period, 5581 tinfo->goal.offset, tinfo->goal.ppr_flags); 5582 5583 printf("\tuser:\n"); 5584 printf("\t\twidth %u period %u offset %u flags %x\n", 5585 tinfo->user.width, tinfo->user.period, 5586 tinfo->user.offset, tinfo->user.ppr_flags); 5587 } 5588 #endif 5589 5590 static int 5591 ahc_istagged_device(struct ahc_softc *ahc, struct scsipi_xfer *xs, 5592 int nocmdcheck) 5593 { 5594 #ifdef AHC_NO_TAGS 5595 return 0; 5596 #else 5597 char channel; 5598 u_int our_id, target; 5599 struct tmode_tstate *tstate; 5600 struct ahc_devinfo devinfo; 5601 5602 channel = SIM_CHANNEL(ahc, xs->xs_periph); 5603 our_id = SIM_SCSI_ID(ahc, xs->xs_periph); 5604 target = xs->xs_periph->periph_target; 5605 (void)ahc_fetch_transinfo(ahc, channel, our_id, target, &tstate); 5606 5607 ahc_compile_devinfo(&devinfo, our_id, target, 5608 xs->xs_periph->periph_lun, channel, ROLE_INITIATOR); 5609 5610 return (tstate->tagenable & devinfo.target_mask); 5611 #endif 5612 } 5613