1*30296cb2Schristos /* $NetBSD: aic7xxx_inline.h,v 1.15 2018/04/19 21:50:08 christos Exp $ */
22d41d30fSfvdl
3ccadc2cbSfvdl /*
4ccadc2cbSfvdl * Inline routines shareable across OS platforms.
5ccadc2cbSfvdl *
6ccadc2cbSfvdl * Copyright (c) 1994-2001 Justin T. Gibbs.
7ccadc2cbSfvdl * Copyright (c) 2000-2001 Adaptec Inc.
8ccadc2cbSfvdl * All rights reserved.
9ccadc2cbSfvdl *
10ccadc2cbSfvdl * Redistribution and use in source and binary forms, with or without
11ccadc2cbSfvdl * modification, are permitted provided that the following conditions
12ccadc2cbSfvdl * are met:
13ccadc2cbSfvdl * 1. Redistributions of source code must retain the above copyright
14ccadc2cbSfvdl * notice, this list of conditions, and the following disclaimer,
15ccadc2cbSfvdl * without modification.
16ccadc2cbSfvdl * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17ccadc2cbSfvdl * substantially similar to the "NO WARRANTY" disclaimer below
18ccadc2cbSfvdl * ("Disclaimer") and any redistribution must be conditioned upon
19ccadc2cbSfvdl * including a substantially similar Disclaimer requirement for further
20ccadc2cbSfvdl * binary redistribution.
21ccadc2cbSfvdl * 3. Neither the names of the above-listed copyright holders nor the names
22ccadc2cbSfvdl * of any contributors may be used to endorse or promote products derived
23ccadc2cbSfvdl * from this software without specific prior written permission.
24ccadc2cbSfvdl *
25ccadc2cbSfvdl * Alternatively, this software may be distributed under the terms of the
26ccadc2cbSfvdl * GNU General Public License ("GPL") version 2 as published by the Free
27ccadc2cbSfvdl * Software Foundation.
28ccadc2cbSfvdl *
29ccadc2cbSfvdl * NO WARRANTY
30ccadc2cbSfvdl * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31ccadc2cbSfvdl * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32ccadc2cbSfvdl * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
33ccadc2cbSfvdl * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34ccadc2cbSfvdl * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
35ccadc2cbSfvdl * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
36ccadc2cbSfvdl * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
37ccadc2cbSfvdl * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
38ccadc2cbSfvdl * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
39ccadc2cbSfvdl * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
40ccadc2cbSfvdl * POSSIBILITY OF SUCH DAMAGES.
41ccadc2cbSfvdl *
42ccadc2cbSfvdl * //depot/aic7xxx/aic7xxx/aic7xxx_inline.h#39 $
43ccadc2cbSfvdl *
44ccadc2cbSfvdl * $FreeBSD: /repoman/r/ncvs/src/sys/dev/aic7xxx/aic7xxx_inline.h,v 1.20 2003/01/20 20:44:55 gibbs Exp $
45ccadc2cbSfvdl */
46ccadc2cbSfvdl /*
47ccadc2cbSfvdl * Ported from FreeBSD by Pascal Renauld, Network Storage Solutions, Inc. - April 2003
48ccadc2cbSfvdl */
49ccadc2cbSfvdl
50ccadc2cbSfvdl #ifndef _AIC7XXX_INLINE_H_
51ccadc2cbSfvdl #define _AIC7XXX_INLINE_H_
52ccadc2cbSfvdl
53ccadc2cbSfvdl /************************* Sequencer Execution Control ************************/
54fbae48b9Sperry static __inline void ahc_pause_bug_fix(struct ahc_softc *ahc);
55fbae48b9Sperry static __inline int ahc_is_paused(struct ahc_softc *ahc);
56fbae48b9Sperry static __inline void ahc_pause(struct ahc_softc *ahc);
57fbae48b9Sperry static __inline void ahc_unpause(struct ahc_softc *ahc);
58ccadc2cbSfvdl
59ccadc2cbSfvdl /*
60ccadc2cbSfvdl * Work around any chip bugs related to halting sequencer execution.
61ccadc2cbSfvdl * On Ultra2 controllers, we must clear the CIOBUS stretch signal by
62ccadc2cbSfvdl * reading a register that will set this signal and deassert it.
63ccadc2cbSfvdl * Without this workaround, if the chip is paused, by an interrupt or
64ccadc2cbSfvdl * manual pause while accessing scb ram, accesses to certain registers
65ccadc2cbSfvdl * will hang the system (infinite pci retries).
66ccadc2cbSfvdl */
67fbae48b9Sperry static __inline void
ahc_pause_bug_fix(struct ahc_softc * ahc)68ccadc2cbSfvdl ahc_pause_bug_fix(struct ahc_softc *ahc)
69ccadc2cbSfvdl {
70ccadc2cbSfvdl if ((ahc->features & AHC_ULTRA2) != 0)
71ccadc2cbSfvdl (void)ahc_inb(ahc, CCSCBCTL);
72ccadc2cbSfvdl }
73ccadc2cbSfvdl
74ccadc2cbSfvdl /*
75ccadc2cbSfvdl * Determine whether the sequencer has halted code execution.
76ccadc2cbSfvdl * Returns non-zero status if the sequencer is stopped.
77ccadc2cbSfvdl */
78fbae48b9Sperry static __inline int
ahc_is_paused(struct ahc_softc * ahc)79ccadc2cbSfvdl ahc_is_paused(struct ahc_softc *ahc)
80ccadc2cbSfvdl {
81ccadc2cbSfvdl return ((ahc_inb(ahc, HCNTRL) & PAUSE) != 0);
82ccadc2cbSfvdl }
83ccadc2cbSfvdl
84ccadc2cbSfvdl /*
85ccadc2cbSfvdl * Request that the sequencer stop and wait, indefinitely, for it
86ccadc2cbSfvdl * to stop. The sequencer will only acknowledge that it is paused
87ccadc2cbSfvdl * once it has reached an instruction boundary and PAUSEDIS is
88ccadc2cbSfvdl * cleared in the SEQCTL register. The sequencer may use PAUSEDIS
89ccadc2cbSfvdl * for critical sections.
90ccadc2cbSfvdl */
91fbae48b9Sperry static __inline void
ahc_pause(struct ahc_softc * ahc)92ccadc2cbSfvdl ahc_pause(struct ahc_softc *ahc)
93ccadc2cbSfvdl {
94ccadc2cbSfvdl ahc_outb(ahc, HCNTRL, ahc->pause);
95ccadc2cbSfvdl
96ccadc2cbSfvdl /*
97ccadc2cbSfvdl * Since the sequencer can disable pausing in a critical section, we
98ccadc2cbSfvdl * must loop until it actually stops.
99ccadc2cbSfvdl */
100ccadc2cbSfvdl while (ahc_is_paused(ahc) == 0)
101ccadc2cbSfvdl ;
102ccadc2cbSfvdl
103ccadc2cbSfvdl ahc_pause_bug_fix(ahc);
104ccadc2cbSfvdl }
105ccadc2cbSfvdl
106ccadc2cbSfvdl /*
107ccadc2cbSfvdl * Allow the sequencer to continue program execution.
108ccadc2cbSfvdl * We check here to ensure that no additional interrupt
109ccadc2cbSfvdl * sources that would cause the sequencer to halt have been
110ccadc2cbSfvdl * asserted. If, for example, a SCSI bus reset is detected
111ccadc2cbSfvdl * while we are fielding a different, pausing, interrupt type,
112ccadc2cbSfvdl * we don't want to release the sequencer before going back
113ccadc2cbSfvdl * into our interrupt handler and dealing with this new
114ccadc2cbSfvdl * condition.
115ccadc2cbSfvdl */
116fbae48b9Sperry static __inline void
ahc_unpause(struct ahc_softc * ahc)117ccadc2cbSfvdl ahc_unpause(struct ahc_softc *ahc)
118ccadc2cbSfvdl {
119ccadc2cbSfvdl if ((ahc_inb(ahc, INTSTAT) & (SCSIINT | SEQINT | BRKADRINT)) == 0)
120ccadc2cbSfvdl ahc_outb(ahc, HCNTRL, ahc->unpause);
121ccadc2cbSfvdl }
122ccadc2cbSfvdl
123ccadc2cbSfvdl /*********************** Untagged Transaction Routines ************************/
124fbae48b9Sperry static __inline void ahc_freeze_untagged_queues(struct ahc_softc *ahc);
125fbae48b9Sperry static __inline void ahc_release_untagged_queues(struct ahc_softc *ahc);
126ccadc2cbSfvdl
127ccadc2cbSfvdl /*
128ccadc2cbSfvdl * Block our completion routine from starting the next untagged
129ccadc2cbSfvdl * transaction for this target or target lun.
130ccadc2cbSfvdl */
131fbae48b9Sperry static __inline void
ahc_freeze_untagged_queues(struct ahc_softc * ahc)132ccadc2cbSfvdl ahc_freeze_untagged_queues(struct ahc_softc *ahc)
133ccadc2cbSfvdl {
134ccadc2cbSfvdl if ((ahc->flags & AHC_SCB_BTT) == 0)
135ccadc2cbSfvdl ahc->untagged_queue_lock++;
136ccadc2cbSfvdl }
137ccadc2cbSfvdl
138ccadc2cbSfvdl /*
139ccadc2cbSfvdl * Allow the next untagged transaction for this target or target lun
140ccadc2cbSfvdl * to be executed. We use a counting semaphore to allow the lock
141ccadc2cbSfvdl * to be acquired recursively. Once the count drops to zero, the
142ccadc2cbSfvdl * transaction queues will be run.
143ccadc2cbSfvdl */
144fbae48b9Sperry static __inline void
ahc_release_untagged_queues(struct ahc_softc * ahc)145ccadc2cbSfvdl ahc_release_untagged_queues(struct ahc_softc *ahc)
146ccadc2cbSfvdl {
147ccadc2cbSfvdl if ((ahc->flags & AHC_SCB_BTT) == 0) {
148ccadc2cbSfvdl ahc->untagged_queue_lock--;
149ccadc2cbSfvdl if (ahc->untagged_queue_lock == 0)
150ccadc2cbSfvdl ahc_run_untagged_queues(ahc);
151ccadc2cbSfvdl }
152ccadc2cbSfvdl }
153ccadc2cbSfvdl
154ccadc2cbSfvdl /************************** Memory mapping routines ***************************/
155fbae48b9Sperry static __inline struct ahc_dma_seg *
156ccadc2cbSfvdl ahc_sg_bus_to_virt(struct scb *scb,
157ccadc2cbSfvdl uint32_t sg_busaddr);
158fbae48b9Sperry static __inline uint32_t
159ccadc2cbSfvdl ahc_sg_virt_to_bus(struct scb *scb,
160ccadc2cbSfvdl struct ahc_dma_seg *sg);
161fbae48b9Sperry static __inline uint32_t
162ccadc2cbSfvdl ahc_hscb_busaddr(struct ahc_softc *ahc, u_int index);
163fbae48b9Sperry static __inline void ahc_sync_scb(struct ahc_softc *ahc,
164ccadc2cbSfvdl struct scb *scb, int op);
165fbae48b9Sperry static __inline void ahc_sync_sglist(struct ahc_softc *ahc,
166ccadc2cbSfvdl struct scb *scb, int op);
167fbae48b9Sperry static __inline uint32_t
168ccadc2cbSfvdl ahc_targetcmd_offset(struct ahc_softc *ahc,
169ccadc2cbSfvdl u_int index);
170ccadc2cbSfvdl
171fbae48b9Sperry static __inline struct ahc_dma_seg *
ahc_sg_bus_to_virt(struct scb * scb,uint32_t sg_busaddr)172ccadc2cbSfvdl ahc_sg_bus_to_virt(struct scb *scb, uint32_t sg_busaddr)
173ccadc2cbSfvdl {
174ccadc2cbSfvdl int sg_index;
175ccadc2cbSfvdl
176ccadc2cbSfvdl sg_index = (sg_busaddr - scb->sg_list_phys)/sizeof(struct ahc_dma_seg);
177ccadc2cbSfvdl /* sg_list_phys points to entry 1, not 0 */
178ccadc2cbSfvdl sg_index++;
179ccadc2cbSfvdl
180ccadc2cbSfvdl return (&scb->sg_list[sg_index]);
181ccadc2cbSfvdl }
182ccadc2cbSfvdl
183fbae48b9Sperry static __inline uint32_t
ahc_sg_virt_to_bus(struct scb * scb,struct ahc_dma_seg * sg)184ccadc2cbSfvdl ahc_sg_virt_to_bus(struct scb *scb, struct ahc_dma_seg *sg)
185ccadc2cbSfvdl {
186ccadc2cbSfvdl int sg_index;
187ccadc2cbSfvdl
188ccadc2cbSfvdl /* sg_list_phys points to entry 1, not 0 */
189ccadc2cbSfvdl sg_index = sg - &scb->sg_list[1];
190ccadc2cbSfvdl
191ccadc2cbSfvdl return (scb->sg_list_phys + (sg_index * sizeof(*scb->sg_list)));
192ccadc2cbSfvdl }
193ccadc2cbSfvdl
194fbae48b9Sperry static __inline uint32_t
ahc_hscb_busaddr(struct ahc_softc * ahc,u_int index)195ccadc2cbSfvdl ahc_hscb_busaddr(struct ahc_softc *ahc, u_int index)
196ccadc2cbSfvdl {
197ccadc2cbSfvdl return (ahc->scb_data->hscb_busaddr
198ccadc2cbSfvdl + (sizeof(struct hardware_scb) * index));
199ccadc2cbSfvdl }
200ccadc2cbSfvdl
201fbae48b9Sperry static __inline void
ahc_sync_scb(struct ahc_softc * ahc,struct scb * scb,int op)202ccadc2cbSfvdl ahc_sync_scb(struct ahc_softc *ahc, struct scb *scb, int op)
203ccadc2cbSfvdl {
204ccadc2cbSfvdl ahc_dmamap_sync(ahc, ahc->parent_dmat,
205ccadc2cbSfvdl ahc->scb_data->hscb_dmamap,
206ccadc2cbSfvdl /*offset*/(scb->hscb - ahc->scb_data->hscbs) * sizeof(*scb->hscb),
207ccadc2cbSfvdl /*len*/sizeof(*scb->hscb), op);
208ccadc2cbSfvdl }
209ccadc2cbSfvdl
210fbae48b9Sperry static __inline void
ahc_sync_sglist(struct ahc_softc * ahc,struct scb * scb,int op)211ccadc2cbSfvdl ahc_sync_sglist(struct ahc_softc *ahc, struct scb *scb, int op)
212ccadc2cbSfvdl {
213ccadc2cbSfvdl if (scb->sg_count == 0)
214ccadc2cbSfvdl return;
215ccadc2cbSfvdl
216ccadc2cbSfvdl ahc_dmamap_sync(ahc, ahc->parent_dmat, scb->sg_map->sg_dmamap,
217ccadc2cbSfvdl /*offset*/(scb->sg_list - scb->sg_map->sg_vaddr)
218ccadc2cbSfvdl * sizeof(struct ahc_dma_seg),
219ccadc2cbSfvdl /*len*/sizeof(struct ahc_dma_seg) * scb->sg_count, op);
220ccadc2cbSfvdl }
221ccadc2cbSfvdl
222fbae48b9Sperry static __inline uint32_t
ahc_targetcmd_offset(struct ahc_softc * ahc,u_int index)223ccadc2cbSfvdl ahc_targetcmd_offset(struct ahc_softc *ahc, u_int index)
224ccadc2cbSfvdl {
225ccadc2cbSfvdl return (((uint8_t *)&ahc->targetcmds[index]) - ahc->qoutfifo);
226ccadc2cbSfvdl }
227ccadc2cbSfvdl
228ccadc2cbSfvdl /******************************** Debugging ***********************************/
229*30296cb2Schristos static __inline const char *ahc_name(struct ahc_softc *ahc);
230ccadc2cbSfvdl
231*30296cb2Schristos static __inline const char *
ahc_name(struct ahc_softc * ahc)232ccadc2cbSfvdl ahc_name(struct ahc_softc *ahc)
233ccadc2cbSfvdl {
234ccadc2cbSfvdl return (ahc->name);
235ccadc2cbSfvdl }
236ccadc2cbSfvdl
237c5670263Swiz /*********************** Miscellaneous Support Functions ***********************/
238ccadc2cbSfvdl
239fbae48b9Sperry static __inline void ahc_update_residual(struct ahc_softc *ahc,
240ccadc2cbSfvdl struct scb *scb);
241fbae48b9Sperry static __inline struct ahc_initiator_tinfo *
242ccadc2cbSfvdl ahc_fetch_transinfo(struct ahc_softc *ahc,
243ccadc2cbSfvdl char channel, u_int our_id,
244ccadc2cbSfvdl u_int remote_id,
245ccadc2cbSfvdl struct ahc_tmode_tstate **tstate);
246fbae48b9Sperry static __inline uint16_t
247ccadc2cbSfvdl ahc_inw(struct ahc_softc *ahc, u_int port);
248fbae48b9Sperry static __inline void ahc_outw(struct ahc_softc *ahc, u_int port,
249ccadc2cbSfvdl u_int value);
250fbae48b9Sperry static __inline uint32_t
251ccadc2cbSfvdl ahc_inl(struct ahc_softc *ahc, u_int port);
252fbae48b9Sperry static __inline void ahc_outl(struct ahc_softc *ahc, u_int port,
253ccadc2cbSfvdl uint32_t value);
254fbae48b9Sperry static __inline uint64_t
255ccadc2cbSfvdl ahc_inq(struct ahc_softc *ahc, u_int port);
256fbae48b9Sperry static __inline void ahc_outq(struct ahc_softc *ahc, u_int port,
257ccadc2cbSfvdl uint64_t value);
258fbae48b9Sperry static __inline struct scb*
259ccadc2cbSfvdl ahc_get_scb(struct ahc_softc *ahc);
260fbae48b9Sperry static __inline void ahc_free_scb(struct ahc_softc *ahc, struct scb *scb);
261fbae48b9Sperry static __inline void ahc_swap_with_next_hscb(struct ahc_softc *ahc,
262ccadc2cbSfvdl struct scb *scb);
263fbae48b9Sperry static __inline void ahc_queue_scb(struct ahc_softc *ahc, struct scb *scb);
264fbae48b9Sperry static __inline struct scsi_sense_data *
265ccadc2cbSfvdl ahc_get_sense_buf(struct ahc_softc *ahc,
266ccadc2cbSfvdl struct scb *scb);
267fbae48b9Sperry static __inline uint32_t
268ccadc2cbSfvdl ahc_get_sense_bufaddr(struct ahc_softc *ahc,
269ccadc2cbSfvdl struct scb *scb);
270ccadc2cbSfvdl
271ccadc2cbSfvdl /*
272ccadc2cbSfvdl * Determine whether the sequencer reported a residual
273ccadc2cbSfvdl * for this SCB/transaction.
274ccadc2cbSfvdl */
275fbae48b9Sperry static __inline void
ahc_update_residual(struct ahc_softc * ahc,struct scb * scb)276ccadc2cbSfvdl ahc_update_residual(struct ahc_softc *ahc, struct scb *scb)
277ccadc2cbSfvdl {
278ccadc2cbSfvdl uint32_t sgptr;
279ccadc2cbSfvdl
280ccadc2cbSfvdl sgptr = ahc_le32toh(scb->hscb->sgptr);
281ccadc2cbSfvdl if ((sgptr & SG_RESID_VALID) != 0)
282ccadc2cbSfvdl ahc_calc_residual(ahc, scb);
283ccadc2cbSfvdl }
284ccadc2cbSfvdl
285ccadc2cbSfvdl /*
286ccadc2cbSfvdl * Return pointers to the transfer negotiation information
287ccadc2cbSfvdl * for the specified our_id/remote_id pair.
288ccadc2cbSfvdl */
289fbae48b9Sperry static __inline struct ahc_initiator_tinfo *
ahc_fetch_transinfo(struct ahc_softc * ahc,char channel,u_int our_id,u_int remote_id,struct ahc_tmode_tstate ** tstate)290168cd830Schristos ahc_fetch_transinfo(struct ahc_softc *ahc, char channel, u_int our_id,
291ccadc2cbSfvdl u_int remote_id, struct ahc_tmode_tstate **tstate)
292ccadc2cbSfvdl {
293ccadc2cbSfvdl /*
294ccadc2cbSfvdl * Transfer data structures are stored from the perspective
295ccadc2cbSfvdl * of the target role. Since the parameters for a connection
296ccadc2cbSfvdl * in the initiator role to a given target are the same as
297ccadc2cbSfvdl * when the roles are reversed, we pretend we are the target.
298ccadc2cbSfvdl */
2994d595fd7Schristos #ifdef notdef
3004d595fd7Schristos if (channel == 'B')
3014d595fd7Schristos our_id += 8;
3024d595fd7Schristos #endif
303ccadc2cbSfvdl *tstate = ahc->enabled_targets[our_id];
304ccadc2cbSfvdl return (&(*tstate)->transinfo[remote_id]);
305ccadc2cbSfvdl }
306ccadc2cbSfvdl
307fbae48b9Sperry static __inline uint16_t
ahc_inw(struct ahc_softc * ahc,u_int port)308ccadc2cbSfvdl ahc_inw(struct ahc_softc *ahc, u_int port)
309ccadc2cbSfvdl {
310ccadc2cbSfvdl return ((ahc_inb(ahc, port+1) << 8) | ahc_inb(ahc, port));
311ccadc2cbSfvdl }
312ccadc2cbSfvdl
313fbae48b9Sperry static __inline void
ahc_outw(struct ahc_softc * ahc,u_int port,u_int value)314ccadc2cbSfvdl ahc_outw(struct ahc_softc *ahc, u_int port, u_int value)
315ccadc2cbSfvdl {
316ccadc2cbSfvdl ahc_outb(ahc, port, value & 0xFF);
317ccadc2cbSfvdl ahc_outb(ahc, port+1, (value >> 8) & 0xFF);
318ccadc2cbSfvdl }
319ccadc2cbSfvdl
320fbae48b9Sperry static __inline uint32_t
ahc_inl(struct ahc_softc * ahc,u_int port)321ccadc2cbSfvdl ahc_inl(struct ahc_softc *ahc, u_int port)
322ccadc2cbSfvdl {
323ccadc2cbSfvdl return ((ahc_inb(ahc, port))
324ccadc2cbSfvdl | (ahc_inb(ahc, port+1) << 8)
325ccadc2cbSfvdl | (ahc_inb(ahc, port+2) << 16)
326ccadc2cbSfvdl | (ahc_inb(ahc, port+3) << 24));
327ccadc2cbSfvdl }
328ccadc2cbSfvdl
329fbae48b9Sperry static __inline void
ahc_outl(struct ahc_softc * ahc,u_int port,uint32_t value)330ccadc2cbSfvdl ahc_outl(struct ahc_softc *ahc, u_int port, uint32_t value)
331ccadc2cbSfvdl {
332ccadc2cbSfvdl ahc_outb(ahc, port, (value) & 0xFF);
333ccadc2cbSfvdl ahc_outb(ahc, port+1, ((value) >> 8) & 0xFF);
334ccadc2cbSfvdl ahc_outb(ahc, port+2, ((value) >> 16) & 0xFF);
335ccadc2cbSfvdl ahc_outb(ahc, port+3, ((value) >> 24) & 0xFF);
336ccadc2cbSfvdl }
337ccadc2cbSfvdl
338fbae48b9Sperry static __inline uint64_t
ahc_inq(struct ahc_softc * ahc,u_int port)339ccadc2cbSfvdl ahc_inq(struct ahc_softc *ahc, u_int port)
340ccadc2cbSfvdl {
341ccadc2cbSfvdl return ((ahc_inb(ahc, port))
342ccadc2cbSfvdl | (ahc_inb(ahc, port+1) << 8)
343ccadc2cbSfvdl | (ahc_inb(ahc, port+2) << 16)
344ccadc2cbSfvdl | (ahc_inb(ahc, port+3) << 24)
345ccadc2cbSfvdl | (((uint64_t)ahc_inb(ahc, port+4)) << 32)
346ccadc2cbSfvdl | (((uint64_t)ahc_inb(ahc, port+5)) << 40)
347ccadc2cbSfvdl | (((uint64_t)ahc_inb(ahc, port+6)) << 48)
348ccadc2cbSfvdl | (((uint64_t)ahc_inb(ahc, port+7)) << 56));
349ccadc2cbSfvdl }
350ccadc2cbSfvdl
351fbae48b9Sperry static __inline void
ahc_outq(struct ahc_softc * ahc,u_int port,uint64_t value)352ccadc2cbSfvdl ahc_outq(struct ahc_softc *ahc, u_int port, uint64_t value)
353ccadc2cbSfvdl {
354ccadc2cbSfvdl ahc_outb(ahc, port, value & 0xFF);
355ccadc2cbSfvdl ahc_outb(ahc, port+1, (value >> 8) & 0xFF);
356ccadc2cbSfvdl ahc_outb(ahc, port+2, (value >> 16) & 0xFF);
357ccadc2cbSfvdl ahc_outb(ahc, port+3, (value >> 24) & 0xFF);
358ccadc2cbSfvdl ahc_outb(ahc, port+4, (value >> 32) & 0xFF);
359ccadc2cbSfvdl ahc_outb(ahc, port+5, (value >> 40) & 0xFF);
360ccadc2cbSfvdl ahc_outb(ahc, port+6, (value >> 48) & 0xFF);
361ccadc2cbSfvdl ahc_outb(ahc, port+7, (value >> 56) & 0xFF);
362ccadc2cbSfvdl }
363ccadc2cbSfvdl
364ccadc2cbSfvdl /*
365ccadc2cbSfvdl * Get a free scb. If there are none, see if we can allocate a new SCB.
366ccadc2cbSfvdl */
367fbae48b9Sperry static __inline struct scb *
ahc_get_scb(struct ahc_softc * ahc)368ccadc2cbSfvdl ahc_get_scb(struct ahc_softc *ahc)
369ccadc2cbSfvdl {
370ccadc2cbSfvdl struct scb *scb;
371ccadc2cbSfvdl
3722ac65956Sbouyer if ((scb = SLIST_FIRST(&ahc->scb_data->free_scbs)) == NULL)
373ccadc2cbSfvdl return (NULL);
374ccadc2cbSfvdl SLIST_REMOVE_HEAD(&ahc->scb_data->free_scbs, links.sle);
375ccadc2cbSfvdl return (scb);
376ccadc2cbSfvdl }
377ccadc2cbSfvdl
378ccadc2cbSfvdl /*
379ccadc2cbSfvdl * Return an SCB resource to the free list.
380ccadc2cbSfvdl */
381fbae48b9Sperry static __inline void
ahc_free_scb(struct ahc_softc * ahc,struct scb * scb)382ccadc2cbSfvdl ahc_free_scb(struct ahc_softc *ahc, struct scb *scb)
383ccadc2cbSfvdl {
384ccadc2cbSfvdl struct hardware_scb *hscb;
385ccadc2cbSfvdl
386ccadc2cbSfvdl hscb = scb->hscb;
387ccadc2cbSfvdl /* Clean up for the next user */
388ccadc2cbSfvdl ahc->scb_data->scbindex[hscb->tag] = NULL;
389ccadc2cbSfvdl scb->flags = SCB_FREE;
390ccadc2cbSfvdl hscb->control = 0;
391ccadc2cbSfvdl
392ccadc2cbSfvdl SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, scb, links.sle);
393ccadc2cbSfvdl
394ccadc2cbSfvdl /* Notify the OSM that a resource is now available. */
395ccadc2cbSfvdl ahc_platform_scb_free(ahc, scb);
396ccadc2cbSfvdl }
397ccadc2cbSfvdl
398fbae48b9Sperry static __inline struct scb *
ahc_lookup_scb(struct ahc_softc * ahc,u_int tag)399ccadc2cbSfvdl ahc_lookup_scb(struct ahc_softc *ahc, u_int tag)
400ccadc2cbSfvdl {
401ccadc2cbSfvdl struct scb* scb;
402ccadc2cbSfvdl
403ccadc2cbSfvdl scb = ahc->scb_data->scbindex[tag];
404ccadc2cbSfvdl if (scb != NULL)
405ccadc2cbSfvdl ahc_sync_scb(ahc, scb,
406ccadc2cbSfvdl BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
407ccadc2cbSfvdl return (scb);
408ccadc2cbSfvdl }
409ccadc2cbSfvdl
410fbae48b9Sperry static __inline void
ahc_swap_with_next_hscb(struct ahc_softc * ahc,struct scb * scb)411ccadc2cbSfvdl ahc_swap_with_next_hscb(struct ahc_softc *ahc, struct scb *scb)
412ccadc2cbSfvdl {
413ccadc2cbSfvdl struct hardware_scb *q_hscb;
414ccadc2cbSfvdl u_int saved_tag;
415ccadc2cbSfvdl
416ccadc2cbSfvdl /*
417ccadc2cbSfvdl * Our queuing method is a bit tricky. The card
418ccadc2cbSfvdl * knows in advance which HSCB to download, and we
419ccadc2cbSfvdl * can't disappoint it. To achieve this, the next
420ccadc2cbSfvdl * SCB to download is saved off in ahc->next_queued_scb.
421ccadc2cbSfvdl * When we are called to queue "an arbitrary scb",
422ccadc2cbSfvdl * we copy the contents of the incoming HSCB to the one
423ccadc2cbSfvdl * the sequencer knows about, swap HSCB pointers and
424ccadc2cbSfvdl * finally assign the SCB to the tag indexed location
425ccadc2cbSfvdl * in the scb_array. This makes sure that we can still
426ccadc2cbSfvdl * locate the correct SCB by SCB_TAG.
427ccadc2cbSfvdl */
428ccadc2cbSfvdl q_hscb = ahc->next_queued_scb->hscb;
429ccadc2cbSfvdl saved_tag = q_hscb->tag;
430ccadc2cbSfvdl memcpy(q_hscb, scb->hscb, sizeof(*scb->hscb));
431ccadc2cbSfvdl if ((scb->flags & SCB_CDB32_PTR) != 0) {
432ccadc2cbSfvdl q_hscb->shared_data.cdb_ptr =
433ccadc2cbSfvdl ahc_htole32(ahc_hscb_busaddr(ahc, q_hscb->tag)
434ccadc2cbSfvdl + offsetof(struct hardware_scb, cdb32));
435ccadc2cbSfvdl }
436ccadc2cbSfvdl q_hscb->tag = saved_tag;
437ccadc2cbSfvdl q_hscb->next = scb->hscb->tag;
438ccadc2cbSfvdl
439ccadc2cbSfvdl /* Now swap HSCB pointers. */
440ccadc2cbSfvdl ahc->next_queued_scb->hscb = scb->hscb;
441ccadc2cbSfvdl scb->hscb = q_hscb;
442ccadc2cbSfvdl
443ccadc2cbSfvdl /* Now define the mapping from tag to SCB in the scbindex */
444ccadc2cbSfvdl ahc->scb_data->scbindex[scb->hscb->tag] = scb;
445ccadc2cbSfvdl }
446ccadc2cbSfvdl
447ccadc2cbSfvdl /*
448ccadc2cbSfvdl * Tell the sequencer about a new transaction to execute.
449ccadc2cbSfvdl */
450fbae48b9Sperry static __inline void
ahc_queue_scb(struct ahc_softc * ahc,struct scb * scb)451ccadc2cbSfvdl ahc_queue_scb(struct ahc_softc *ahc, struct scb *scb)
452ccadc2cbSfvdl {
453ccadc2cbSfvdl ahc_swap_with_next_hscb(ahc, scb);
454ccadc2cbSfvdl
455ccadc2cbSfvdl if (scb->hscb->tag == SCB_LIST_NULL
456ccadc2cbSfvdl || scb->hscb->next == SCB_LIST_NULL)
457ccadc2cbSfvdl panic("Attempt to queue invalid SCB tag %x:%x\n",
458ccadc2cbSfvdl scb->hscb->tag, scb->hscb->next);
459ccadc2cbSfvdl /*
460ccadc2cbSfvdl * Keep a history of SCBs we've downloaded in the qinfifo.
461ccadc2cbSfvdl */
462ccadc2cbSfvdl ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag;
463ccadc2cbSfvdl
464ccadc2cbSfvdl /*
465c5670263Swiz * Make sure our data is consistent from the
466ccadc2cbSfvdl * perspective of the adapter.
467ccadc2cbSfvdl */
468ccadc2cbSfvdl ahc_sync_scb(ahc, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
469ccadc2cbSfvdl
470ccadc2cbSfvdl /* Tell the adapter about the newly queued SCB */
471ccadc2cbSfvdl if ((ahc->features & AHC_QUEUE_REGS) != 0) {
472ccadc2cbSfvdl ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
473ccadc2cbSfvdl } else {
474ccadc2cbSfvdl if ((ahc->features & AHC_AUTOPAUSE) == 0)
475ccadc2cbSfvdl ahc_pause(ahc);
476ccadc2cbSfvdl ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
477ccadc2cbSfvdl if ((ahc->features & AHC_AUTOPAUSE) == 0)
478ccadc2cbSfvdl ahc_unpause(ahc);
479ccadc2cbSfvdl }
480ccadc2cbSfvdl }
481ccadc2cbSfvdl
482fbae48b9Sperry static __inline struct scsi_sense_data *
ahc_get_sense_buf(struct ahc_softc * ahc,struct scb * scb)483ccadc2cbSfvdl ahc_get_sense_buf(struct ahc_softc *ahc, struct scb *scb)
484ccadc2cbSfvdl {
485ccadc2cbSfvdl int offset;
486ccadc2cbSfvdl
487ccadc2cbSfvdl offset = scb - ahc->scb_data->scbarray;
488ccadc2cbSfvdl return (&ahc->scb_data->sense[offset]);
489ccadc2cbSfvdl }
490ccadc2cbSfvdl
491fbae48b9Sperry static __inline uint32_t
ahc_get_sense_bufaddr(struct ahc_softc * ahc,struct scb * scb)492ccadc2cbSfvdl ahc_get_sense_bufaddr(struct ahc_softc *ahc, struct scb *scb)
493ccadc2cbSfvdl {
494ccadc2cbSfvdl int offset;
495ccadc2cbSfvdl
496ccadc2cbSfvdl offset = scb - ahc->scb_data->scbarray;
497ccadc2cbSfvdl return (ahc->scb_data->sense_busaddr
498df9803ceSthorpej + (offset * sizeof(struct scsi_sense_data)));
499ccadc2cbSfvdl }
500ccadc2cbSfvdl
501ccadc2cbSfvdl /************************** Interrupt Processing ******************************/
502fbae48b9Sperry static __inline void ahc_sync_qoutfifo(struct ahc_softc *ahc, int op);
503fbae48b9Sperry static __inline void ahc_sync_tqinfifo(struct ahc_softc *ahc, int op);
504fbae48b9Sperry static __inline u_int ahc_check_cmdcmpltqueues(struct ahc_softc *ahc);
505fbae48b9Sperry static __inline int ahc_intr(void *arg);
506fbae48b9Sperry static __inline void ahc_minphys(struct buf *bp);
507ccadc2cbSfvdl
508fbae48b9Sperry static __inline void
ahc_minphys(struct buf * bp)5094b83748cScegger ahc_minphys(struct buf *bp)
510ccadc2cbSfvdl {
511ccadc2cbSfvdl /*
512ccadc2cbSfvdl * Even though the card can transfer up to 16megs per command
5131ffa7b76Swiz * we are limited by the number of segments in the DMA segment
514ccadc2cbSfvdl * list that we can hold. The worst case is that all pages are
515c5670263Swiz * discontinuous physically, hence the "page per segment" limit
516ccadc2cbSfvdl * enforced here.
517ccadc2cbSfvdl */
518ccadc2cbSfvdl if (bp->b_bcount > AHC_MAXTRANSFER_SIZE) {
519ccadc2cbSfvdl bp->b_bcount = AHC_MAXTRANSFER_SIZE;
520ccadc2cbSfvdl }
521ccadc2cbSfvdl minphys(bp);
522ccadc2cbSfvdl }
523ccadc2cbSfvdl
524fbae48b9Sperry static __inline void
ahc_sync_qoutfifo(struct ahc_softc * ahc,int op)525ccadc2cbSfvdl ahc_sync_qoutfifo(struct ahc_softc *ahc, int op)
526ccadc2cbSfvdl {
527ccadc2cbSfvdl ahc_dmamap_sync(ahc, ahc->parent_dmat, ahc->shared_data_dmamap,
528ccadc2cbSfvdl /*offset*/0, /*len*/256, op);
529ccadc2cbSfvdl }
530ccadc2cbSfvdl
531fbae48b9Sperry static __inline void
ahc_sync_tqinfifo(struct ahc_softc * ahc,int op)532168cd830Schristos ahc_sync_tqinfifo(struct ahc_softc *ahc, int op)
533ccadc2cbSfvdl {
534ccadc2cbSfvdl #ifdef AHC_TARGET_MODE
535ccadc2cbSfvdl if ((ahc->flags & AHC_TARGETROLE) != 0) {
536ccadc2cbSfvdl ahc_dmamap_sync(ahc, ahc->parent_dmat /*shared_data_dmat*/,
537ccadc2cbSfvdl ahc->shared_data_dmamap,
538ccadc2cbSfvdl ahc_targetcmd_offset(ahc, 0),
539ccadc2cbSfvdl sizeof(struct target_cmd) * AHC_TMODE_CMDS,
540ccadc2cbSfvdl op);
541ccadc2cbSfvdl }
542ccadc2cbSfvdl #endif
543ccadc2cbSfvdl }
544ccadc2cbSfvdl
545ccadc2cbSfvdl /*
546ccadc2cbSfvdl * See if the firmware has posted any completed commands
547ccadc2cbSfvdl * into our in-core command complete fifos.
548ccadc2cbSfvdl */
549ccadc2cbSfvdl #define AHC_RUN_QOUTFIFO 0x1
550ccadc2cbSfvdl #define AHC_RUN_TQINFIFO 0x2
551fbae48b9Sperry static __inline u_int
ahc_check_cmdcmpltqueues(struct ahc_softc * ahc)552ccadc2cbSfvdl ahc_check_cmdcmpltqueues(struct ahc_softc *ahc)
553ccadc2cbSfvdl {
554ccadc2cbSfvdl u_int retval;
555ccadc2cbSfvdl
556ccadc2cbSfvdl retval = 0;
557ccadc2cbSfvdl ahc_dmamap_sync(ahc, ahc->parent_dmat /*shared_data_dmat*/, ahc->shared_data_dmamap,
558ccadc2cbSfvdl /*offset*/ahc->qoutfifonext, /*len*/1,
559ccadc2cbSfvdl BUS_DMASYNC_POSTREAD);
560ccadc2cbSfvdl if (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL)
561ccadc2cbSfvdl retval |= AHC_RUN_QOUTFIFO;
562ccadc2cbSfvdl #ifdef AHC_TARGET_MODE
563ccadc2cbSfvdl if ((ahc->flags & AHC_TARGETROLE) != 0
564ccadc2cbSfvdl && (ahc->flags & AHC_TQINFIFO_BLOCKED) == 0) {
565ccadc2cbSfvdl ahc_dmamap_sync(ahc, ahc->parent_dmat /*shared_data_dmat*/,
566ccadc2cbSfvdl ahc->shared_data_dmamap,
567ccadc2cbSfvdl ahc_targetcmd_offset(ahc, ahc->tqinfifonext),
568ccadc2cbSfvdl /*len*/sizeof(struct target_cmd),
569ccadc2cbSfvdl BUS_DMASYNC_POSTREAD);
570ccadc2cbSfvdl if (ahc->targetcmds[ahc->tqinfifonext].cmd_valid != 0)
571ccadc2cbSfvdl retval |= AHC_RUN_TQINFIFO;
572ccadc2cbSfvdl }
573ccadc2cbSfvdl #endif
574ccadc2cbSfvdl return (retval);
575ccadc2cbSfvdl }
576ccadc2cbSfvdl
577ccadc2cbSfvdl /*
578ccadc2cbSfvdl * Catch an interrupt from the adapter
579ccadc2cbSfvdl */
580fbae48b9Sperry static __inline int
ahc_intr(void * arg)581ccadc2cbSfvdl ahc_intr(void *arg)
582ccadc2cbSfvdl {
583ccadc2cbSfvdl struct ahc_softc *ahc = (struct ahc_softc*)arg;
584ccadc2cbSfvdl u_int intstat;
585ccadc2cbSfvdl
586ccadc2cbSfvdl if ((ahc->pause & INTEN) == 0) {
587ccadc2cbSfvdl /*
588ccadc2cbSfvdl * Our interrupt is not enabled on the chip
589ccadc2cbSfvdl * and may be disabled for re-entrancy reasons,
590ccadc2cbSfvdl * so just return. This is likely just a shared
591ccadc2cbSfvdl * interrupt.
592ccadc2cbSfvdl */
593ccadc2cbSfvdl return 1;
594ccadc2cbSfvdl }
595ccadc2cbSfvdl /*
596ccadc2cbSfvdl * Instead of directly reading the interrupt status register,
597ccadc2cbSfvdl * infer the cause of the interrupt by checking our in-core
598ccadc2cbSfvdl * completion queues. This avoids a costly PCI bus read in
599ccadc2cbSfvdl * most cases.
600ccadc2cbSfvdl */
601ccadc2cbSfvdl if ((ahc->flags & (AHC_ALL_INTERRUPTS|AHC_EDGE_INTERRUPT)) == 0
602ccadc2cbSfvdl && (ahc_check_cmdcmpltqueues(ahc) != 0))
603ccadc2cbSfvdl intstat = CMDCMPLT;
604ccadc2cbSfvdl else {
605ccadc2cbSfvdl intstat = ahc_inb(ahc, INTSTAT);
606ccadc2cbSfvdl }
607ccadc2cbSfvdl
608ccadc2cbSfvdl if (intstat & CMDCMPLT) {
609ccadc2cbSfvdl ahc_outb(ahc, CLRINT, CLRCMDINT);
610ccadc2cbSfvdl /*
611ccadc2cbSfvdl * Ensure that the chip sees that we've cleared
612ccadc2cbSfvdl * this interrupt before we walk the output fifo.
613ccadc2cbSfvdl * Otherwise, we may, due to posted bus writes,
614ccadc2cbSfvdl * clear the interrupt after we finish the scan,
615ccadc2cbSfvdl * and after the sequencer has added new entries
616ccadc2cbSfvdl * and asserted the interrupt again.
617ccadc2cbSfvdl */
618ccadc2cbSfvdl ahc_flush_device_writes(ahc);
619ccadc2cbSfvdl scsipi_channel_freeze(ahc->channel == 'A' ? &ahc->sc_channel : &ahc->sc_channel_b, 1);
620ccadc2cbSfvdl ahc_run_qoutfifo(ahc);
621ccadc2cbSfvdl scsipi_channel_thaw(ahc->channel == 'A' ? &ahc->sc_channel : &ahc->sc_channel_b, 1);
622ccadc2cbSfvdl #ifdef AHC_TARGET_MODE
623ccadc2cbSfvdl if ((ahc->flags & AHC_TARGETROLE) != 0)
624ccadc2cbSfvdl ahc_run_tqinfifo(ahc, /*paused*/FALSE);
625ccadc2cbSfvdl #endif
626ccadc2cbSfvdl }
627ccadc2cbSfvdl
628ccadc2cbSfvdl if (intstat == 0xFF && (ahc->features & AHC_REMOVABLE) != 0)
629ccadc2cbSfvdl /* Hot eject */
630ccadc2cbSfvdl return 1;
631ccadc2cbSfvdl
632ccadc2cbSfvdl if ((intstat & INT_PEND) == 0) {
633ccadc2cbSfvdl #if AHC_PCI_CONFIG > 0
634ccadc2cbSfvdl if (ahc->unsolicited_ints > 500) {
635ccadc2cbSfvdl ahc->unsolicited_ints = 0;
636ccadc2cbSfvdl if ((ahc->chip & AHC_PCI) != 0
637ccadc2cbSfvdl && (ahc_inb(ahc, ERROR) & PCIERRSTAT) != 0)
638ccadc2cbSfvdl ahc->bus_intr(ahc);
639ccadc2cbSfvdl }
640ccadc2cbSfvdl #endif
641ccadc2cbSfvdl ahc->unsolicited_ints++;
642ccadc2cbSfvdl return 1;
643ccadc2cbSfvdl }
644ccadc2cbSfvdl ahc->unsolicited_ints = 0;
645ccadc2cbSfvdl
646ccadc2cbSfvdl if (intstat & BRKADRINT) {
647ccadc2cbSfvdl ahc_handle_brkadrint(ahc);
648ccadc2cbSfvdl /* Fatal error, no more interrupts to handle. */
649ccadc2cbSfvdl return 1;
650ccadc2cbSfvdl }
651ccadc2cbSfvdl
652ccadc2cbSfvdl if ((intstat & (SEQINT|SCSIINT)) != 0)
653ccadc2cbSfvdl ahc_pause_bug_fix(ahc);
654ccadc2cbSfvdl
655ccadc2cbSfvdl if ((intstat & SEQINT) != 0)
656ccadc2cbSfvdl ahc_handle_seqint(ahc, intstat);
657ccadc2cbSfvdl
658ccadc2cbSfvdl if ((intstat & SCSIINT) != 0)
659ccadc2cbSfvdl ahc_handle_scsiint(ahc, intstat);
660ccadc2cbSfvdl
661ccadc2cbSfvdl return 1;
662ccadc2cbSfvdl }
663ccadc2cbSfvdl
664ccadc2cbSfvdl #endif /* _AIC7XXX_INLINE_H_ */
665