1 /* $NetBSD: anreg.h,v 1.8 2001/06/29 11:24:42 onoe Exp $ */ 2 /* 3 * Copyright (c) 1997, 1998, 1999 4 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: src/sys/dev/an/if_anreg.h,v 1.3 2000/11/13 23:04:12 wpaul Exp $ 34 */ 35 36 #ifndef _DEV_IC_ANREG_H 37 #define _DEV_IC_ANREG_H 38 39 /* 40 * Size of Aironet I/O space. 41 */ 42 #define AN_IOSIZ 0x40 43 44 /* 45 * Hermes register definitions and what little I know about them. 46 */ 47 48 /* Hermes command/status registers. */ 49 #define AN_COMMAND 0x00 50 #define AN_PARAM0 0x02 51 #define AN_PARAM1 0x04 52 #define AN_PARAM2 0x06 53 #define AN_STATUS 0x08 54 #define AN_RESP0 0x0A 55 #define AN_RESP1 0x0C 56 #define AN_RESP2 0x0E 57 #define AN_LINKSTAT 0x10 58 59 /* Command register */ 60 #define AN_CMD_BUSY 0x8000 /* busy bit */ 61 #define AN_CMD_NO_ACK 0x0080 /* don't acknowledge command */ 62 #define AN_CMD_CODE_MASK 0x003F 63 #define AN_CMD_QUAL_MASK 0x7F00 64 65 /* Command codes */ 66 #define AN_CMD_NOOP 0x0000 /* no-op */ 67 #define AN_CMD_ENABLE 0x0001 /* enable */ 68 #define AN_CMD_DISABLE 0x0002 /* disable */ 69 #define AN_CMD_FORCE_SYNCLOSS 0x0003 /* force loss of sync */ 70 #define AN_CMD_FW_RESTART 0x0004 /* firmware resrart */ 71 #define AN_CMD_HOST_SLEEP 0x0005 72 #define AN_CMD_MAGIC_PKT 0x0006 73 #define AN_CMD_READCFG 0x0008 74 #define AN_CMD_SET_MODE 0x0009 75 #define AN_CMD_ALLOC_MEM 0x000A /* allocate NIC memory */ 76 #define AN_CMD_TX 0x000B /* transmit */ 77 #define AN_CMD_DEALLOC_MEM 0x000C 78 #define AN_CMD_NOOP2 0x0010 79 #define AN_CMD_ACCESS 0x0021 80 #define AN_CMD_ALLOC_BUF 0x0028 81 #define AN_CMD_PSP_NODES 0x0030 82 #define AN_CMD_SET_PHYREG 0x003E 83 #define AN_CMD_TX_TEST 0x003F 84 #define AN_CMD_SLEEP 0x0085 85 #define AN_CMD_SAVECFG 0x0108 86 87 /* 88 * Reclaim qualifier bit, applicable to the 89 * TX command. 90 */ 91 #define AN_RECLAIM 0x0100 /* reclaim NIC memory */ 92 93 /* 94 * ACCESS command qualifier bits. 95 */ 96 #define AN_ACCESS_READ 0x0000 97 #define AN_ACCESS_WRITE 0x0100 98 99 /* 100 * PROGRAM command qualifier bits. 101 */ 102 #define AN_PROGRAM_DISABLE 0x0000 103 #define AN_PROGRAM_ENABLE_RAM 0x0100 104 #define AN_PROGRAM_ENABLE_NVRAM 0x0200 105 #define AN_PROGRAM_NVRAM 0x0300 106 107 /* Status register values */ 108 #define AN_STAT_CMD_CODE 0x003F 109 #define AN_STAT_CMD_RESULT 0x7F00 110 111 /* Linkstat register */ 112 #define AN_LINKSTAT_ASSOCIATED 0x0400 113 #define AN_LINKSTAT_AUTHFAIL 0x0300 114 #define AN_LINKSTAT_ASSOC_FAIL 0x8400 115 #define AN_LINKSTAT_DISASSOC 0x8200 116 #define AN_LINKSTAT_DEAUTH 0x8100 117 #define AN_LINKSTAT_SYNCLOST_TSF 0x8004 118 #define AN_LINKSTAT_SYNCLOST_HOSTREQ 0x8003 119 #define AN_LINKSTAT_SYNCLOST_AVGRETRY 0x8002 120 #define AN_LINKSTAT_SYNCLOST_MAXRETRY 0x8001 121 #define AN_LINKSTAT_SYNCLOST_MISSBEACON 0x8000 122 123 /* memory handle management registers */ 124 #define AN_RX_FID 0x20 125 #define AN_ALLOC_FID 0x22 126 #define AN_TX_CMP_FID 0x24 127 128 /* 129 * Buffer Access Path (BAP) registers. 130 * These are I/O channels. I believe you can use each one for 131 * any desired purpose independently of the other. In general 132 * though, we use BAP1 for reading and writing LTV records and 133 * reading received data frames, and BAP0 for writing transmit 134 * frames. This is a convention though, not a rule. 135 */ 136 #define AN_SEL0 0x18 137 #define AN_SEL1 0x1A 138 #define AN_OFF0 0x1C 139 #define AN_OFF1 0x1E 140 #define AN_DATA0 0x36 141 #define AN_DATA1 0x38 142 #define AN_BAP0 AN_DATA0 143 #define AN_BAP1 AN_DATA1 144 145 #define AN_OFF_BUSY 0x8000 146 #define AN_OFF_ERR 0x4000 147 #define AN_OFF_DONE 0x2000 148 #define AN_OFF_DATAOFF 0x0FFF 149 150 /* Event registers */ 151 #define AN_EVENT_STAT 0x30 /* Event status */ 152 #define AN_INT_EN 0x32 /* Interrupt enable/disable */ 153 #define AN_EVENT_ACK 0x34 /* Ack event */ 154 155 /* Events */ 156 #define AN_EV_CLR_STUCK_BUSY 0x4000 /* clear stuck busy bit */ 157 #define AN_EV_WAKEREQUEST 0x2000 /* awaken from PSP mode */ 158 #define AN_EV_AWAKE 0x0100 /* station woke up from PSP mode*/ 159 #define AN_EV_LINKSTAT 0x0080 /* link status available */ 160 #define AN_EV_CMD 0x0010 /* command completed */ 161 #define AN_EV_ALLOC 0x0008 /* async alloc/reclaim completed */ 162 #define AN_EV_TX_EXC 0x0004 /* async xmit completed with failure */ 163 #define AN_EV_TX 0x0002 /* async xmit completed succesfully */ 164 #define AN_EV_RX 0x0001 /* async rx completed */ 165 166 /* Host software registers */ 167 #define AN_SW0 0x28 168 #define AN_SW1 0x2A 169 #define AN_SW2 0x2C 170 #define AN_SW3 0x2E 171 172 #define AN_CNTL 0x14 173 174 #define AN_CNTL_AUX_ENA 0xC000 175 #define AN_CNTL_AUX_ENA_STAT 0xC000 176 #define AN_CNTL_AUX_DIS_STAT 0x0000 177 #define AN_CNTL_AUX_ENA_CNTL 0x8000 178 #define AN_CNTL_AUX_DIS_CNTL 0x4000 179 180 #define AN_AUX_PAGE 0x3A 181 #define AN_AUX_OFFSET 0x3C 182 #define AN_AUX_DATA 0x3E 183 184 /* 185 * Length, Type, Value (LTV) record definitions and RID values. 186 */ 187 struct an_ltv_gen { 188 u_int16_t an_len; 189 u_int16_t an_type; 190 u_int16_t an_val; 191 }; 192 193 /* 194 * General configuration information. 195 */ 196 #define AN_RID_GENCONFIG 0xFF10 197 struct an_ltv_genconfig { 198 /* General configuration. */ 199 u_int16_t an_len; /* 0x00 */ 200 u_int16_t an_type; /* XXXX */ 201 u_int16_t an_opmode; /* 0x02 */ 202 u_int16_t an_rxmode; /* 0x04 */ 203 u_int16_t an_fragthresh; /* 0x06 */ 204 u_int16_t an_rtsthresh; /* 0x08 */ 205 u_int8_t an_macaddr[6]; /* 0x0A */ 206 u_int8_t an_rates[8]; /* 0x10 */ 207 u_int16_t an_shortretry_limit; /* 0x18 */ 208 u_int16_t an_longretry_limit; /* 0x1A */ 209 u_int16_t an_tx_msdu_lifetime; /* 0x1C */ 210 u_int16_t an_rx_msdu_lifetime; /* 0x1E */ 211 u_int16_t an_stationary; /* 0x20 */ 212 u_int16_t an_ordering; /* 0x22 */ 213 u_int16_t an_devtype; /* 0x24 */ 214 u_int16_t an_rsvd0[5]; /* 0x26 */ 215 /* Scanning associating. */ 216 u_int16_t an_scanmode; /* 0x30 */ 217 u_int16_t an_probedelay; /* 0x32 */ 218 u_int16_t an_probe_energy_timeout;/* 0x34 */ 219 u_int16_t an_probe_response_timeout;/*0x36 */ 220 u_int16_t an_beacon_listen_timeout;/*0x38 */ 221 u_int16_t an_ibss_join_net_timeout;/*0x3A */ 222 u_int16_t an_auth_timeout; /* 0x3C */ 223 u_int16_t an_authtype; /* 0x3E */ 224 u_int16_t an_assoc_timeout; /* 0x40 */ 225 u_int16_t an_specified_ap_timeout;/* 0x42 */ 226 u_int16_t an_offline_scan_interval;/*0x44 */ 227 u_int16_t an_offline_scan_duration;/*0x46 */ 228 u_int16_t an_link_loss_delay; /* 0x48 */ 229 u_int16_t an_max_beacon_lost_time;/* 0x4A */ 230 u_int16_t an_refresh_interval; /* 0x4C */ 231 u_int16_t an_rsvd1; /* 0x4E */ 232 /* Power save operation */ 233 u_int16_t an_psave_mode; /* 0x50 */ 234 u_int16_t an_sleep_for_dtims; /* 0x52 */ 235 u_int16_t an_listen_interval; /* 0x54 */ 236 u_int16_t an_fast_listen_interval;/* 0x56 */ 237 u_int16_t an_listen_decay; /* 0x58 */ 238 u_int16_t an_fast_listen_decay; /* 0x5A */ 239 u_int16_t an_rsvd2[2]; /* 0x5C */ 240 /* Ad-hoc (or AP) operation. */ 241 u_int16_t an_beacon_period; /* 0x60 */ 242 u_int16_t an_atim_duration; /* 0x62 */ 243 u_int16_t an_rsvd3; /* 0x64 */ 244 u_int16_t an_ds_channel; /* 0x66 */ 245 u_int16_t an_rsvd4; /* 0x68 */ 246 u_int16_t an_dtim_period; /* 0x6A */ 247 u_int16_t an_rsvd5[2]; /* 0x6C */ 248 /* Radio operation. */ 249 u_int16_t an_radiotype; /* 0x70 */ 250 u_int16_t an_diversity; /* 0x72 */ 251 u_int16_t an_tx_power; /* 0x74 */ 252 u_int16_t an_rss_thresh; /* 0x76 */ 253 u_int16_t an_modulation_type; /* 0x78 */ 254 u_int16_t an_short_preamble; /* 0x7A */ 255 u_int16_t an_home_product; /* 0x7C */ 256 u_int16_t an_rsvd6; /* 0x7E */ 257 /* Aironet extensions. */ 258 u_int8_t an_nodename[16]; /* 0x80 */ 259 u_int16_t an_arl_thresh; /* 0x90 */ 260 u_int16_t an_arl_decay; /* 0x92 */ 261 u_int16_t an_arl_delay; /* 0x94 */ 262 u_int8_t an_rsvd7; /* 0x96 */ 263 u_int8_t an_rsvd8; /* 0x97 */ 264 u_int8_t an_magic_packet_action; /* 0x98 */ 265 u_int8_t an_magic_packet_ctl; /* 0x99 */ 266 u_int16_t an_rsvd9; 267 }; 268 269 #define AN_OPMODE_IBSS_ADHOC 0x0000 270 #define AN_OPMODE_INFRASTRUCTURE_STATION 0x0001 271 #define AN_OPMODE_AP 0x0002 272 #define AN_OPMODE_AP_REPEATER 0x0003 273 #define AN_OPMODE_UNMODIFIED_PAYLOAD 0x0100 274 #define AN_OPMODE_AIRONET_EXTENSIONS 0x0200 275 #define AN_OPMODE_AP_EXTENSIONS 0x0400 276 277 #define AN_RXMODE_BC_MC_ADDR 0x0000 278 #define AN_RXMODE_BC_ADDR 0x0001 279 #define AN_RXMODE_ADDR 0x0002 280 #define AN_RXMODE_80211_MONITOR_CURBSS 0x0003 281 #define AN_RXMODE_80211_MONITOR_ANYBSS 0x0004 282 #define AN_RXMODE_LAN_MONITOR_CURBSS 0x0005 283 #define AN_RXMODE_NO_8023_HEADER 0x0100 284 285 #define AN_RATE_1MBPS 0x0002 286 #define AN_RATE_2MBPS 0x0004 287 #define AN_RATE_5_5MBPS 0x000B 288 #define AN_RATE_11MBPS 0x0016 289 290 #define AN_DEVTYPE_PC4500 0x0065 291 #define AN_DEVTYPE_PC4800 0x006D 292 293 #define AN_SCANMODE_ACTIVE 0x0000 294 #define AN_SCANMODE_PASSIVE 0x0001 295 #define AN_SCANMODE_AIRONET_ACTIVE 0x0002 296 297 #define AN_AUTHTYPE_NONE 0x0000 298 #define AN_AUTHTYPE_OPEN 0x0001 299 #define AN_AUTHTYPE_SHAREDKEY 0x0002 300 #define AN_AUTHTYPE_MASK 0x00ff 301 #define AN_AUTHTYPE_PRIVACY_IN_USE 0x0100 302 #define AN_AUTHTYPE_ALLOW_UNENCRYPTED 0x0200 303 #define AN_AUTHTYPE_LEAP 0x1000 304 305 #define AN_PSAVE_NONE 0x0000 306 #define AN_PSAVE_CAM 0x0001 307 #define AN_PSAVE_PSP 0x0002 308 #define AN_PSAVE_PSP_CAM 0x0003 309 310 #define AN_RADIOTYPE_80211_FH 0x0001 311 #define AN_RADIOTYPE_80211_DS 0x0002 312 #define AN_RADIOTYPE_LM2000_DS 0x0004 313 314 #define AN_DIVERSITY_FACTORY_DEFAULT 0x0000 315 #define AN_DIVERSITY_ANTENNA_1_ONLY 0x0001 316 #define AN_DIVERSITY_ANTENNA_2_ONLY 0x0002 317 #define AN_DIVERSITY_ANTENNA_1_AND_2 0x0003 318 319 #define AN_TXPOWER_FACTORY_DEFAULT 0x0000 320 #define AN_TXPOWER_50MW 50 321 #define AN_TXPOWER_100MW 100 322 #define AN_TXPOWER_250MW 250 323 324 /* 325 * Valid SSID list. You can specify up to three SSIDs denoting 326 * the service sets that you want to join. The first SSID always 327 * defaults to "tsunami" which is a handy way to detect the 328 * card. 329 */ 330 #define AN_RID_SSIDLIST 0xFF11 331 struct an_ltv_ssidlist { 332 u_int16_t an_len; 333 u_int16_t an_type; 334 u_int16_t an_ssid1_len; 335 char an_ssid1[32]; 336 u_int16_t an_ssid2_len; 337 char an_ssid2[32]; 338 u_int16_t an_ssid3_len; 339 char an_ssid3[32]; 340 }; 341 342 #define AN_DEF_SSID_LEN 7 343 #define AN_DEF_SSID "tsunami" 344 345 /* 346 * Valid AP list. 347 */ 348 #define AN_RID_APLIST 0xFF12 349 struct an_ltv_aplist { 350 u_int16_t an_len; 351 u_int16_t an_type; 352 u_int8_t an_ap1[8]; 353 u_int8_t an_ap2[8]; 354 u_int8_t an_ap3[8]; 355 u_int8_t an_ap4[8]; 356 }; 357 358 /* 359 * Driver name. 360 */ 361 #define AN_RID_DRVNAME 0xFF13 362 struct an_ltv_drvname { 363 u_int16_t an_len; 364 u_int16_t an_type; 365 u_int8_t an_drvname[16]; 366 }; 367 368 /* 369 * Frame encapsulation. 370 */ 371 #define AN_RID_ENCAP 0xFF14 372 struct an_rid_encap { 373 u_int16_t an_len; 374 u_int16_t an_type; 375 u_int16_t an_ethertype_default; 376 u_int16_t an_action_default; 377 u_int16_t an_ethertype0; 378 u_int16_t an_action0; 379 u_int16_t an_ethertype1; 380 u_int16_t an_action1; 381 u_int16_t an_ethertype2; 382 u_int16_t an_action2; 383 u_int16_t an_ethertype3; 384 u_int16_t an_action3; 385 u_int16_t an_ethertype4; 386 u_int16_t an_action4; 387 u_int16_t an_ethertype5; 388 u_int16_t an_action5; 389 u_int16_t an_ethertype6; 390 u_int16_t an_action6; 391 }; 392 393 #define AN_ENCAP_ACTION_RX 0x0001 394 #define AN_ENCAP_ACTION_TX 0x0002 395 396 #define AN_RXENCAP_NONE 0x0000 397 #define AN_RXENCAP_RFC1024 0x0001 398 399 #define AN_TXENCAP_RFC1024 0x0000 400 #define AN_TXENCAP_80211 0x0002 401 402 /* 403 * Actual config, same structure as general config (read only). 404 */ 405 #define AN_RID_ACTUALCFG 0xFF20 406 407 /* 408 * Card capabilities (read only). 409 */ 410 #define AN_RID_CAPABILITIES 0xFF00 411 struct an_ltv_caps { 412 u_int16_t an_len; /* 0x00 */ 413 u_int16_t an_type; /* XXXX */ 414 u_int8_t an_oui[3]; /* 0x02 */ 415 u_int8_t an_rsvd0; /* 0x05 */ 416 u_int16_t an_prodnum; /* 0x06 */ 417 u_int8_t an_manufname[32]; /* 0x08 */ 418 u_int8_t an_prodname[16]; /* 0x28 */ 419 u_int8_t an_prodvers[8]; /* 0x38 */ 420 u_int8_t an_oemaddr[6]; /* 0x40 */ 421 u_int8_t an_aironetaddr[6]; /* 0x46 */ 422 u_int16_t an_radiotype; /* 0x4C */ 423 u_int16_t an_regdomain; /* 0x4E */ 424 u_int8_t an_callid[6]; /* 0x50 */ 425 u_int8_t an_rates[8]; /* 0x56 */ 426 u_int8_t an_rx_diversity; /* 0x5E */ 427 u_int8_t an_tx_diversity; /* 0x5F */ 428 u_int16_t an_tx_powerlevels[8]; /* 0x60 */ 429 u_int16_t an_hwrev; /* 0x70 */ 430 u_int16_t an_hwcaps; /* 0x72 */ 431 u_int16_t an_temprange; /* 0x74 */ 432 u_int16_t an_fwrev; /* 0x76 */ 433 u_int16_t an_fwsubrev; /* 0x78 */ 434 u_int16_t an_ifacerev; /* 0x7A */ 435 u_int16_t an_softcaps; /* 0x7C */ 436 u_int16_t an_bootblockrev; /* 0x7E */ 437 u_int16_t an_req_hw_support; /* 0x80 */ 438 }; 439 440 /* 441 * Access point (read only) 442 */ 443 #define AN_RID_APINFO 0xFF01 444 struct an_ltv_apinfo { 445 u_int16_t an_len; 446 u_int16_t an_type; 447 u_int16_t an_tim_addr; 448 u_int16_t an_airo_addr; 449 }; 450 451 /* 452 * Radio info (read only). 453 */ 454 #define AN_RID_RADIOINFO 0xFF02 455 struct an_ltv_radioinfo { 456 u_int16_t an_len; 457 u_int16_t an_type; 458 /* ??? */ 459 }; 460 461 /* 462 * Status (read only). Note: the manual claims this RID is 108 bytes 463 * long (0x6A is the last datum, which is 2 bytes long) however when 464 * this RID is read from the NIC, it returns a length of 110 or 112. 465 * To be on the safe side, this structure is padded with 4 extra 16-bit 466 * words. (There is a misprint in the manual which says the macaddr 467 * field is 8 bytes long.) 468 * 469 * Also, the channel_set and current_channel fields appear to be 470 * reversed. Either that, or the hop_period field is unused. 471 */ 472 #define AN_RID_STATUS 0xFF50 473 struct an_ltv_status { 474 u_int16_t an_len; /* 0x00 */ 475 u_int16_t an_type; /* 0xXX */ 476 u_int8_t an_macaddr[6]; /* 0x02 */ 477 u_int16_t an_opmode; /* 0x08 */ 478 u_int16_t an_errcode; /* 0x0A */ 479 u_int16_t an_cur_signal_strength; /* 0x0C */ 480 u_int16_t an_ssidlen; /* 0x0E */ 481 u_int8_t an_ssid[32]; /* 0x10 */ 482 u_int8_t an_ap_name[16]; /* 0x30 */ 483 u_int8_t an_cur_bssid[6]; /* 0x40 */ 484 u_int8_t an_prev_bssid1[6]; /* 0x46 */ 485 u_int8_t an_prev_bssid2[6]; /* 0x4C */ 486 u_int8_t an_prev_bssid3[6]; /* 0x52 */ 487 u_int16_t an_beacon_period; /* 0x58 */ 488 u_int16_t an_dtim_period; /* 0x5A */ 489 u_int16_t an_atim_duration; /* 0x5C */ 490 u_int16_t an_hop_period; /* 0x5E */ 491 u_int16_t an_cur_channel; /* 0x62 */ 492 u_int16_t an_channel_set; /* 0x60 */ 493 u_int16_t an_hops_to_backbone; /* 0x64 */ 494 u_int16_t an_ap_total_load; /* 0x66 */ 495 u_int16_t an_our_generated_load; /* 0x68 */ 496 u_int16_t an_accumulated_arl; /* 0x6A */ 497 u_int16_t an_cur_signal_quality; /* 0x6C */ 498 u_int16_t an_current_tx_rate; /* 0x6E */ 499 u_int16_t an_ap_device; /* 0x70 */ 500 u_int16_t an_normalized_rssi; /* 0x72 */ 501 u_int16_t an_short_pre_in_use; /* 0x74 */ 502 u_int8_t an_ap_ip_addr[4]; /* 0x76 */ 503 u_int16_t an_max_noise_prev_sec; /* 0x7A */ 504 u_int16_t an_avg_noise_prev_min; /* 0x7C */ 505 u_int16_t an_max_noise_prev_min; /* 0x7E */ 506 u_int16_t an_spare[4]; 507 }; 508 509 #define AN_STATUS_OPMODE_CONFIGURED 0x0001 510 #define AN_STATUS_OPMODE_MAC_ENABLED 0x0002 511 #define AN_STATUS_OPMODE_RX_ENABLED 0x0004 512 #define AN_STATUS_OPMODE_IN_SYNC 0x0010 513 #define AN_STATUS_OPMODE_ASSOCIATED 0x0020 514 #define AN_STATUS_OPMODE_ERROR 0x8000 515 516 517 /* 518 * Statistics 519 */ 520 #define AN_RID_16BITS_CUM 0xFF60 /* Cumulative 16-bit stats counters */ 521 #define AN_RID_16BITS_DELTA 0xFF61 /* 16-bit stats (since last clear) */ 522 #define AN_RID_16BITS_DELTACLR 0xFF62 /* 16-bit stats, clear on read */ 523 #define AN_RID_32BITS_CUM 0xFF68 /* Cumulative 32-bit stats counters */ 524 #define AN_RID_32BITS_DELTA 0xFF69 /* 32-bit stats (since last clear) */ 525 #define AN_RID_32BITS_DELTACLR 0xFF6A /* 32-bit stats, clear on read */ 526 527 /* 528 * Grrr. The manual says the statistics record is 384 bytes in length, 529 * but the card says the record is 404 bytes. There's some padding left 530 * at the end of this structure to account for any discrepancies. 531 */ 532 struct an_ltv_stats { 533 u_int16_t an_len; /* 0x00 */ 534 u_int16_t an_type; /* 0xXX */ 535 u_int16_t an_spacer; /* 0x02 */ 536 u_int32_t an_rx_overruns; /* 0x04 */ 537 u_int32_t an_rx_plcp_csum_errs; /* 0x08 */ 538 u_int32_t an_rx_plcp_format_errs; /* 0x0C */ 539 u_int32_t an_rx_plcp_len_errs; /* 0x10 */ 540 u_int32_t an_rx_mac_crc_errs; /* 0x14 */ 541 u_int32_t an_rx_mac_crc_ok; /* 0x18 */ 542 u_int32_t an_rx_wep_errs; /* 0x1C */ 543 u_int32_t an_rx_wep_ok; /* 0x20 */ 544 u_int32_t an_retry_long; /* 0x24 */ 545 u_int32_t an_retry_short; /* 0x28 */ 546 u_int32_t an_retry_max; /* 0x2C */ 547 u_int32_t an_no_ack; /* 0x30 */ 548 u_int32_t an_no_cts; /* 0x34 */ 549 u_int32_t an_rx_ack_ok; /* 0x38 */ 550 u_int32_t an_rx_cts_ok; /* 0x3C */ 551 u_int32_t an_tx_ack_ok; /* 0x40 */ 552 u_int32_t an_tx_rts_ok; /* 0x44 */ 553 u_int32_t an_tx_cts_ok; /* 0x48 */ 554 u_int32_t an_tx_lmac_mcasts; /* 0x4C */ 555 u_int32_t an_tx_lmac_bcasts; /* 0x50 */ 556 u_int32_t an_tx_lmac_ucast_frags; /* 0x54 */ 557 u_int32_t an_tx_lmac_ucasts; /* 0x58 */ 558 u_int32_t an_tx_beacons; /* 0x5C */ 559 u_int32_t an_rx_beacons; /* 0x60 */ 560 u_int32_t an_tx_single_cols; /* 0x64 */ 561 u_int32_t an_tx_multi_cols; /* 0x68 */ 562 u_int32_t an_tx_defers_no; /* 0x6C */ 563 u_int32_t an_tx_defers_prot; /* 0x70 */ 564 u_int32_t an_tx_defers_energy; /* 0x74 */ 565 u_int32_t an_rx_dups; /* 0x78 */ 566 u_int32_t an_rx_partial; /* 0x7C */ 567 u_int32_t an_tx_too_old; /* 0x80 */ 568 u_int32_t an_rx_too_old; /* 0x84 */ 569 u_int32_t an_lostsync_max_retries;/* 0x88 */ 570 u_int32_t an_lostsync_missed_beacons;/* 0x8C */ 571 u_int32_t an_lostsync_arl_exceeded;/*0x90 */ 572 u_int32_t an_lostsync_deauthed; /* 0x94 */ 573 u_int32_t an_lostsync_disassociated;/*0x98 */ 574 u_int32_t an_lostsync_tsf_timing; /* 0x9C */ 575 u_int32_t an_tx_host_mcasts; /* 0xA0 */ 576 u_int32_t an_tx_host_bcasts; /* 0xA4 */ 577 u_int32_t an_tx_host_ucasts; /* 0xA8 */ 578 u_int32_t an_tx_host_failed; /* 0xAC */ 579 u_int32_t an_rx_host_mcasts; /* 0xB0 */ 580 u_int32_t an_rx_host_bcasts; /* 0xB4 */ 581 u_int32_t an_rx_host_ucasts; /* 0xB8 */ 582 u_int32_t an_rx_host_discarded; /* 0xBC */ 583 u_int32_t an_tx_hmac_mcasts; /* 0xC0 */ 584 u_int32_t an_tx_hmac_bcasts; /* 0xC4 */ 585 u_int32_t an_tx_hmac_ucasts; /* 0xC8 */ 586 u_int32_t an_tx_hmac_failed; /* 0xCC */ 587 u_int32_t an_rx_hmac_mcasts; /* 0xD0 */ 588 u_int32_t an_rx_hmac_bcasts; /* 0xD4 */ 589 u_int32_t an_rx_hmac_ucasts; /* 0xD8 */ 590 u_int32_t an_rx_hmac_discarded; /* 0xDC */ 591 u_int32_t an_tx_hmac_accepted; /* 0xE0 */ 592 u_int32_t an_ssid_mismatches; /* 0xE4 */ 593 u_int32_t an_ap_mismatches; /* 0xE8 */ 594 u_int32_t an_rates_mismatches; /* 0xEC */ 595 u_int32_t an_auth_rejects; /* 0xF0 */ 596 u_int32_t an_auth_timeouts; /* 0xF4 */ 597 u_int32_t an_assoc_rejects; /* 0xF8 */ 598 u_int32_t an_assoc_timeouts; /* 0xFC */ 599 u_int32_t an_reason_outside_table;/* 0x100 */ 600 u_int32_t an_reason1; /* 0x104 */ 601 u_int32_t an_reason2; /* 0x108 */ 602 u_int32_t an_reason3; /* 0x10C */ 603 u_int32_t an_reason4; /* 0x110 */ 604 u_int32_t an_reason5; /* 0x114 */ 605 u_int32_t an_reason6; /* 0x118 */ 606 u_int32_t an_reason7; /* 0x11C */ 607 u_int32_t an_reason8; /* 0x120 */ 608 u_int32_t an_reason9; /* 0x124 */ 609 u_int32_t an_reason10; /* 0x128 */ 610 u_int32_t an_reason11; /* 0x12C */ 611 u_int32_t an_reason12; /* 0x130 */ 612 u_int32_t an_reason13; /* 0x134 */ 613 u_int32_t an_reason14; /* 0x138 */ 614 u_int32_t an_reason15; /* 0x13C */ 615 u_int32_t an_reason16; /* 0x140 */ 616 u_int32_t an_reason17; /* 0x144 */ 617 u_int32_t an_reason18; /* 0x148 */ 618 u_int32_t an_reason19; /* 0x14C */ 619 u_int32_t an_rx_mgmt_pkts; /* 0x150 */ 620 u_int32_t an_tx_mgmt_pkts; /* 0x154 */ 621 u_int32_t an_rx_refresh_pkts; /* 0x158 */ 622 u_int32_t an_tx_refresh_pkts; /* 0x15C */ 623 u_int32_t an_rx_poll_pkts; /* 0x160 */ 624 u_int32_t an_tx_poll_pkts; /* 0x164 */ 625 u_int32_t an_host_retries; /* 0x168 */ 626 u_int32_t an_lostsync_hostreq; /* 0x16C */ 627 u_int32_t an_host_tx_bytes; /* 0x170 */ 628 u_int32_t an_host_rx_bytes; /* 0x174 */ 629 u_int32_t an_uptime_usecs; /* 0x178 */ 630 u_int32_t an_uptime_secs; /* 0x17C */ 631 u_int32_t an_lostsync_better_ap; /* 0x180 */ 632 u_int32_t an_rsvd[10]; 633 }; 634 635 /* 636 * Volatile WEP Key 637 */ 638 #define AN_RID_WEP_VOLATILE 0xFF15 /* Volatile WEP Key */ 639 struct an_ltv_wepkey { 640 u_int16_t an_len; /* 0x00 */ 641 u_int16_t an_type; /* 0xXX */ 642 u_int16_t an_key_index; /* 0x02 */ 643 u_int8_t an_mac_addr[6]; /* 0x04 */ 644 u_int16_t an_key_len; /* 0x0A */ 645 u_int8_t an_key[13]; /* 0x0C */ 646 }; 647 648 /* 649 * Persistent WEP Key 650 */ 651 #define AN_RID_WEP_PERSISTENT 0xFF16 /* Persistent WEP Key */ 652 653 /* 654 * LEAP Key 655 */ 656 #define AN_RID_LEAP_USER 0xFF23 /* User Name for LEAP */ 657 #define AN_RID_LEAP_PASS 0xFF24 /* Password for LEAP */ 658 struct an_ltv_leapkey { 659 u_int16_t an_len; /* 0x00 */ 660 u_int16_t an_type; /* 0xXX */ 661 u_int16_t an_key_len; /* 0x02 */ 662 u_int8_t an_key[32]; /* 0x04 */ 663 }; 664 665 /* 666 * Receive frame structure. 667 */ 668 struct an_rxframe { 669 u_int32_t an_rx_time; /* 0x00 */ 670 u_int16_t an_rx_status; /* 0x04 */ 671 u_int16_t an_rx_payload_len; /* 0x06 */ 672 u_int8_t an_rsvd0; /* 0x08 */ 673 u_int8_t an_rx_signal_strength; /* 0x09 */ 674 u_int8_t an_rx_rate; /* 0x0A */ 675 u_int8_t an_rx_chan; /* 0x0B */ 676 u_int8_t an_rx_assoc_cnt; /* 0x0C */ 677 u_int8_t an_rsvd1[3]; /* 0x0D */ 678 u_int8_t an_plcp_hdr[4]; /* 0x10 */ 679 u_int16_t an_frame_ctl; /* 0x14 */ 680 u_int16_t an_duration; /* 0x16 */ 681 u_int8_t an_addr1[6]; /* 0x18 */ 682 u_int8_t an_addr2[6]; /* 0x1E */ 683 u_int8_t an_addr3[6]; /* 0x24 */ 684 u_int16_t an_seq_ctl; /* 0x2A */ 685 u_int8_t an_addr4[6]; /* 0x2C */ 686 u_int16_t an_gaplen; /* 0x32 */ 687 }; 688 689 #define AN_RXGAP_MAX 8 690 691 /* 692 * Transmit frame structure. 693 */ 694 struct an_txframe { 695 u_int32_t an_tx_sw; /* 0x00 */ 696 u_int16_t an_tx_status; /* 0x04 */ 697 u_int16_t an_tx_payload_len; /* 0x06 */ 698 u_int16_t an_tx_ctl; /* 0x08 */ 699 u_int16_t an_tx_assoc_id; /* 0x0A */ 700 u_int16_t an_tx_retry; /* 0x0C */ 701 u_int8_t an_tx_assoc_cnt; /* 0x0E */ 702 u_int8_t an_tx_rate; /* 0x0F */ 703 u_int8_t an_tx_max_long_retries; /* 0x10 */ 704 u_int8_t an_tx_max_short_retries; /*0x11 */ 705 u_int8_t an_rsvd0[2]; /* 0x12 */ 706 u_int16_t an_frame_ctl; /* 0x14 */ 707 u_int16_t an_duration; /* 0x16 */ 708 u_int8_t an_addr1[6]; /* 0x18 */ 709 u_int8_t an_addr2[6]; /* 0x1E */ 710 u_int8_t an_addr3[6]; /* 0x24 */ 711 u_int16_t an_seq_ctl; /* 0x2A */ 712 u_int8_t an_addr4[6]; /* 0x2C */ 713 u_int16_t an_gaplen; /* 0x32 */ 714 }; 715 716 struct an_rxframe_802_3 { 717 u_int16_t an_rx_802_3_status; /* 0x34 */ 718 u_int16_t an_rx_802_3_payload_len;/* 0x36 */ 719 u_int8_t an_rx_dst_addr[6]; /* 0x38 */ 720 u_int8_t an_rx_src_addr[6]; /* 0x3E */ 721 }; 722 #define AN_RXGAP_MAX 8 723 724 struct an_txframe_802_3 { 725 /* 726 * Transmit 802.3 header structure. 727 */ 728 u_int16_t an_tx_802_3_status; /* 0x34 */ 729 u_int16_t an_tx_802_3_payload_len;/* 0x36 */ 730 u_int8_t an_tx_dst_addr[6]; /* 0x38 */ 731 u_int8_t an_tx_src_addr[6]; /* 0x3E */ 732 }; 733 734 #define AN_TXSTAT_EXCESS_RETRY 0x0002 735 #define AN_TXSTAT_LIFE_EXCEEDED 0x0004 736 #define AN_TXSTAT_AID_FAIL 0x0008 737 #define AN_TXSTAT_MAC_DISABLED 0x0010 738 #define AN_TXSTAT_ASSOC_LOST 0x0020 739 740 #define AN_TXCTL_RSVD 0x0001 741 #define AN_TXCTL_TXOK_INTR 0x0002 742 #define AN_TXCTL_TXERR_INTR 0x0004 743 #define AN_TXCTL_HEADER_TYPE 0x0008 744 #define AN_TXCTL_PAYLOAD_TYPE 0x0010 745 #define AN_TXCTL_NORELEASE 0x0020 746 #define AN_TXCTL_NORETRIES 0x0040 747 #define AN_TXCTL_CLEAR_AID 0x0080 748 #define AN_TXCTL_STRICT_ORDER 0x0100 749 #define AN_TXCTL_USE_RTS 0x0200 750 751 #define AN_HEADERTYPE_8023 0x0000 752 #define AN_HEADERTYPE_80211 0x0008 753 754 #define AN_PAYLOADTYPE_ETHER 0x0000 755 #define AN_PAYLOADTYPE_LLC 0x0010 756 757 #define AN_TXCTL_80211 \ 758 (AN_TXCTL_TXOK_INTR|AN_TXCTL_TXERR_INTR|AN_HEADERTYPE_80211| \ 759 AN_PAYLOADTYPE_LLC|AN_TXCTL_NORELEASE) 760 761 #define AN_TXCTL_8023 \ 762 (AN_TXCTL_TXOK_INTR|AN_TXCTL_TXERR_INTR|AN_HEADERTYPE_8023| \ 763 AN_PAYLOADTYPE_ETHER|AN_TXCTL_NORELEASE) 764 765 #define AN_802_3_OFFSET 0x34 766 #define AN_802_11_OFFSET 0x44 767 #define AN_802_11_OFFSET_RAW 0x3C 768 769 #define AN_STAT_BADCRC 0x0001 770 #define AN_STAT_UNDECRYPTABLE 0x0002 771 #define AN_STAT_ERRSTAT 0x0003 772 #define AN_STAT_MAC_PORT 0x0700 773 #define AN_STAT_1042 0x2000 /* RFC1042 encoded */ 774 #define AN_STAT_TUNNEL 0x4000 /* Bridge-tunnel encoded */ 775 #define AN_STAT_WMP_MSG 0x6000 /* WaveLAN-II management protocol */ 776 #define AN_RXSTAT_MSG_TYPE 0xE000 777 778 #define AN_ENC_TX_802_3 0x00 779 #define AN_ENC_TX_802_11 0x11 780 #define AN_ENC_TX_E_II 0x0E 781 782 #define AN_ENC_TX_1042 0x00 783 #define AN_ENC_TX_TUNNEL 0xF8 784 785 #define AN_TXCNTL_MACPORT 0x00FF 786 #define AN_TXCNTL_STRUCTTYPE 0xFF00 787 788 #endif /* _DEV_IC_ANREG_H */ 789