1 /* $NetBSD: bcmgenet.c,v 1.13 2022/08/01 07:37:18 mlelstv Exp $ */ 2 3 /*- 4 * Copyright (c) 2020 Jared McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * Broadcom GENETv5 31 */ 32 33 #include "opt_net_mpsafe.h" 34 #include "opt_ddb.h" 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: bcmgenet.c,v 1.13 2022/08/01 07:37:18 mlelstv Exp $"); 38 39 #include <sys/param.h> 40 #include <sys/bus.h> 41 #include <sys/device.h> 42 #include <sys/intr.h> 43 #include <sys/systm.h> 44 #include <sys/kernel.h> 45 #include <sys/mutex.h> 46 #include <sys/callout.h> 47 #include <sys/cprng.h> 48 49 #include <sys/rndsource.h> 50 51 #include <net/if.h> 52 #include <net/if_dl.h> 53 #include <net/if_ether.h> 54 #include <net/if_media.h> 55 #include <net/bpf.h> 56 57 #include <dev/mii/miivar.h> 58 59 #include <dev/ic/bcmgenetreg.h> 60 #include <dev/ic/bcmgenetvar.h> 61 62 CTASSERT(MCLBYTES == 2048); 63 64 #ifdef GENET_DEBUG 65 #define DPRINTF(...) printf(##__VA_ARGS__) 66 #else 67 #define DPRINTF(...) ((void)0) 68 #endif 69 70 #ifdef NET_MPSAFE 71 #define GENET_MPSAFE 1 72 #define CALLOUT_FLAGS CALLOUT_MPSAFE 73 #else 74 #define CALLOUT_FLAGS 0 75 #endif 76 77 #define TX_MAX_SEGS 128 78 #define TX_DESC_COUNT 256 /* GENET_DMA_DESC_COUNT */ 79 #define RX_DESC_COUNT 256 /* GENET_DMA_DESC_COUNT */ 80 #define MII_BUSY_RETRY 1000 81 #define GENET_MAX_MDF_FILTER 17 82 83 #define TX_SKIP(n, o) (((n) + (o)) % TX_DESC_COUNT) 84 #define TX_NEXT(n) TX_SKIP(n, 1) 85 #define RX_NEXT(n) (((n) + 1) % RX_DESC_COUNT) 86 87 #define GENET_LOCK(sc) mutex_enter(&(sc)->sc_lock) 88 #define GENET_UNLOCK(sc) mutex_exit(&(sc)->sc_lock) 89 #define GENET_ASSERT_LOCKED(sc) KASSERT(mutex_owned(&(sc)->sc_lock)) 90 91 #define GENET_TXLOCK(sc) mutex_enter(&(sc)->sc_txlock) 92 #define GENET_TXUNLOCK(sc) mutex_exit(&(sc)->sc_txlock) 93 #define GENET_ASSERT_TXLOCKED(sc) KASSERT(mutex_owned(&(sc)->sc_txlock)) 94 95 #define RD4(sc, reg) \ 96 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 97 #define WR4(sc, reg, val) \ 98 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 99 100 static int 101 genet_mii_readreg(device_t dev, int phy, int reg, uint16_t *val) 102 { 103 struct genet_softc *sc = device_private(dev); 104 int retry; 105 106 WR4(sc, GENET_MDIO_CMD, 107 GENET_MDIO_READ | GENET_MDIO_START_BUSY | 108 __SHIFTIN(phy, GENET_MDIO_PMD) | 109 __SHIFTIN(reg, GENET_MDIO_REG)); 110 for (retry = MII_BUSY_RETRY; retry > 0; retry--) { 111 if ((RD4(sc, GENET_MDIO_CMD) & GENET_MDIO_START_BUSY) == 0) { 112 *val = RD4(sc, GENET_MDIO_CMD) & 0xffff; 113 break; 114 } 115 delay(10); 116 } 117 118 119 if (retry == 0) { 120 device_printf(dev, "phy read timeout, phy=%d reg=%d\n", 121 phy, reg); 122 return ETIMEDOUT; 123 } 124 125 return 0; 126 } 127 128 static int 129 genet_mii_writereg(device_t dev, int phy, int reg, uint16_t val) 130 { 131 struct genet_softc *sc = device_private(dev); 132 int retry; 133 134 WR4(sc, GENET_MDIO_CMD, 135 val | GENET_MDIO_WRITE | GENET_MDIO_START_BUSY | 136 __SHIFTIN(phy, GENET_MDIO_PMD) | 137 __SHIFTIN(reg, GENET_MDIO_REG)); 138 for (retry = MII_BUSY_RETRY; retry > 0; retry--) { 139 if ((RD4(sc, GENET_MDIO_CMD) & GENET_MDIO_START_BUSY) == 0) 140 break; 141 delay(10); 142 } 143 144 if (retry == 0) { 145 device_printf(dev, "phy write timeout, phy=%d reg=%d\n", 146 phy, reg); 147 return ETIMEDOUT; 148 } 149 150 return 0; 151 } 152 153 static void 154 genet_update_link(struct genet_softc *sc) 155 { 156 struct mii_data *mii = &sc->sc_mii; 157 uint32_t val; 158 u_int speed; 159 160 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 161 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 162 speed = GENET_UMAC_CMD_SPEED_1000; 163 else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) 164 speed = GENET_UMAC_CMD_SPEED_100; 165 else 166 speed = GENET_UMAC_CMD_SPEED_10; 167 168 val = RD4(sc, GENET_EXT_RGMII_OOB_CTRL); 169 val &= ~GENET_EXT_RGMII_OOB_OOB_DISABLE; 170 val |= GENET_EXT_RGMII_OOB_RGMII_LINK; 171 val |= GENET_EXT_RGMII_OOB_RGMII_MODE_EN; 172 if (sc->sc_phy_mode == GENET_PHY_MODE_RGMII) 173 val |= GENET_EXT_RGMII_OOB_ID_MODE_DISABLE; 174 else 175 val &= ~GENET_EXT_RGMII_OOB_ID_MODE_DISABLE; 176 WR4(sc, GENET_EXT_RGMII_OOB_CTRL, val); 177 178 val = RD4(sc, GENET_UMAC_CMD); 179 val &= ~GENET_UMAC_CMD_SPEED; 180 val |= __SHIFTIN(speed, GENET_UMAC_CMD_SPEED); 181 WR4(sc, GENET_UMAC_CMD, val); 182 } 183 184 static void 185 genet_mii_statchg(struct ifnet *ifp) 186 { 187 struct genet_softc * const sc = ifp->if_softc; 188 189 genet_update_link(sc); 190 } 191 192 static void 193 genet_setup_txdesc(struct genet_softc *sc, int index, int flags, 194 bus_addr_t paddr, u_int len) 195 { 196 uint32_t status; 197 198 status = flags | __SHIFTIN(len, GENET_TX_DESC_STATUS_BUFLEN); 199 200 WR4(sc, GENET_TX_DESC_ADDRESS_LO(index), (uint32_t)paddr); 201 WR4(sc, GENET_TX_DESC_ADDRESS_HI(index), (uint32_t)(paddr >> 32)); 202 WR4(sc, GENET_TX_DESC_STATUS(index), status); 203 } 204 205 static int 206 genet_setup_txbuf(struct genet_softc *sc, int index, struct mbuf *m) 207 { 208 bus_dma_segment_t *segs; 209 int error, nsegs, cur, i; 210 uint32_t flags; 211 bool nospace; 212 213 /* at least one descriptor free ? */ 214 if (sc->sc_tx.queued >= TX_DESC_COUNT - 1) 215 return -1; 216 217 error = bus_dmamap_load_mbuf(sc->sc_tx.buf_tag, 218 sc->sc_tx.buf_map[index].map, m, BUS_DMA_WRITE | BUS_DMA_NOWAIT); 219 if (error == EFBIG) { 220 device_printf(sc->sc_dev, 221 "TX packet needs too many DMA segments, dropping...\n"); 222 return -2; 223 } 224 if (error != 0) { 225 device_printf(sc->sc_dev, 226 "TX packet cannot be mapped, retried...\n"); 227 return 0; 228 } 229 230 segs = sc->sc_tx.buf_map[index].map->dm_segs; 231 nsegs = sc->sc_tx.buf_map[index].map->dm_nsegs; 232 233 nospace = sc->sc_tx.queued >= TX_DESC_COUNT - nsegs; 234 if (nospace) { 235 bus_dmamap_unload(sc->sc_tx.buf_tag, 236 sc->sc_tx.buf_map[index].map); 237 /* XXX coalesce and retry ? */ 238 return -1; 239 } 240 241 bus_dmamap_sync(sc->sc_tx.buf_tag, sc->sc_tx.buf_map[index].map, 242 0, sc->sc_tx.buf_map[index].map->dm_mapsize, BUS_DMASYNC_PREWRITE); 243 244 /* stored in same index as loaded map */ 245 sc->sc_tx.buf_map[index].mbuf = m; 246 247 flags = GENET_TX_DESC_STATUS_SOP | 248 GENET_TX_DESC_STATUS_CRC | 249 GENET_TX_DESC_STATUS_QTAG; 250 251 for (cur = index, i = 0; i < nsegs; i++) { 252 if (i == nsegs - 1) 253 flags |= GENET_TX_DESC_STATUS_EOP; 254 255 genet_setup_txdesc(sc, cur, flags, segs[i].ds_addr, 256 segs[i].ds_len); 257 258 if (i == 0) 259 flags &= ~GENET_TX_DESC_STATUS_SOP; 260 cur = TX_NEXT(cur); 261 } 262 263 return nsegs; 264 } 265 266 static void 267 genet_setup_rxdesc(struct genet_softc *sc, int index, 268 bus_addr_t paddr, bus_size_t len) 269 { 270 WR4(sc, GENET_RX_DESC_ADDRESS_LO(index), (uint32_t)paddr); 271 WR4(sc, GENET_RX_DESC_ADDRESS_HI(index), (uint32_t)(paddr >> 32)); 272 } 273 274 static int 275 genet_setup_rxbuf(struct genet_softc *sc, int index, struct mbuf *m) 276 { 277 int error; 278 279 error = bus_dmamap_load_mbuf(sc->sc_rx.buf_tag, 280 sc->sc_rx.buf_map[index].map, m, BUS_DMA_READ | BUS_DMA_NOWAIT); 281 if (error != 0) 282 return error; 283 284 bus_dmamap_sync(sc->sc_rx.buf_tag, sc->sc_rx.buf_map[index].map, 285 0, sc->sc_rx.buf_map[index].map->dm_mapsize, 286 BUS_DMASYNC_PREREAD); 287 288 sc->sc_rx.buf_map[index].mbuf = m; 289 genet_setup_rxdesc(sc, index, 290 sc->sc_rx.buf_map[index].map->dm_segs[0].ds_addr, 291 sc->sc_rx.buf_map[index].map->dm_segs[0].ds_len); 292 293 return 0; 294 } 295 296 static struct mbuf * 297 genet_alloc_mbufcl(struct genet_softc *sc) 298 { 299 struct mbuf *m; 300 301 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 302 if (m != NULL) 303 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 304 305 return m; 306 } 307 308 static void 309 genet_enable_intr(struct genet_softc *sc) 310 { 311 WR4(sc, GENET_INTRL2_CPU_CLEAR_MASK, 312 GENET_IRQ_TXDMA_DONE | GENET_IRQ_RXDMA_DONE); 313 } 314 315 static void 316 genet_disable_intr(struct genet_softc *sc) 317 { 318 /* Disable interrupts */ 319 WR4(sc, GENET_INTRL2_CPU_SET_MASK, 0xffffffff); 320 WR4(sc, GENET_INTRL2_CPU_CLEAR, 0xffffffff); 321 } 322 323 static void 324 genet_tick(void *softc) 325 { 326 struct genet_softc *sc = softc; 327 struct mii_data *mii = &sc->sc_mii; 328 #ifndef GENET_MPSAFE 329 int s = splnet(); 330 #endif 331 332 GENET_LOCK(sc); 333 mii_tick(mii); 334 callout_schedule(&sc->sc_stat_ch, hz); 335 GENET_UNLOCK(sc); 336 337 #ifndef GENET_MPSAFE 338 splx(s); 339 #endif 340 } 341 342 static void 343 genet_setup_rxfilter_mdf(struct genet_softc *sc, u_int n, const uint8_t *ea) 344 { 345 uint32_t addr0 = (ea[0] << 8) | ea[1]; 346 uint32_t addr1 = (ea[2] << 24) | (ea[3] << 16) | (ea[4] << 8) | ea[5]; 347 348 WR4(sc, GENET_UMAC_MDF_ADDR0(n), addr0); 349 WR4(sc, GENET_UMAC_MDF_ADDR1(n), addr1); 350 } 351 352 static void 353 genet_setup_rxfilter(struct genet_softc *sc) 354 { 355 struct ethercom *ec = &sc->sc_ec; 356 struct ifnet *ifp = &ec->ec_if; 357 struct ether_multistep step; 358 struct ether_multi *enm; 359 uint32_t cmd, mdf_ctrl; 360 u_int n; 361 362 GENET_ASSERT_LOCKED(sc); 363 364 ETHER_LOCK(ec); 365 366 cmd = RD4(sc, GENET_UMAC_CMD); 367 368 /* 369 * Count the required number of hardware filters. We need one 370 * for each multicast address, plus one for our own address and 371 * the broadcast address. 372 */ 373 ETHER_FIRST_MULTI(step, ec, enm); 374 for (n = 2; enm != NULL; n++) 375 ETHER_NEXT_MULTI(step, enm); 376 377 if (n > GENET_MAX_MDF_FILTER) 378 ifp->if_flags |= IFF_ALLMULTI; 379 else 380 ifp->if_flags &= ~IFF_ALLMULTI; 381 382 if ((ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) != 0) { 383 cmd |= GENET_UMAC_CMD_PROMISC; 384 mdf_ctrl = 0; 385 } else { 386 cmd &= ~GENET_UMAC_CMD_PROMISC; 387 genet_setup_rxfilter_mdf(sc, 0, ifp->if_broadcastaddr); 388 genet_setup_rxfilter_mdf(sc, 1, CLLADDR(ifp->if_sadl)); 389 ETHER_FIRST_MULTI(step, ec, enm); 390 for (n = 2; enm != NULL; n++) { 391 genet_setup_rxfilter_mdf(sc, n, enm->enm_addrlo); 392 ETHER_NEXT_MULTI(step, enm); 393 } 394 mdf_ctrl = __BITS(GENET_MAX_MDF_FILTER - 1, 395 GENET_MAX_MDF_FILTER - n); 396 } 397 398 WR4(sc, GENET_UMAC_CMD, cmd); 399 WR4(sc, GENET_UMAC_MDF_CTRL, mdf_ctrl); 400 401 ETHER_UNLOCK(ec); 402 } 403 404 static int 405 genet_reset(struct genet_softc *sc) 406 { 407 uint32_t val; 408 409 val = RD4(sc, GENET_SYS_RBUF_FLUSH_CTRL); 410 val |= GENET_SYS_RBUF_FLUSH_RESET; 411 WR4(sc, GENET_SYS_RBUF_FLUSH_CTRL, val); 412 delay(10); 413 414 val &= ~GENET_SYS_RBUF_FLUSH_RESET; 415 WR4(sc, GENET_SYS_RBUF_FLUSH_CTRL, val); 416 delay(10); 417 418 WR4(sc, GENET_SYS_RBUF_FLUSH_CTRL, 0); 419 delay(10); 420 421 WR4(sc, GENET_UMAC_CMD, 0); 422 WR4(sc, GENET_UMAC_CMD, 423 GENET_UMAC_CMD_LCL_LOOP_EN | GENET_UMAC_CMD_SW_RESET); 424 delay(10); 425 WR4(sc, GENET_UMAC_CMD, 0); 426 427 WR4(sc, GENET_UMAC_MIB_CTRL, GENET_UMAC_MIB_RESET_RUNT | 428 GENET_UMAC_MIB_RESET_RX | GENET_UMAC_MIB_RESET_TX); 429 WR4(sc, GENET_UMAC_MIB_CTRL, 0); 430 431 WR4(sc, GENET_UMAC_MAX_FRAME_LEN, 1536); 432 433 val = RD4(sc, GENET_RBUF_CTRL); 434 val |= GENET_RBUF_ALIGN_2B; 435 WR4(sc, GENET_RBUF_CTRL, val); 436 437 WR4(sc, GENET_RBUF_TBUF_SIZE_CTRL, 1); 438 439 return 0; 440 } 441 442 static void 443 genet_set_rxthresh(struct genet_softc *sc, int qid, int usecs, int count) 444 { 445 int ticks; 446 uint32_t val; 447 448 /* convert to 125MHz/1024 ticks */ 449 ticks = howmany(usecs * 125, 1024); 450 451 if (count < 1) 452 count = 1; 453 if (count > GENET_INTR_THRESHOLD_MASK) 454 count = GENET_INTR_THRESHOLD_MASK; 455 if (ticks < 0) 456 ticks = 0; 457 if (ticks > GENET_DMA_RING_TIMEOUT_MASK) 458 ticks = GENET_DMA_RING_TIMEOUT_MASK; 459 460 WR4(sc, GENET_RX_DMA_MBUF_DONE_THRES(qid), count); 461 462 val = RD4(sc, GENET_RX_DMA_RING_TIMEOUT(qid)); 463 val &= ~GENET_DMA_RING_TIMEOUT_MASK; 464 val |= ticks; 465 WR4(sc, GENET_RX_DMA_RING_TIMEOUT(qid), val); 466 } 467 468 static void 469 genet_set_txthresh(struct genet_softc *sc, int qid, int count) 470 { 471 if (count < 1) 472 count = 1; 473 if (count > GENET_INTR_THRESHOLD_MASK) 474 count = GENET_INTR_THRESHOLD_MASK; 475 476 WR4(sc, GENET_TX_DMA_MBUF_DONE_THRES(qid), count); 477 } 478 479 static void 480 genet_init_rings(struct genet_softc *sc, int qid) 481 { 482 uint32_t val; 483 484 /* TX ring */ 485 486 sc->sc_tx.queued = 0; 487 sc->sc_tx.cidx = sc->sc_tx.pidx = 0; 488 489 WR4(sc, GENET_TX_SCB_BURST_SIZE, 0x08); 490 491 WR4(sc, GENET_TX_DMA_READ_PTR_LO(qid), 0); 492 WR4(sc, GENET_TX_DMA_READ_PTR_HI(qid), 0); 493 WR4(sc, GENET_TX_DMA_CONS_INDEX(qid), 0); 494 WR4(sc, GENET_TX_DMA_PROD_INDEX(qid), 0); 495 WR4(sc, GENET_TX_DMA_RING_BUF_SIZE(qid), 496 __SHIFTIN(TX_DESC_COUNT, GENET_TX_DMA_RING_BUF_SIZE_DESC_COUNT) | 497 __SHIFTIN(MCLBYTES, GENET_TX_DMA_RING_BUF_SIZE_BUF_LENGTH)); 498 WR4(sc, GENET_TX_DMA_START_ADDR_LO(qid), 0); 499 WR4(sc, GENET_TX_DMA_START_ADDR_HI(qid), 0); 500 WR4(sc, GENET_TX_DMA_END_ADDR_LO(qid), 501 TX_DESC_COUNT * GENET_DMA_DESC_SIZE / 4 - 1); 502 WR4(sc, GENET_TX_DMA_END_ADDR_HI(qid), 0); 503 WR4(sc, GENET_TX_DMA_FLOW_PERIOD(qid), 0); 504 WR4(sc, GENET_TX_DMA_WRITE_PTR_LO(qid), 0); 505 WR4(sc, GENET_TX_DMA_WRITE_PTR_HI(qid), 0); 506 507 /* interrupt after 10 packets or when ring empty */ 508 genet_set_txthresh(sc, qid, 10); 509 510 WR4(sc, GENET_TX_DMA_RING_CFG, __BIT(qid)); /* enable */ 511 512 /* Enable transmit DMA */ 513 val = RD4(sc, GENET_TX_DMA_CTRL); 514 val |= GENET_TX_DMA_CTRL_EN; 515 val |= GENET_TX_DMA_CTRL_RBUF_EN(GENET_DMA_DEFAULT_QUEUE); 516 WR4(sc, GENET_TX_DMA_CTRL, val); 517 518 /* RX ring */ 519 520 sc->sc_rx.cidx = sc->sc_rx.pidx = 0; 521 522 WR4(sc, GENET_RX_SCB_BURST_SIZE, 0x08); 523 524 WR4(sc, GENET_RX_DMA_WRITE_PTR_LO(qid), 0); 525 WR4(sc, GENET_RX_DMA_WRITE_PTR_HI(qid), 0); 526 WR4(sc, GENET_RX_DMA_PROD_INDEX(qid), 0); 527 WR4(sc, GENET_RX_DMA_CONS_INDEX(qid), 0); 528 WR4(sc, GENET_RX_DMA_RING_BUF_SIZE(qid), 529 __SHIFTIN(RX_DESC_COUNT, GENET_RX_DMA_RING_BUF_SIZE_DESC_COUNT) | 530 __SHIFTIN(MCLBYTES, GENET_RX_DMA_RING_BUF_SIZE_BUF_LENGTH)); 531 WR4(sc, GENET_RX_DMA_START_ADDR_LO(qid), 0); 532 WR4(sc, GENET_RX_DMA_START_ADDR_HI(qid), 0); 533 WR4(sc, GENET_RX_DMA_END_ADDR_LO(qid), 534 RX_DESC_COUNT * GENET_DMA_DESC_SIZE / 4 - 1); 535 WR4(sc, GENET_RX_DMA_END_ADDR_HI(qid), 0); 536 WR4(sc, GENET_RX_DMA_XON_XOFF_THRES(qid), 537 __SHIFTIN(5, GENET_RX_DMA_XON_XOFF_THRES_LO) | 538 __SHIFTIN(RX_DESC_COUNT >> 4, GENET_RX_DMA_XON_XOFF_THRES_HI)); 539 WR4(sc, GENET_RX_DMA_READ_PTR_LO(qid), 0); 540 WR4(sc, GENET_RX_DMA_READ_PTR_HI(qid), 0); 541 542 /* 543 * interrupt on first packet, 544 * mitigation timeout timeout 57 us (~84 minimal packets at 1Gbit/s) 545 */ 546 genet_set_rxthresh(sc, qid, 57, 10); 547 548 WR4(sc, GENET_RX_DMA_RING_CFG, __BIT(qid)); /* enable */ 549 550 /* Enable receive DMA */ 551 val = RD4(sc, GENET_RX_DMA_CTRL); 552 val |= GENET_RX_DMA_CTRL_EN; 553 val |= GENET_RX_DMA_CTRL_RBUF_EN(GENET_DMA_DEFAULT_QUEUE); 554 WR4(sc, GENET_RX_DMA_CTRL, val); 555 } 556 557 static int 558 genet_init_locked(struct genet_softc *sc) 559 { 560 struct ifnet *ifp = &sc->sc_ec.ec_if; 561 struct mii_data *mii = &sc->sc_mii; 562 uint32_t val; 563 const uint8_t *enaddr = CLLADDR(ifp->if_sadl); 564 565 GENET_ASSERT_LOCKED(sc); 566 GENET_ASSERT_TXLOCKED(sc); 567 568 if ((ifp->if_flags & IFF_RUNNING) != 0) 569 return 0; 570 571 if (sc->sc_phy_mode == GENET_PHY_MODE_RGMII || 572 sc->sc_phy_mode == GENET_PHY_MODE_RGMII_ID || 573 sc->sc_phy_mode == GENET_PHY_MODE_RGMII_RXID || 574 sc->sc_phy_mode == GENET_PHY_MODE_RGMII_TXID) 575 WR4(sc, GENET_SYS_PORT_CTRL, 576 GENET_SYS_PORT_MODE_EXT_GPHY); 577 else 578 WR4(sc, GENET_SYS_PORT_CTRL, 0); 579 580 /* Write hardware address */ 581 val = enaddr[3] | (enaddr[2] << 8) | (enaddr[1] << 16) | 582 (enaddr[0] << 24); 583 WR4(sc, GENET_UMAC_MAC0, val); 584 val = enaddr[5] | (enaddr[4] << 8); 585 WR4(sc, GENET_UMAC_MAC1, val); 586 587 /* Setup RX filter */ 588 genet_setup_rxfilter(sc); 589 590 /* Setup TX/RX rings */ 591 genet_init_rings(sc, GENET_DMA_DEFAULT_QUEUE); 592 593 /* Enable transmitter and receiver */ 594 val = RD4(sc, GENET_UMAC_CMD); 595 val |= GENET_UMAC_CMD_TXEN; 596 val |= GENET_UMAC_CMD_RXEN; 597 WR4(sc, GENET_UMAC_CMD, val); 598 599 /* Enable interrupts */ 600 genet_enable_intr(sc); 601 602 ifp->if_flags |= IFF_RUNNING; 603 ifp->if_flags &= ~IFF_OACTIVE; 604 605 mii_mediachg(mii); 606 callout_schedule(&sc->sc_stat_ch, hz); 607 608 return 0; 609 } 610 611 static int 612 genet_init(struct ifnet *ifp) 613 { 614 struct genet_softc *sc = ifp->if_softc; 615 int error; 616 617 GENET_LOCK(sc); 618 GENET_TXLOCK(sc); 619 error = genet_init_locked(sc); 620 GENET_TXUNLOCK(sc); 621 GENET_UNLOCK(sc); 622 623 return error; 624 } 625 626 static void 627 genet_stop_locked(struct genet_softc *sc, int disable) 628 { 629 struct ifnet *ifp = &sc->sc_ec.ec_if; 630 uint32_t val; 631 632 GENET_ASSERT_LOCKED(sc); 633 634 callout_stop(&sc->sc_stat_ch); 635 636 mii_down(&sc->sc_mii); 637 638 /* Disable receiver */ 639 val = RD4(sc, GENET_UMAC_CMD); 640 val &= ~GENET_UMAC_CMD_RXEN; 641 WR4(sc, GENET_UMAC_CMD, val); 642 643 /* Stop receive DMA */ 644 val = RD4(sc, GENET_RX_DMA_CTRL); 645 val &= ~GENET_RX_DMA_CTRL_EN; 646 WR4(sc, GENET_RX_DMA_CTRL, val); 647 648 /* Stop transmit DMA */ 649 val = RD4(sc, GENET_TX_DMA_CTRL); 650 val &= ~GENET_TX_DMA_CTRL_EN; 651 WR4(sc, GENET_TX_DMA_CTRL, val); 652 653 /* Flush data in the TX FIFO */ 654 WR4(sc, GENET_UMAC_TX_FLUSH, 1); 655 delay(10); 656 WR4(sc, GENET_UMAC_TX_FLUSH, 0); 657 658 /* Disable transmitter */ 659 val = RD4(sc, GENET_UMAC_CMD); 660 val &= ~GENET_UMAC_CMD_TXEN; 661 WR4(sc, GENET_UMAC_CMD, val); 662 663 /* Disable interrupts */ 664 genet_disable_intr(sc); 665 666 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 667 } 668 669 static void 670 genet_stop(struct ifnet *ifp, int disable) 671 { 672 struct genet_softc * const sc = ifp->if_softc; 673 674 GENET_LOCK(sc); 675 genet_stop_locked(sc, disable); 676 GENET_UNLOCK(sc); 677 } 678 679 static void 680 genet_rxintr(struct genet_softc *sc, int qid) 681 { 682 struct ifnet *ifp = &sc->sc_ec.ec_if; 683 int error, index, len, n; 684 struct mbuf *m, *m0; 685 uint32_t status, pidx, total; 686 int pkts = 0; 687 688 pidx = RD4(sc, GENET_RX_DMA_PROD_INDEX(qid)) & 0xffff; 689 total = (pidx - sc->sc_rx.cidx) & 0xffff; 690 691 DPRINTF("RX pidx=%08x total=%d\n", pidx, total); 692 693 index = sc->sc_rx.cidx % RX_DESC_COUNT; 694 for (n = 0; n < total; n++) { 695 status = RD4(sc, GENET_RX_DESC_STATUS(index)); 696 697 if (status & GENET_RX_DESC_STATUS_ALL_ERRS) { 698 if (status & GENET_RX_DESC_STATUS_OVRUN_ERR) 699 device_printf(sc->sc_dev, "overrun\n"); 700 if (status & GENET_RX_DESC_STATUS_CRC_ERR) 701 device_printf(sc->sc_dev, "CRC error\n"); 702 if (status & GENET_RX_DESC_STATUS_RX_ERR) 703 device_printf(sc->sc_dev, "receive error\n"); 704 if (status & GENET_RX_DESC_STATUS_FRAME_ERR) 705 device_printf(sc->sc_dev, "frame error\n"); 706 if (status & GENET_RX_DESC_STATUS_LEN_ERR) 707 device_printf(sc->sc_dev, "length error\n"); 708 if_statinc(ifp, if_ierrors); 709 goto next; 710 } 711 712 if (status & GENET_RX_DESC_STATUS_OWN) 713 device_printf(sc->sc_dev, "OWN %d of %d\n",n,total); 714 715 len = __SHIFTOUT(status, GENET_RX_DESC_STATUS_BUFLEN); 716 if (len < ETHER_ALIGN) { 717 if_statinc(ifp, if_ierrors); 718 goto next; 719 } 720 721 m = sc->sc_rx.buf_map[index].mbuf; 722 723 if ((m0 = genet_alloc_mbufcl(sc)) == NULL) { 724 if_statinc(ifp, if_ierrors); 725 goto next; 726 } 727 728 /* unload map before it gets loaded in setup_rxbuf */ 729 if (sc->sc_rx.buf_map[index].map->dm_mapsize > 0) { 730 bus_dmamap_sync(sc->sc_rx.buf_tag, sc->sc_rx.buf_map[index].map, 731 0, sc->sc_rx.buf_map[index].map->dm_mapsize, 732 BUS_DMASYNC_POSTREAD); 733 } 734 bus_dmamap_unload(sc->sc_rx.buf_tag, sc->sc_rx.buf_map[index].map); 735 sc->sc_rx.buf_map[index].mbuf = NULL; 736 737 error = genet_setup_rxbuf(sc, index, m0); 738 if (error != 0) { 739 m_freem(m0); 740 if_statinc(ifp, if_ierrors); 741 742 /* XXX mbuf is unloaded but load failed */ 743 m_freem(m); 744 device_printf(sc->sc_dev, 745 "cannot load RX mbuf. panic?\n"); 746 goto next; 747 } 748 749 DPRINTF("RX [#%d] index=%02x status=%08x len=%d adj_len=%d\n", 750 n, index, status, len, len - ETHER_ALIGN); 751 752 m_set_rcvif(m, ifp); 753 m->m_len = m->m_pkthdr.len = len; 754 m_adj(m, ETHER_ALIGN); 755 756 if_percpuq_enqueue(ifp->if_percpuq, m); 757 ++pkts; 758 759 next: 760 index = RX_NEXT(index); 761 762 sc->sc_rx.cidx = (sc->sc_rx.cidx + 1) & 0xffff; 763 WR4(sc, GENET_RX_DMA_CONS_INDEX(qid), sc->sc_rx.cidx); 764 } 765 766 if (pkts != 0) 767 rnd_add_uint32(&sc->sc_rndsource, pkts); 768 } 769 770 static void 771 genet_txintr(struct genet_softc *sc, int qid) 772 { 773 struct ifnet *ifp = &sc->sc_ec.ec_if; 774 struct genet_bufmap *bmap; 775 int cidx, i, pkts = 0; 776 777 cidx = RD4(sc, GENET_TX_DMA_CONS_INDEX(qid)) & 0xffff; 778 i = sc->sc_tx.cidx % TX_DESC_COUNT; 779 while (sc->sc_tx.cidx != cidx) { 780 bmap = &sc->sc_tx.buf_map[i]; 781 if (bmap->mbuf != NULL) { 782 /* XXX first segment already unloads */ 783 if (bmap->map->dm_mapsize > 0) { 784 bus_dmamap_sync(sc->sc_tx.buf_tag, bmap->map, 785 0, bmap->map->dm_mapsize, 786 BUS_DMASYNC_POSTWRITE); 787 } 788 bus_dmamap_unload(sc->sc_tx.buf_tag, bmap->map); 789 m_freem(bmap->mbuf); 790 bmap->mbuf = NULL; 791 ++pkts; 792 } 793 794 ifp->if_flags &= ~IFF_OACTIVE; 795 i = TX_NEXT(i); 796 sc->sc_tx.cidx = (sc->sc_tx.cidx + 1) & 0xffff; 797 } 798 799 if_statadd(ifp, if_opackets, pkts); 800 801 if (pkts != 0) 802 rnd_add_uint32(&sc->sc_rndsource, pkts); 803 } 804 805 static void 806 genet_start_locked(struct genet_softc *sc) 807 { 808 struct ifnet *ifp = &sc->sc_ec.ec_if; 809 struct mbuf *m; 810 int nsegs, index, cnt; 811 812 GENET_ASSERT_TXLOCKED(sc); 813 814 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 815 return; 816 817 const int qid = GENET_DMA_DEFAULT_QUEUE; 818 819 index = sc->sc_tx.pidx % TX_DESC_COUNT; 820 cnt = 0; 821 822 sc->sc_tx.queued = (RD4(sc, GENET_TX_DMA_PROD_INDEX(qid)) 823 - RD4(sc, GENET_TX_DMA_CONS_INDEX(qid))) & 0xffff; 824 825 for (;;) { 826 IFQ_POLL(&ifp->if_snd, m); 827 if (m == NULL) 828 break; 829 830 nsegs = genet_setup_txbuf(sc, index, m); 831 if (nsegs <= 0) { 832 if (nsegs == -1) { 833 ifp->if_flags |= IFF_OACTIVE; 834 } 835 else if (nsegs == -2) { 836 IFQ_DEQUEUE(&ifp->if_snd, m); 837 m_freem(m); 838 } 839 break; 840 } 841 842 IFQ_DEQUEUE(&ifp->if_snd, m); 843 bpf_mtap(ifp, m, BPF_D_OUT); 844 845 index = TX_SKIP(index, nsegs); 846 sc->sc_tx.queued += nsegs; 847 sc->sc_tx.pidx = (sc->sc_tx.pidx + nsegs) & 0xffff; 848 cnt++; 849 } 850 851 if (cnt != 0) 852 WR4(sc, GENET_TX_DMA_PROD_INDEX(qid), sc->sc_tx.pidx); 853 } 854 855 static void 856 genet_start(struct ifnet *ifp) 857 { 858 struct genet_softc *sc = ifp->if_softc; 859 860 GENET_TXLOCK(sc); 861 genet_start_locked(sc); 862 GENET_TXUNLOCK(sc); 863 } 864 865 int 866 genet_intr(void *arg) 867 { 868 struct genet_softc *sc = arg; 869 struct ifnet *ifp = &sc->sc_ec.ec_if; 870 uint32_t val; 871 bool dotx = false; 872 873 val = RD4(sc, GENET_INTRL2_CPU_STAT); 874 val &= ~RD4(sc, GENET_INTRL2_CPU_STAT_MASK); 875 WR4(sc, GENET_INTRL2_CPU_CLEAR, val); 876 877 if (val & GENET_IRQ_RXDMA_DONE) { 878 GENET_LOCK(sc); 879 genet_rxintr(sc, GENET_DMA_DEFAULT_QUEUE); 880 GENET_UNLOCK(sc); 881 } 882 883 if (val & GENET_IRQ_TXDMA_DONE) { 884 genet_txintr(sc, GENET_DMA_DEFAULT_QUEUE); 885 dotx = true; 886 } 887 888 if (dotx) 889 if_schedule_deferred_start(ifp); 890 891 return 1; 892 } 893 894 static int 895 genet_ioctl(struct ifnet *ifp, u_long cmd, void *data) 896 { 897 struct genet_softc *sc = ifp->if_softc; 898 int error, s; 899 900 #ifndef GENET_MPSAFE 901 s = splnet(); 902 #endif 903 904 switch (cmd) { 905 default: 906 #ifdef GENET_MPSAFE 907 s = splnet(); 908 #endif 909 error = ether_ioctl(ifp, cmd, data); 910 #ifdef GENET_MPSAFE 911 splx(s); 912 #endif 913 if (error != ENETRESET) 914 break; 915 916 error = 0; 917 918 if (cmd == SIOCSIFCAP) 919 error = if_init(ifp); 920 else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 921 ; 922 else if ((ifp->if_flags & IFF_RUNNING) != 0) { 923 GENET_LOCK(sc); 924 genet_setup_rxfilter(sc); 925 GENET_UNLOCK(sc); 926 } 927 break; 928 } 929 930 #ifndef GENET_MPSAFE 931 splx(s); 932 #endif 933 934 return error; 935 } 936 937 static void 938 genet_get_eaddr(struct genet_softc *sc, uint8_t *eaddr) 939 { 940 prop_dictionary_t prop = device_properties(sc->sc_dev); 941 uint32_t maclo, machi, val; 942 prop_data_t eaprop; 943 944 eaprop = prop_dictionary_get(prop, "mac-address"); 945 if (eaprop != NULL) { 946 KASSERT(prop_object_type(eaprop) == PROP_TYPE_DATA); 947 KASSERT(prop_data_size(eaprop) == ETHER_ADDR_LEN); 948 memcpy(eaddr, prop_data_value(eaprop), 949 ETHER_ADDR_LEN); 950 return; 951 } 952 953 maclo = machi = 0; 954 955 val = RD4(sc, GENET_SYS_RBUF_FLUSH_CTRL); 956 if ((val & GENET_SYS_RBUF_FLUSH_RESET) == 0) { 957 maclo = htobe32(RD4(sc, GENET_UMAC_MAC0)); 958 machi = htobe16(RD4(sc, GENET_UMAC_MAC1) & 0xffff); 959 } 960 961 if (maclo == 0 && machi == 0) { 962 /* Create one */ 963 maclo = 0x00f2 | (cprng_strong32() & 0xffff0000); 964 machi = cprng_strong32() & 0xffff; 965 } 966 967 eaddr[0] = maclo & 0xff; 968 eaddr[1] = (maclo >> 8) & 0xff; 969 eaddr[2] = (maclo >> 16) & 0xff; 970 eaddr[3] = (maclo >> 24) & 0xff; 971 eaddr[4] = machi & 0xff; 972 eaddr[5] = (machi >> 8) & 0xff; 973 } 974 975 static int 976 genet_setup_dma(struct genet_softc *sc, int qid) 977 { 978 struct mbuf *m; 979 int error, i; 980 981 /* Setup TX ring */ 982 sc->sc_tx.buf_tag = sc->sc_dmat; 983 for (i = 0; i < TX_DESC_COUNT; i++) { 984 error = bus_dmamap_create(sc->sc_tx.buf_tag, MCLBYTES, 985 TX_MAX_SEGS, MCLBYTES, 0, BUS_DMA_WAITOK, 986 &sc->sc_tx.buf_map[i].map); 987 if (error != 0) { 988 device_printf(sc->sc_dev, 989 "cannot create TX buffer map\n"); 990 return error; 991 } 992 } 993 994 /* Setup RX ring */ 995 sc->sc_rx.buf_tag = sc->sc_dmat; 996 for (i = 0; i < RX_DESC_COUNT; i++) { 997 error = bus_dmamap_create(sc->sc_rx.buf_tag, MCLBYTES, 998 1, MCLBYTES, 0, BUS_DMA_WAITOK, 999 &sc->sc_rx.buf_map[i].map); 1000 if (error != 0) { 1001 device_printf(sc->sc_dev, 1002 "cannot create RX buffer map\n"); 1003 return error; 1004 } 1005 if ((m = genet_alloc_mbufcl(sc)) == NULL) { 1006 device_printf(sc->sc_dev, "cannot allocate RX mbuf\n"); 1007 return ENOMEM; 1008 } 1009 error = genet_setup_rxbuf(sc, i, m); 1010 if (error != 0) { 1011 device_printf(sc->sc_dev, "cannot create RX buffer\n"); 1012 return error; 1013 } 1014 } 1015 1016 return 0; 1017 } 1018 1019 int 1020 genet_attach(struct genet_softc *sc) 1021 { 1022 struct mii_data *mii = &sc->sc_mii; 1023 struct ifnet *ifp = &sc->sc_ec.ec_if; 1024 uint8_t eaddr[ETHER_ADDR_LEN]; 1025 u_int maj, min; 1026 int mii_flags = 0; 1027 1028 const uint32_t rev = RD4(sc, GENET_SYS_REV_CTRL); 1029 min = __SHIFTOUT(rev, SYS_REV_MINOR); 1030 maj = __SHIFTOUT(rev, SYS_REV_MAJOR); 1031 if (maj == 0) 1032 maj++; 1033 else if (maj == 5 || maj == 6) 1034 maj--; 1035 1036 if (maj != 5) { 1037 aprint_error(": GENETv%d.%d not supported\n", maj, min); 1038 return ENXIO; 1039 } 1040 1041 switch (sc->sc_phy_mode) { 1042 case GENET_PHY_MODE_RGMII_TXID: 1043 mii_flags |= MIIF_TXID; 1044 break; 1045 case GENET_PHY_MODE_RGMII_RXID: 1046 mii_flags |= MIIF_RXID; 1047 break; 1048 case GENET_PHY_MODE_RGMII_ID: 1049 mii_flags |= MIIF_RXID | MIIF_TXID; 1050 break; 1051 case GENET_PHY_MODE_RGMII: 1052 default: 1053 break; 1054 } 1055 1056 aprint_naive("\n"); 1057 aprint_normal(": GENETv%d.%d\n", maj, min); 1058 1059 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NET); 1060 mutex_init(&sc->sc_txlock, MUTEX_DEFAULT, IPL_NET); 1061 callout_init(&sc->sc_stat_ch, CALLOUT_FLAGS); 1062 callout_setfunc(&sc->sc_stat_ch, genet_tick, sc); 1063 1064 genet_get_eaddr(sc, eaddr); 1065 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", ether_sprintf(eaddr)); 1066 1067 /* Soft reset EMAC core */ 1068 genet_reset(sc); 1069 1070 /* Setup DMA descriptors */ 1071 if (genet_setup_dma(sc, GENET_DMA_DEFAULT_QUEUE) != 0) { 1072 aprint_error_dev(sc->sc_dev, "failed to setup DMA descriptors\n"); 1073 return EINVAL; 1074 } 1075 1076 /* Setup ethernet interface */ 1077 ifp->if_softc = sc; 1078 snprintf(ifp->if_xname, IFNAMSIZ, "%s", device_xname(sc->sc_dev)); 1079 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1080 #ifdef GENET_MPSAFE 1081 ifp->if_extflags = IFEF_MPSAFE; 1082 #endif 1083 ifp->if_start = genet_start; 1084 ifp->if_ioctl = genet_ioctl; 1085 ifp->if_init = genet_init; 1086 ifp->if_stop = genet_stop; 1087 ifp->if_capabilities = 0; 1088 ifp->if_capenable = ifp->if_capabilities; 1089 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 1090 IFQ_SET_READY(&ifp->if_snd); 1091 1092 /* 802.1Q VLAN-sized frames are supported */ 1093 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_MTU; 1094 1095 /* Attach MII driver */ 1096 sc->sc_ec.ec_mii = mii; 1097 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 1098 mii->mii_ifp = ifp; 1099 mii->mii_readreg = genet_mii_readreg; 1100 mii->mii_writereg = genet_mii_writereg; 1101 mii->mii_statchg = genet_mii_statchg; 1102 mii_attach(sc->sc_dev, mii, 0xffffffff, sc->sc_phy_id, MII_OFFSET_ANY, 1103 mii_flags); 1104 1105 if (LIST_EMPTY(&mii->mii_phys)) { 1106 aprint_error_dev(sc->sc_dev, "no PHY found!\n"); 1107 return ENOENT; 1108 } 1109 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 1110 1111 /* Attach interface */ 1112 if_attach(ifp); 1113 if_deferred_start_init(ifp, NULL); 1114 1115 /* Attach ethernet interface */ 1116 ether_ifattach(ifp, eaddr); 1117 1118 rnd_attach_source(&sc->sc_rndsource, ifp->if_xname, RND_TYPE_NET, 1119 RND_FLAG_DEFAULT); 1120 1121 return 0; 1122 } 1123 1124 #ifdef DDB 1125 void genet_debug(void); 1126 1127 void 1128 genet_debug(void) 1129 { 1130 device_t dev = device_find_by_xname("genet0"); 1131 if (dev == NULL) 1132 return; 1133 1134 struct genet_softc * const sc = device_private(dev); 1135 const int qid = GENET_DMA_DEFAULT_QUEUE; 1136 1137 printf("TX CIDX = %08x (soft)\n", sc->sc_tx.cidx); 1138 printf("TX CIDX = %08x\n", RD4(sc, GENET_TX_DMA_CONS_INDEX(qid))); 1139 printf("TX PIDX = %08x (soft)\n", sc->sc_tx.pidx); 1140 printf("TX PIDX = %08x\n", RD4(sc, GENET_TX_DMA_PROD_INDEX(qid))); 1141 1142 printf("RX CIDX = %08x (soft)\n", sc->sc_rx.cidx); 1143 printf("RX CIDX = %08x\n", RD4(sc, GENET_RX_DMA_CONS_INDEX(qid))); 1144 printf("RX PIDX = %08x (soft)\n", sc->sc_rx.pidx); 1145 printf("RX PIDX = %08x\n", RD4(sc, GENET_RX_DMA_PROD_INDEX(qid))); 1146 } 1147 #endif 1148