1 /* $NetBSD: clmpcc.c,v 1.20 2002/03/17 19:40:57 atatat Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Steve C. Woodford. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Cirrus Logic CD2400/CD2401 Four Channel Multi-Protocol Comms. Controller. 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: clmpcc.c,v 1.20 2002/03/17 19:40:57 atatat Exp $"); 45 46 #include "opt_ddb.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/ioctl.h> 51 #include <sys/select.h> 52 #include <sys/tty.h> 53 #include <sys/proc.h> 54 #include <sys/user.h> 55 #include <sys/conf.h> 56 #include <sys/file.h> 57 #include <sys/uio.h> 58 #include <sys/kernel.h> 59 #include <sys/syslog.h> 60 #include <sys/device.h> 61 #include <sys/malloc.h> 62 63 #include <machine/bus.h> 64 #include <machine/intr.h> 65 #include <machine/param.h> 66 67 #include <dev/ic/clmpccreg.h> 68 #include <dev/ic/clmpccvar.h> 69 #include <dev/cons.h> 70 71 72 #if defined(CLMPCC_ONLY_BYTESWAP_LOW) && defined(CLMPCC_ONLY_BYTESWAP_HIGH) 73 #error "CLMPCC_ONLY_BYTESWAP_LOW and CLMPCC_ONLY_BYTESWAP_HIGH are mutually exclusive." 74 #endif 75 76 77 static int clmpcc_init __P((struct clmpcc_softc *sc)); 78 static void clmpcc_shutdown __P((struct clmpcc_chan *)); 79 static int clmpcc_speed __P((struct clmpcc_softc *, speed_t, 80 int *, int *)); 81 static int clmpcc_param __P((struct tty *, struct termios *)); 82 static void clmpcc_set_params __P((struct clmpcc_chan *)); 83 static void clmpcc_start __P((struct tty *)); 84 static int clmpcc_modem_control __P((struct clmpcc_chan *, int, int)); 85 86 87 cdev_decl(clmpcc); 88 89 #define CLMPCCUNIT(x) (minor(x) & 0x7fffc) 90 #define CLMPCCCHAN(x) (minor(x) & 0x00003) 91 #define CLMPCCDIALOUT(x) (minor(x) & 0x80000) 92 93 /* 94 * These should be in a header file somewhere... 95 */ 96 #define ISSET(v, f) (((v) & (f)) != 0) 97 #define ISCLR(v, f) (((v) & (f)) == 0) 98 #define SET(v, f) (v) |= (f) 99 #define CLR(v, f) (v) &= ~(f) 100 101 102 extern struct cfdriver clmpcc_cd; 103 104 105 /* 106 * Make this an option variable one can patch. 107 */ 108 u_int clmpcc_ibuf_size = CLMPCC_RING_SIZE; 109 110 111 /* 112 * Things needed when the device is used as a console 113 */ 114 static struct clmpcc_softc *cons_sc = NULL; 115 static int cons_chan; 116 static int cons_rate; 117 118 static int clmpcc_common_getc __P((struct clmpcc_softc *, int)); 119 static void clmpcc_common_putc __P((struct clmpcc_softc *, int, int)); 120 int clmpcccngetc __P((dev_t)); 121 void clmpcccnputc __P((dev_t, int)); 122 123 124 /* 125 * Convenience functions, inlined for speed 126 */ 127 #define integrate static inline 128 integrate u_int8_t clmpcc_rdreg __P((struct clmpcc_softc *, u_int)); 129 integrate void clmpcc_wrreg __P((struct clmpcc_softc *, u_int, u_int)); 130 integrate u_int8_t clmpcc_rdreg_odd __P((struct clmpcc_softc *, u_int)); 131 integrate void clmpcc_wrreg_odd __P((struct clmpcc_softc *, u_int, u_int)); 132 integrate void clmpcc_wrtx_multi __P((struct clmpcc_softc *, u_int8_t *, 133 u_int)); 134 integrate u_int8_t clmpcc_select_channel __P((struct clmpcc_softc *, u_int)); 135 integrate void clmpcc_channel_cmd __P((struct clmpcc_softc *,int,int)); 136 integrate void clmpcc_enable_transmitter __P((struct clmpcc_chan *)); 137 138 #define clmpcc_rd_msvr(s) clmpcc_rdreg_odd(s,CLMPCC_REG_MSVR) 139 #define clmpcc_wr_msvr(s,r,v) clmpcc_wrreg_odd(s,r,v) 140 #define clmpcc_wr_pilr(s,r,v) clmpcc_wrreg_odd(s,r,v) 141 #define clmpcc_rd_rxdata(s) clmpcc_rdreg_odd(s,CLMPCC_REG_RDR) 142 #define clmpcc_wr_txdata(s,v) clmpcc_wrreg_odd(s,CLMPCC_REG_TDR,v) 143 144 145 integrate u_int8_t 146 clmpcc_rdreg(sc, offset) 147 struct clmpcc_softc *sc; 148 u_int offset; 149 { 150 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH) 151 offset ^= sc->sc_byteswap; 152 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH) 153 offset ^= CLMPCC_BYTESWAP_HIGH; 154 #endif 155 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 156 } 157 158 integrate void 159 clmpcc_wrreg(sc, offset, val) 160 struct clmpcc_softc *sc; 161 u_int offset; 162 u_int val; 163 { 164 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH) 165 offset ^= sc->sc_byteswap; 166 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH) 167 offset ^= CLMPCC_BYTESWAP_HIGH; 168 #endif 169 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, val); 170 } 171 172 integrate u_int8_t 173 clmpcc_rdreg_odd(sc, offset) 174 struct clmpcc_softc *sc; 175 u_int offset; 176 { 177 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH) 178 offset ^= (sc->sc_byteswap & 2); 179 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH) 180 offset ^= (CLMPCC_BYTESWAP_HIGH & 2); 181 #endif 182 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 183 } 184 185 integrate void 186 clmpcc_wrreg_odd(sc, offset, val) 187 struct clmpcc_softc *sc; 188 u_int offset; 189 u_int val; 190 { 191 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH) 192 offset ^= (sc->sc_byteswap & 2); 193 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH) 194 offset ^= (CLMPCC_BYTESWAP_HIGH & 2); 195 #endif 196 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, val); 197 } 198 199 integrate void 200 clmpcc_wrtx_multi(sc, buff, count) 201 struct clmpcc_softc *sc; 202 u_int8_t *buff; 203 u_int count; 204 { 205 u_int offset = CLMPCC_REG_TDR; 206 207 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH) 208 offset ^= (sc->sc_byteswap & 2); 209 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH) 210 offset ^= (CLMPCC_BYTESWAP_HIGH & 2); 211 #endif 212 bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh, offset, buff, count); 213 } 214 215 integrate u_int8_t 216 clmpcc_select_channel(sc, new_chan) 217 struct clmpcc_softc *sc; 218 u_int new_chan; 219 { 220 u_int old_chan = clmpcc_rdreg_odd(sc, CLMPCC_REG_CAR); 221 222 clmpcc_wrreg_odd(sc, CLMPCC_REG_CAR, new_chan); 223 224 return old_chan; 225 } 226 227 integrate void 228 clmpcc_channel_cmd(sc, chan, cmd) 229 struct clmpcc_softc *sc; 230 int chan; 231 int cmd; 232 { 233 int i; 234 235 for (i = 5000; i; i--) { 236 if ( clmpcc_rdreg(sc, CLMPCC_REG_CCR) == 0 ) 237 break; 238 delay(1); 239 } 240 241 if ( i == 0 ) 242 printf("%s: channel %d command timeout (idle)\n", 243 sc->sc_dev.dv_xname, chan); 244 245 clmpcc_wrreg(sc, CLMPCC_REG_CCR, cmd); 246 } 247 248 integrate void 249 clmpcc_enable_transmitter(ch) 250 struct clmpcc_chan *ch; 251 { 252 u_int old; 253 int s; 254 255 old = clmpcc_select_channel(ch->ch_sc, ch->ch_car); 256 257 s = splserial(); 258 clmpcc_wrreg(ch->ch_sc, CLMPCC_REG_IER, 259 clmpcc_rdreg(ch->ch_sc, CLMPCC_REG_IER) | CLMPCC_IER_TX_EMPTY); 260 SET(ch->ch_tty->t_state, TS_BUSY); 261 splx(s); 262 263 clmpcc_select_channel(ch->ch_sc, old); 264 } 265 266 static int 267 clmpcc_speed(sc, speed, cor, bpr) 268 struct clmpcc_softc *sc; 269 speed_t speed; 270 int *cor, *bpr; 271 { 272 int c, co, br; 273 274 for (co = 0, c = 8; c <= 2048; co++, c *= 4) { 275 br = ((sc->sc_clk / c) / speed) - 1; 276 if ( br < 0x100 ) { 277 *cor = co; 278 *bpr = br; 279 return 0; 280 } 281 } 282 283 return -1; 284 } 285 286 void 287 clmpcc_attach(sc) 288 struct clmpcc_softc *sc; 289 { 290 struct clmpcc_chan *ch; 291 struct tty *tp; 292 int chan; 293 294 if ( cons_sc != NULL && 295 sc->sc_iot == cons_sc->sc_iot && sc->sc_ioh == cons_sc->sc_ioh ) 296 cons_sc = sc; 297 298 /* Initialise the chip */ 299 clmpcc_init(sc); 300 301 printf(": Cirrus Logic CD240%c Serial Controller\n", 302 (clmpcc_rd_msvr(sc) & CLMPCC_MSVR_PORT_ID) ? '0' : '1'); 303 304 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS 305 sc->sc_soft_running = 0; 306 #else 307 sc->sc_softintr_cookie = 308 softintr_establish(IPL_SOFTSERIAL, clmpcc_softintr, sc); 309 #ifdef DEBUG 310 if (sc->sc_softintr_cookie == NULL) 311 panic("clmpcc_attach: softintr_establish"); 312 #endif 313 #endif 314 memset(&(sc->sc_chans[0]), 0, sizeof(sc->sc_chans)); 315 316 for (chan = 0; chan < CLMPCC_NUM_CHANS; chan++) { 317 ch = &sc->sc_chans[chan]; 318 319 ch->ch_sc = sc; 320 ch->ch_car = chan; 321 322 tp = ttymalloc(); 323 tp->t_oproc = clmpcc_start; 324 tp->t_param = clmpcc_param; 325 326 ch->ch_tty = tp; 327 328 ch->ch_ibuf = malloc(clmpcc_ibuf_size * 2, M_DEVBUF, M_NOWAIT); 329 if ( ch->ch_ibuf == NULL ) { 330 printf("%s(%d): unable to allocate ring buffer\n", 331 sc->sc_dev.dv_xname, chan); 332 return; 333 } 334 335 ch->ch_ibuf_end = &(ch->ch_ibuf[clmpcc_ibuf_size * 2]); 336 ch->ch_ibuf_rd = ch->ch_ibuf_wr = ch->ch_ibuf; 337 338 tty_attach(tp); 339 } 340 341 printf("%s: %d channels available", sc->sc_dev.dv_xname, 342 CLMPCC_NUM_CHANS); 343 if ( cons_sc == sc ) { 344 printf(", console on channel %d.\n", cons_chan); 345 SET(sc->sc_chans[cons_chan].ch_flags, CLMPCC_FLG_IS_CONSOLE); 346 SET(sc->sc_chans[cons_chan].ch_openflags, TIOCFLAG_SOFTCAR); 347 } else 348 printf(".\n"); 349 } 350 351 static int 352 clmpcc_init(sc) 353 struct clmpcc_softc *sc; 354 { 355 u_int tcor, tbpr; 356 u_int rcor, rbpr; 357 u_int msvr_rts, msvr_dtr; 358 u_int ccr; 359 int is_console; 360 int i; 361 362 /* 363 * All we're really concerned about here is putting the chip 364 * into a quiescent state so that it won't do anything until 365 * clmpccopen() is called. (Except the console channel.) 366 */ 367 368 /* 369 * If the chip is acting as console, set all channels to the supplied 370 * console baud rate. Otherwise, plump for 9600. 371 */ 372 if ( cons_sc && 373 sc->sc_ioh == cons_sc->sc_ioh && sc->sc_iot == cons_sc->sc_iot ) { 374 clmpcc_speed(sc, cons_rate, &tcor, &tbpr); 375 clmpcc_speed(sc, cons_rate, &rcor, &rbpr); 376 is_console = 1; 377 } else { 378 clmpcc_speed(sc, 9600, &tcor, &tbpr); 379 clmpcc_speed(sc, 9600, &rcor, &rbpr); 380 is_console = 0; 381 } 382 383 /* Allow any pending output to be sent */ 384 delay(10000); 385 386 /* Send the Reset All command to channel 0 (resets all channels!) */ 387 clmpcc_channel_cmd(sc, 0, CLMPCC_CCR_T0_RESET_ALL); 388 389 delay(1000); 390 391 /* 392 * The chip will set it's firmware revision register to a non-zero 393 * value to indicate completion of reset. 394 */ 395 for (i = 10000; clmpcc_rdreg(sc, CLMPCC_REG_GFRCR) == 0 && i; i--) 396 delay(1); 397 398 if ( i == 0 ) { 399 /* 400 * Watch out... If this chip is console, the message 401 * probably won't be sent since we just reset it! 402 */ 403 printf("%s: Failed to reset chip\n", sc->sc_dev.dv_xname); 404 return -1; 405 } 406 407 for (i = 0; i < CLMPCC_NUM_CHANS; i++) { 408 clmpcc_select_channel(sc, i); 409 410 /* All interrupts are disabled to begin with */ 411 clmpcc_wrreg(sc, CLMPCC_REG_IER, 0); 412 413 /* Make sure the channel interrupts on the correct vectors */ 414 clmpcc_wrreg(sc, CLMPCC_REG_LIVR, sc->sc_vector_base); 415 clmpcc_wr_pilr(sc, CLMPCC_REG_RPILR, sc->sc_rpilr); 416 clmpcc_wr_pilr(sc, CLMPCC_REG_TPILR, sc->sc_tpilr); 417 clmpcc_wr_pilr(sc, CLMPCC_REG_MPILR, sc->sc_mpilr); 418 419 /* Receive timer prescaler set to 1ms */ 420 clmpcc_wrreg(sc, CLMPCC_REG_TPR, 421 CLMPCC_MSEC_TO_TPR(sc->sc_clk, 1)); 422 423 /* We support Async mode only */ 424 clmpcc_wrreg(sc, CLMPCC_REG_CMR, CLMPCC_CMR_ASYNC); 425 426 /* Set the required baud rate */ 427 clmpcc_wrreg(sc, CLMPCC_REG_TCOR, CLMPCC_TCOR_CLK(tcor)); 428 clmpcc_wrreg(sc, CLMPCC_REG_TBPR, tbpr); 429 clmpcc_wrreg(sc, CLMPCC_REG_RCOR, CLMPCC_RCOR_CLK(rcor)); 430 clmpcc_wrreg(sc, CLMPCC_REG_RBPR, rbpr); 431 432 /* Always default to 8N1 (XXX what about console?) */ 433 clmpcc_wrreg(sc, CLMPCC_REG_COR1, CLMPCC_COR1_CHAR_8BITS | 434 CLMPCC_COR1_NO_PARITY | 435 CLMPCC_COR1_IGNORE_PAR); 436 437 clmpcc_wrreg(sc, CLMPCC_REG_COR2, 0); 438 439 clmpcc_wrreg(sc, CLMPCC_REG_COR3, CLMPCC_COR3_STOP_1); 440 441 clmpcc_wrreg(sc, CLMPCC_REG_COR4, CLMPCC_COR4_DSRzd | 442 CLMPCC_COR4_CDzd | 443 CLMPCC_COR4_CTSzd); 444 445 clmpcc_wrreg(sc, CLMPCC_REG_COR5, CLMPCC_COR5_DSRod | 446 CLMPCC_COR5_CDod | 447 CLMPCC_COR5_CTSod | 448 CLMPCC_COR5_FLOW_NORM); 449 450 clmpcc_wrreg(sc, CLMPCC_REG_COR6, 0); 451 clmpcc_wrreg(sc, CLMPCC_REG_COR7, 0); 452 453 /* Set the receive FIFO timeout */ 454 clmpcc_wrreg(sc, CLMPCC_REG_RTPRl, CLMPCC_RTPR_DEFAULT); 455 clmpcc_wrreg(sc, CLMPCC_REG_RTPRh, 0); 456 457 /* At this point, we set up the console differently */ 458 if ( is_console && i == cons_chan ) { 459 msvr_rts = CLMPCC_MSVR_RTS; 460 msvr_dtr = CLMPCC_MSVR_DTR; 461 ccr = CLMPCC_CCR_T0_RX_EN | CLMPCC_CCR_T0_TX_EN; 462 } else { 463 msvr_rts = 0; 464 msvr_dtr = 0; 465 ccr = CLMPCC_CCR_T0_RX_DIS | CLMPCC_CCR_T0_TX_DIS; 466 } 467 468 clmpcc_wrreg(sc, CLMPCC_REG_MSVR_RTS, msvr_rts); 469 clmpcc_wrreg(sc, CLMPCC_REG_MSVR_DTR, msvr_dtr); 470 clmpcc_channel_cmd(sc, i, CLMPCC_CCR_T0_INIT | ccr); 471 delay(100); 472 } 473 474 return 0; 475 } 476 477 static void 478 clmpcc_shutdown(ch) 479 struct clmpcc_chan *ch; 480 { 481 int oldch; 482 483 oldch = clmpcc_select_channel(ch->ch_sc, ch->ch_car); 484 485 /* Turn off interrupts. */ 486 clmpcc_wrreg(ch->ch_sc, CLMPCC_REG_IER, 0); 487 488 if ( ISCLR(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) ) { 489 /* Disable the transmitter and receiver */ 490 clmpcc_channel_cmd(ch->ch_sc, ch->ch_car, CLMPCC_CCR_T0_RX_DIS | 491 CLMPCC_CCR_T0_TX_DIS); 492 493 /* Drop RTS and DTR */ 494 clmpcc_modem_control(ch, TIOCM_RTS | TIOCM_DTR, DMBIS); 495 } 496 497 clmpcc_select_channel(ch->ch_sc, oldch); 498 } 499 500 int 501 clmpccopen(dev, flag, mode, p) 502 dev_t dev; 503 int flag, mode; 504 struct proc *p; 505 { 506 struct clmpcc_softc *sc; 507 struct clmpcc_chan *ch; 508 struct tty *tp; 509 int oldch; 510 int error; 511 512 sc = device_lookup(&clmpcc_cd, CLMPCCUNIT(dev)); 513 if (sc == NULL) 514 return (ENXIO); 515 516 ch = &sc->sc_chans[CLMPCCCHAN(dev)]; 517 518 tp = ch->ch_tty; 519 520 if ( ISSET(tp->t_state, TS_ISOPEN) && 521 ISSET(tp->t_state, TS_XCLUDE) && p->p_ucred->cr_uid != 0 ) 522 return EBUSY; 523 524 /* 525 * Do the following iff this is a first open. 526 */ 527 if ( ISCLR(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0 ) { 528 529 ttychars(tp); 530 531 tp->t_dev = dev; 532 tp->t_iflag = TTYDEF_IFLAG; 533 tp->t_oflag = TTYDEF_OFLAG; 534 tp->t_lflag = TTYDEF_LFLAG; 535 tp->t_cflag = TTYDEF_CFLAG; 536 tp->t_ospeed = tp->t_ispeed = TTYDEF_SPEED; 537 538 if ( ISSET(ch->ch_openflags, TIOCFLAG_CLOCAL) ) 539 SET(tp->t_cflag, CLOCAL); 540 if ( ISSET(ch->ch_openflags, TIOCFLAG_CRTSCTS) ) 541 SET(tp->t_cflag, CRTSCTS); 542 if ( ISSET(ch->ch_openflags, TIOCFLAG_MDMBUF) ) 543 SET(tp->t_cflag, MDMBUF); 544 545 /* 546 * Override some settings if the channel is being 547 * used as the console. 548 */ 549 if ( ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) ) { 550 tp->t_ospeed = tp->t_ispeed = cons_rate; 551 SET(tp->t_cflag, CLOCAL); 552 CLR(tp->t_cflag, CRTSCTS); 553 CLR(tp->t_cflag, HUPCL); 554 } 555 556 ch->ch_control = 0; 557 558 clmpcc_param(tp, &tp->t_termios); 559 ttsetwater(tp); 560 561 /* Clear the input ring */ 562 ch->ch_ibuf_rd = ch->ch_ibuf_wr = ch->ch_ibuf; 563 564 /* Select the channel */ 565 oldch = clmpcc_select_channel(sc, ch->ch_car); 566 567 /* Reset it */ 568 clmpcc_channel_cmd(sc, ch->ch_car, CLMPCC_CCR_T0_CLEAR | 569 CLMPCC_CCR_T0_RX_EN | 570 CLMPCC_CCR_T0_TX_EN); 571 572 /* Enable receiver and modem change interrupts. */ 573 clmpcc_wrreg(sc, CLMPCC_REG_IER, CLMPCC_IER_MODEM | 574 CLMPCC_IER_RET | 575 CLMPCC_IER_RX_FIFO); 576 577 /* Raise RTS and DTR */ 578 clmpcc_modem_control(ch, TIOCM_RTS | TIOCM_DTR, DMBIS); 579 580 clmpcc_select_channel(sc, oldch); 581 } else 582 if ( ISSET(tp->t_state, TS_XCLUDE) && p->p_ucred->cr_uid != 0 ) 583 return EBUSY; 584 585 error = ttyopen(tp, CLMPCCDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 586 if (error) 587 goto bad; 588 589 error = (*tp->t_linesw->l_open)(dev, tp); 590 if (error) 591 goto bad; 592 593 return 0; 594 595 bad: 596 if ( ISCLR(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0 ) { 597 /* 598 * We failed to open the device, and nobody else had it opened. 599 * Clean up the state as appropriate. 600 */ 601 clmpcc_shutdown(ch); 602 } 603 604 return error; 605 } 606 607 int 608 clmpccclose(dev, flag, mode, p) 609 dev_t dev; 610 int flag, mode; 611 struct proc *p; 612 { 613 struct clmpcc_softc *sc = 614 device_lookup(&clmpcc_cd, CLMPCCUNIT(dev)); 615 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(dev)]; 616 struct tty *tp = ch->ch_tty; 617 int s; 618 619 if ( ISCLR(tp->t_state, TS_ISOPEN) ) 620 return 0; 621 622 (*tp->t_linesw->l_close)(tp, flag); 623 624 s = spltty(); 625 626 if ( ISCLR(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0 ) { 627 /* 628 * Although we got a last close, the device may still be in 629 * use; e.g. if this was the dialout node, and there are still 630 * processes waiting for carrier on the non-dialout node. 631 */ 632 clmpcc_shutdown(ch); 633 } 634 635 ttyclose(tp); 636 637 splx(s); 638 639 return 0; 640 } 641 642 int 643 clmpccread(dev, uio, flag) 644 dev_t dev; 645 struct uio *uio; 646 int flag; 647 { 648 struct clmpcc_softc *sc = device_lookup(&clmpcc_cd, CLMPCCUNIT(dev)); 649 struct tty *tp = sc->sc_chans[CLMPCCCHAN(dev)].ch_tty; 650 651 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 652 } 653 654 int 655 clmpccwrite(dev, uio, flag) 656 dev_t dev; 657 struct uio *uio; 658 int flag; 659 { 660 struct clmpcc_softc *sc = device_lookup(&clmpcc_cd, CLMPCCUNIT(dev)); 661 struct tty *tp = sc->sc_chans[CLMPCCCHAN(dev)].ch_tty; 662 663 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 664 } 665 666 int 667 clmpccpoll(dev, events, p) 668 dev_t dev; 669 int events; 670 struct proc *p; 671 { 672 struct clmpcc_softc *sc = device_lookup(&clmpcc_cd, CLMPCCUNIT(dev)); 673 struct tty *tp = sc->sc_chans[CLMPCCCHAN(dev)].ch_tty; 674 675 return ((*tp->t_linesw->l_poll)(tp, events, p)); 676 } 677 678 struct tty * 679 clmpcctty(dev) 680 dev_t dev; 681 { 682 struct clmpcc_softc *sc = device_lookup(&clmpcc_cd, CLMPCCUNIT(dev)); 683 684 return (sc->sc_chans[CLMPCCCHAN(dev)].ch_tty); 685 } 686 687 int 688 clmpccioctl(dev, cmd, data, flag, p) 689 dev_t dev; 690 u_long cmd; 691 caddr_t data; 692 int flag; 693 struct proc *p; 694 { 695 struct clmpcc_softc *sc = device_lookup(&clmpcc_cd, CLMPCCUNIT(dev)); 696 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(dev)]; 697 struct tty *tp = ch->ch_tty; 698 int error; 699 700 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, p); 701 if (error != EPASSTHROUGH) 702 return error; 703 704 error = ttioctl(tp, cmd, data, flag, p); 705 if (error != EPASSTHROUGH) 706 return error; 707 708 error = 0; 709 710 switch (cmd) { 711 case TIOCSBRK: 712 SET(ch->ch_flags, CLMPCC_FLG_START_BREAK); 713 clmpcc_enable_transmitter(ch); 714 break; 715 716 case TIOCCBRK: 717 SET(ch->ch_flags, CLMPCC_FLG_END_BREAK); 718 clmpcc_enable_transmitter(ch); 719 break; 720 721 case TIOCSDTR: 722 clmpcc_modem_control(ch, TIOCM_DTR, DMBIS); 723 break; 724 725 case TIOCCDTR: 726 clmpcc_modem_control(ch, TIOCM_DTR, DMBIC); 727 break; 728 729 case TIOCMSET: 730 clmpcc_modem_control(ch, *((int *)data), DMSET); 731 break; 732 733 case TIOCMBIS: 734 clmpcc_modem_control(ch, *((int *)data), DMBIS); 735 break; 736 737 case TIOCMBIC: 738 clmpcc_modem_control(ch, *((int *)data), DMBIC); 739 break; 740 741 case TIOCMGET: 742 *((int *)data) = clmpcc_modem_control(ch, 0, DMGET); 743 break; 744 745 case TIOCGFLAGS: 746 *((int *)data) = ch->ch_openflags; 747 break; 748 749 case TIOCSFLAGS: 750 error = suser(p->p_ucred, &p->p_acflag); 751 if ( error ) 752 break; 753 ch->ch_openflags = *((int *)data) & 754 (TIOCFLAG_SOFTCAR | TIOCFLAG_CLOCAL | 755 TIOCFLAG_CRTSCTS | TIOCFLAG_MDMBUF); 756 if ( ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) ) 757 SET(ch->ch_openflags, TIOCFLAG_SOFTCAR); 758 break; 759 760 default: 761 error = EPASSTHROUGH; 762 break; 763 } 764 765 return error; 766 } 767 768 int 769 clmpcc_modem_control(ch, bits, howto) 770 struct clmpcc_chan *ch; 771 int bits; 772 int howto; 773 { 774 struct clmpcc_softc *sc = ch->ch_sc; 775 struct tty *tp = ch->ch_tty; 776 int oldch; 777 int msvr; 778 int rbits = 0; 779 780 oldch = clmpcc_select_channel(sc, ch->ch_car); 781 782 switch ( howto ) { 783 case DMGET: 784 msvr = clmpcc_rd_msvr(sc); 785 786 if ( sc->sc_swaprtsdtr ) { 787 rbits |= (msvr & CLMPCC_MSVR_RTS) ? TIOCM_DTR : 0; 788 rbits |= (msvr & CLMPCC_MSVR_DTR) ? TIOCM_RTS : 0; 789 } else { 790 rbits |= (msvr & CLMPCC_MSVR_RTS) ? TIOCM_RTS : 0; 791 rbits |= (msvr & CLMPCC_MSVR_DTR) ? TIOCM_DTR : 0; 792 } 793 794 rbits |= (msvr & CLMPCC_MSVR_CTS) ? TIOCM_CTS : 0; 795 rbits |= (msvr & CLMPCC_MSVR_CD) ? TIOCM_CD : 0; 796 rbits |= (msvr & CLMPCC_MSVR_DSR) ? TIOCM_DSR : 0; 797 break; 798 799 case DMSET: 800 if ( sc->sc_swaprtsdtr ) { 801 if ( ISCLR(tp->t_cflag, CRTSCTS) ) 802 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR, 803 bits & TIOCM_RTS ? CLMPCC_MSVR_DTR : 0); 804 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS, 805 bits & TIOCM_DTR ? CLMPCC_MSVR_RTS : 0); 806 } else { 807 if ( ISCLR(tp->t_cflag, CRTSCTS) ) 808 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS, 809 bits & TIOCM_RTS ? CLMPCC_MSVR_RTS : 0); 810 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR, 811 bits & TIOCM_DTR ? CLMPCC_MSVR_DTR : 0); 812 } 813 break; 814 815 case DMBIS: 816 if ( sc->sc_swaprtsdtr ) { 817 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISSET(bits, TIOCM_RTS) ) 818 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_DTR, CLMPCC_MSVR_DTR); 819 if ( ISSET(bits, TIOCM_DTR) ) 820 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_RTS, CLMPCC_MSVR_RTS); 821 } else { 822 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISSET(bits, TIOCM_RTS) ) 823 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_RTS, CLMPCC_MSVR_RTS); 824 if ( ISSET(bits, TIOCM_DTR) ) 825 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_DTR, CLMPCC_MSVR_DTR); 826 } 827 break; 828 829 case DMBIC: 830 if ( sc->sc_swaprtsdtr ) { 831 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISCLR(bits, TIOCM_RTS) ) 832 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR, 0); 833 if ( ISCLR(bits, TIOCM_DTR) ) 834 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS, 0); 835 } else { 836 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISCLR(bits, TIOCM_RTS) ) 837 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS, 0); 838 if ( ISCLR(bits, TIOCM_DTR) ) 839 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR, 0); 840 } 841 break; 842 } 843 844 clmpcc_select_channel(sc, oldch); 845 846 return rbits; 847 } 848 849 static int 850 clmpcc_param(tp, t) 851 struct tty *tp; 852 struct termios *t; 853 { 854 struct clmpcc_softc *sc = 855 device_lookup(&clmpcc_cd, CLMPCCUNIT(tp->t_dev)); 856 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(tp->t_dev)]; 857 u_char cor; 858 u_char oldch; 859 int oclk, obpr; 860 int iclk, ibpr; 861 int s; 862 863 /* Check requested parameters. */ 864 if ( t->c_ospeed && clmpcc_speed(sc, t->c_ospeed, &oclk, &obpr) < 0 ) 865 return EINVAL; 866 867 if ( t->c_ispeed && clmpcc_speed(sc, t->c_ispeed, &iclk, &ibpr) < 0 ) 868 return EINVAL; 869 870 /* 871 * For the console, always force CLOCAL and !HUPCL, so that the port 872 * is always active. 873 */ 874 if ( ISSET(ch->ch_openflags, TIOCFLAG_SOFTCAR) || 875 ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) ) { 876 SET(t->c_cflag, CLOCAL); 877 CLR(t->c_cflag, HUPCL); 878 } 879 880 CLR(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS); 881 882 /* If ospeed it zero, hangup the line */ 883 clmpcc_modem_control(ch, TIOCM_DTR, t->c_ospeed == 0 ? DMBIC : DMBIS); 884 885 if ( t->c_ospeed ) { 886 ch->ch_tcor = CLMPCC_TCOR_CLK(oclk); 887 ch->ch_tbpr = obpr; 888 } else { 889 ch->ch_tcor = 0; 890 ch->ch_tbpr = 0; 891 } 892 893 if ( t->c_ispeed ) { 894 ch->ch_rcor = CLMPCC_RCOR_CLK(iclk); 895 ch->ch_rbpr = ibpr; 896 } else { 897 ch->ch_rcor = 0; 898 ch->ch_rbpr = 0; 899 } 900 901 /* Work out value to use for COR1 */ 902 cor = 0; 903 if ( ISSET(t->c_cflag, PARENB) ) { 904 cor |= CLMPCC_COR1_NORM_PARITY; 905 if ( ISSET(t->c_cflag, PARODD) ) 906 cor |= CLMPCC_COR1_ODD_PARITY; 907 } 908 909 if ( ISCLR(t->c_cflag, INPCK) ) 910 cor |= CLMPCC_COR1_IGNORE_PAR; 911 912 switch ( t->c_cflag & CSIZE ) { 913 case CS5: 914 cor |= CLMPCC_COR1_CHAR_5BITS; 915 break; 916 917 case CS6: 918 cor |= CLMPCC_COR1_CHAR_6BITS; 919 break; 920 921 case CS7: 922 cor |= CLMPCC_COR1_CHAR_7BITS; 923 break; 924 925 case CS8: 926 cor |= CLMPCC_COR1_CHAR_8BITS; 927 break; 928 } 929 930 ch->ch_cor1 = cor; 931 932 /* 933 * The only interesting bit in COR2 is 'CTS Automatic Enable' 934 * when hardware flow control is in effect. 935 */ 936 ch->ch_cor2 = ISSET(t->c_cflag, CRTSCTS) ? CLMPCC_COR2_CtsAE : 0; 937 938 /* COR3 needs to be set to the number of stop bits... */ 939 ch->ch_cor3 = ISSET(t->c_cflag, CSTOPB) ? CLMPCC_COR3_STOP_2 : 940 CLMPCC_COR3_STOP_1; 941 942 /* 943 * COR4 contains the FIFO threshold setting. 944 * We adjust the threshold depending on the input speed... 945 */ 946 if ( t->c_ispeed <= 1200 ) 947 ch->ch_cor4 = CLMPCC_COR4_FIFO_LOW; 948 else if ( t->c_ispeed <= 19200 ) 949 ch->ch_cor4 = CLMPCC_COR4_FIFO_MED; 950 else 951 ch->ch_cor4 = CLMPCC_COR4_FIFO_HIGH; 952 953 /* 954 * If chip is used with CTS and DTR swapped, we can enable 955 * automatic hardware flow control. 956 */ 957 if ( sc->sc_swaprtsdtr && ISSET(t->c_cflag, CRTSCTS) ) 958 ch->ch_cor5 = CLMPCC_COR5_FLOW_NORM; 959 else 960 ch->ch_cor5 = 0; 961 962 s = splserial(); 963 oldch = clmpcc_select_channel(sc, ch->ch_car); 964 965 /* 966 * COR2 needs to be set immediately otherwise we might never get 967 * a Tx EMPTY interrupt to change the other parameters. 968 */ 969 if ( clmpcc_rdreg(sc, CLMPCC_REG_COR2) != ch->ch_cor2 ) 970 clmpcc_wrreg(sc, CLMPCC_REG_COR2, ch->ch_cor2); 971 972 if ( ISCLR(ch->ch_tty->t_state, TS_BUSY) ) 973 clmpcc_set_params(ch); 974 else 975 SET(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS); 976 977 clmpcc_select_channel(sc, oldch); 978 979 splx(s); 980 981 return 0; 982 } 983 984 static void 985 clmpcc_set_params(ch) 986 struct clmpcc_chan *ch; 987 { 988 struct clmpcc_softc *sc = ch->ch_sc; 989 u_char r1; 990 u_char r2; 991 992 if ( ch->ch_tcor || ch->ch_tbpr ) { 993 r1 = clmpcc_rdreg(sc, CLMPCC_REG_TCOR); 994 r2 = clmpcc_rdreg(sc, CLMPCC_REG_TBPR); 995 /* Only write Tx rate if it really has changed */ 996 if ( ch->ch_tcor != r1 || ch->ch_tbpr != r2 ) { 997 clmpcc_wrreg(sc, CLMPCC_REG_TCOR, ch->ch_tcor); 998 clmpcc_wrreg(sc, CLMPCC_REG_TBPR, ch->ch_tbpr); 999 } 1000 } 1001 1002 if ( ch->ch_rcor || ch->ch_rbpr ) { 1003 r1 = clmpcc_rdreg(sc, CLMPCC_REG_RCOR); 1004 r2 = clmpcc_rdreg(sc, CLMPCC_REG_RBPR); 1005 /* Only write Rx rate if it really has changed */ 1006 if ( ch->ch_rcor != r1 || ch->ch_rbpr != r2 ) { 1007 clmpcc_wrreg(sc, CLMPCC_REG_RCOR, ch->ch_rcor); 1008 clmpcc_wrreg(sc, CLMPCC_REG_RBPR, ch->ch_rbpr); 1009 } 1010 } 1011 1012 if ( clmpcc_rdreg(sc, CLMPCC_REG_COR1) != ch->ch_cor1 ) { 1013 clmpcc_wrreg(sc, CLMPCC_REG_COR1, ch->ch_cor1); 1014 /* Any change to COR1 requires an INIT command */ 1015 SET(ch->ch_flags, CLMPCC_FLG_NEED_INIT); 1016 } 1017 1018 if ( clmpcc_rdreg(sc, CLMPCC_REG_COR3) != ch->ch_cor3 ) 1019 clmpcc_wrreg(sc, CLMPCC_REG_COR3, ch->ch_cor3); 1020 1021 r1 = clmpcc_rdreg(sc, CLMPCC_REG_COR4); 1022 if ( ch->ch_cor4 != (r1 & CLMPCC_COR4_FIFO_MASK) ) { 1023 /* 1024 * Note: If the FIFO has changed, we always set it to 1025 * zero here and disable the Receive Timeout interrupt. 1026 * It's up to the Rx Interrupt handler to pick the 1027 * appropriate moment to write the new FIFO length. 1028 */ 1029 clmpcc_wrreg(sc, CLMPCC_REG_COR4, r1 & ~CLMPCC_COR4_FIFO_MASK); 1030 r1 = clmpcc_rdreg(sc, CLMPCC_REG_IER); 1031 clmpcc_wrreg(sc, CLMPCC_REG_IER, r1 & ~CLMPCC_IER_RET); 1032 SET(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR); 1033 } 1034 1035 r1 = clmpcc_rdreg(sc, CLMPCC_REG_COR5); 1036 if ( ch->ch_cor5 != (r1 & CLMPCC_COR5_FLOW_MASK) ) { 1037 r1 &= ~CLMPCC_COR5_FLOW_MASK; 1038 clmpcc_wrreg(sc, CLMPCC_REG_COR5, r1 | ch->ch_cor5); 1039 } 1040 } 1041 1042 static void 1043 clmpcc_start(tp) 1044 struct tty *tp; 1045 { 1046 struct clmpcc_softc *sc = 1047 device_lookup(&clmpcc_cd, CLMPCCUNIT(tp->t_dev)); 1048 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(tp->t_dev)]; 1049 u_int oldch; 1050 int s; 1051 1052 s = spltty(); 1053 1054 if ( ISCLR(tp->t_state, TS_TTSTOP | TS_TIMEOUT | TS_BUSY) ) { 1055 if ( tp->t_outq.c_cc <= tp->t_lowat ) { 1056 if ( ISSET(tp->t_state, TS_ASLEEP) ) { 1057 CLR(tp->t_state, TS_ASLEEP); 1058 wakeup(&tp->t_outq); 1059 } 1060 selwakeup(&tp->t_wsel); 1061 } 1062 1063 if ( ISSET(ch->ch_flags, CLMPCC_FLG_START_BREAK | 1064 CLMPCC_FLG_END_BREAK) || 1065 tp->t_outq.c_cc > 0 ) { 1066 1067 if ( ISCLR(ch->ch_flags, CLMPCC_FLG_START_BREAK | 1068 CLMPCC_FLG_END_BREAK) ) { 1069 ch->ch_obuf_addr = tp->t_outq.c_cf; 1070 ch->ch_obuf_size = ndqb(&tp->t_outq, 0); 1071 } 1072 1073 /* Enable TX empty interrupts */ 1074 oldch = clmpcc_select_channel(ch->ch_sc, ch->ch_car); 1075 clmpcc_wrreg(ch->ch_sc, CLMPCC_REG_IER, 1076 clmpcc_rdreg(ch->ch_sc, CLMPCC_REG_IER) | 1077 CLMPCC_IER_TX_EMPTY); 1078 clmpcc_select_channel(ch->ch_sc, oldch); 1079 SET(tp->t_state, TS_BUSY); 1080 } 1081 } 1082 1083 splx(s); 1084 } 1085 1086 /* 1087 * Stop output on a line. 1088 */ 1089 void 1090 clmpccstop(tp, flag) 1091 struct tty *tp; 1092 int flag; 1093 { 1094 struct clmpcc_softc *sc = 1095 device_lookup(&clmpcc_cd, CLMPCCUNIT(tp->t_dev)); 1096 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(tp->t_dev)]; 1097 int s; 1098 1099 s = splserial(); 1100 1101 if ( ISSET(tp->t_state, TS_BUSY) ) { 1102 if ( ISCLR(tp->t_state, TS_TTSTOP) ) 1103 SET(tp->t_state, TS_FLUSH); 1104 ch->ch_obuf_size = 0; 1105 } 1106 splx(s); 1107 } 1108 1109 /* 1110 * RX interrupt routine 1111 */ 1112 int 1113 clmpcc_rxintr(arg) 1114 void *arg; 1115 { 1116 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg; 1117 struct clmpcc_chan *ch; 1118 u_int8_t *put, *end, rxd; 1119 u_char errstat; 1120 u_char fc, tc; 1121 u_char risr; 1122 u_char rir; 1123 #ifdef DDB 1124 int saw_break = 0; 1125 #endif 1126 1127 /* Receive interrupt active? */ 1128 rir = clmpcc_rdreg(sc, CLMPCC_REG_RIR); 1129 1130 /* 1131 * If we're using auto-vectored interrupts, we have to 1132 * verify if the chip is generating the interrupt. 1133 */ 1134 if ( sc->sc_vector_base == 0 && (rir & CLMPCC_RIR_RACT) == 0 ) 1135 return 0; 1136 1137 /* Get pointer to interrupting channel's data structure */ 1138 ch = &sc->sc_chans[rir & CLMPCC_RIR_RCN_MASK]; 1139 1140 /* Get the interrupt status register */ 1141 risr = clmpcc_rdreg(sc, CLMPCC_REG_RISRl); 1142 if ( risr & CLMPCC_RISR_TIMEOUT ) { 1143 u_char reg; 1144 /* 1145 * Set the FIFO threshold to zero, and disable 1146 * further receive timeout interrupts. 1147 */ 1148 reg = clmpcc_rdreg(sc, CLMPCC_REG_COR4); 1149 clmpcc_wrreg(sc, CLMPCC_REG_COR4, reg & ~CLMPCC_COR4_FIFO_MASK); 1150 reg = clmpcc_rdreg(sc, CLMPCC_REG_IER); 1151 clmpcc_wrreg(sc, CLMPCC_REG_IER, reg & ~CLMPCC_IER_RET); 1152 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, CLMPCC_REOIR_NO_TRANS); 1153 SET(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR); 1154 return 1; 1155 } 1156 1157 /* How many bytes are waiting in the FIFO? */ 1158 fc = tc = clmpcc_rdreg(sc, CLMPCC_REG_RFOC) & CLMPCC_RFOC_MASK; 1159 1160 #ifdef DDB 1161 /* 1162 * Allow BREAK on the console to drop to the debugger. 1163 */ 1164 if ( ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) && 1165 risr & CLMPCC_RISR_BREAK ) { 1166 saw_break = 1; 1167 } 1168 #endif 1169 1170 if ( ISCLR(ch->ch_tty->t_state, TS_ISOPEN) && fc ) { 1171 /* Just get rid of the data */ 1172 while ( fc-- ) 1173 (void) clmpcc_rd_rxdata(sc); 1174 goto rx_done; 1175 } 1176 1177 put = ch->ch_ibuf_wr; 1178 end = ch->ch_ibuf_end; 1179 1180 /* 1181 * Note: The chip is completely hosed WRT these error 1182 * conditions; there seems to be no way to associate 1183 * the error with the correct character in the FIFO. 1184 * We compromise by tagging the first character we read 1185 * with the error. Not perfect, but there's no other way. 1186 */ 1187 errstat = 0; 1188 if ( risr & CLMPCC_RISR_PARITY ) 1189 errstat |= TTY_PE; 1190 if ( risr & (CLMPCC_RISR_FRAMING | CLMPCC_RISR_BREAK) ) 1191 errstat |= TTY_FE; 1192 1193 /* 1194 * As long as there are characters in the FIFO, and we 1195 * have space for them... 1196 */ 1197 while ( fc > 0 ) { 1198 1199 *put++ = rxd = clmpcc_rd_rxdata(sc); 1200 *put++ = errstat; 1201 1202 if ( put >= end ) 1203 put = ch->ch_ibuf; 1204 1205 if ( put == ch->ch_ibuf_rd ) { 1206 put -= 2; 1207 if ( put < ch->ch_ibuf ) 1208 put = end - 2; 1209 } 1210 1211 errstat = 0; 1212 fc--; 1213 } 1214 1215 ch->ch_ibuf_wr = put; 1216 1217 #if 0 1218 if ( sc->sc_swaprtsdtr == 0 && 1219 ISSET(cy->cy_tty->t_cflag, CRTSCTS) && cc < ch->ch_r_hiwat) { 1220 /* 1221 * If RTS/DTR are not physically swapped, we have to 1222 * do hardware flow control manually 1223 */ 1224 clmpcc_wr_msvr(sc, CLMPCC_MSVR_RTS, 0); 1225 } 1226 #endif 1227 1228 rx_done: 1229 if ( fc != tc ) { 1230 if ( ISSET(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR) ) { 1231 u_char reg; 1232 /* 1233 * Set the FIFO threshold to the preset value, 1234 * and enable receive timeout interrupts. 1235 */ 1236 reg = clmpcc_rdreg(sc, CLMPCC_REG_COR4); 1237 reg = (reg & ~CLMPCC_COR4_FIFO_MASK) | ch->ch_cor4; 1238 clmpcc_wrreg(sc, CLMPCC_REG_COR4, reg); 1239 reg = clmpcc_rdreg(sc, CLMPCC_REG_IER); 1240 clmpcc_wrreg(sc, CLMPCC_REG_IER, reg | CLMPCC_IER_RET); 1241 CLR(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR); 1242 } 1243 1244 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, 0); 1245 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS 1246 if ( sc->sc_soft_running == 0 ) { 1247 sc->sc_soft_running = 1; 1248 (sc->sc_softhook)(sc); 1249 } 1250 #else 1251 softintr_schedule(sc->sc_softintr_cookie); 1252 #endif 1253 } else 1254 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, CLMPCC_REOIR_NO_TRANS); 1255 1256 #ifdef DDB 1257 /* 1258 * Only =after= we write REOIR is it safe to drop to the debugger. 1259 */ 1260 if ( saw_break ) 1261 Debugger(); 1262 #endif 1263 1264 return 1; 1265 } 1266 1267 /* 1268 * Tx interrupt routine 1269 */ 1270 int 1271 clmpcc_txintr(arg) 1272 void *arg; 1273 { 1274 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg; 1275 struct clmpcc_chan *ch; 1276 struct tty *tp; 1277 u_char ftc, oftc; 1278 u_char tir, teoir; 1279 int etcmode = 0; 1280 1281 /* Tx interrupt active? */ 1282 tir = clmpcc_rdreg(sc, CLMPCC_REG_TIR); 1283 1284 /* 1285 * If we're using auto-vectored interrupts, we have to 1286 * verify if the chip is generating the interrupt. 1287 */ 1288 if ( sc->sc_vector_base == 0 && (tir & CLMPCC_TIR_TACT) == 0 ) 1289 return 0; 1290 1291 /* Get pointer to interrupting channel's data structure */ 1292 ch = &sc->sc_chans[tir & CLMPCC_TIR_TCN_MASK]; 1293 tp = ch->ch_tty; 1294 1295 /* Dummy read of the interrupt status register */ 1296 (void) clmpcc_rdreg(sc, CLMPCC_REG_TISR); 1297 1298 /* Make sure embedded transmit commands are disabled */ 1299 clmpcc_wrreg(sc, CLMPCC_REG_COR2, ch->ch_cor2); 1300 1301 ftc = oftc = clmpcc_rdreg(sc, CLMPCC_REG_TFTC); 1302 1303 /* Handle a delayed parameter change */ 1304 if ( ISSET(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS) ) { 1305 CLR(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS); 1306 clmpcc_set_params(ch); 1307 } 1308 1309 if ( ch->ch_obuf_size > 0 ) { 1310 u_int n = min(ch->ch_obuf_size, ftc); 1311 1312 clmpcc_wrtx_multi(sc, ch->ch_obuf_addr, n); 1313 1314 ftc -= n; 1315 ch->ch_obuf_size -= n; 1316 ch->ch_obuf_addr += n; 1317 1318 } else { 1319 /* 1320 * Check if we should start/stop a break 1321 */ 1322 if ( ISSET(ch->ch_flags, CLMPCC_FLG_START_BREAK) ) { 1323 CLR(ch->ch_flags, CLMPCC_FLG_START_BREAK); 1324 /* Enable embedded transmit commands */ 1325 clmpcc_wrreg(sc, CLMPCC_REG_COR2, 1326 ch->ch_cor2 | CLMPCC_COR2_ETC); 1327 clmpcc_wr_txdata(sc, CLMPCC_ETC_MAGIC); 1328 clmpcc_wr_txdata(sc, CLMPCC_ETC_SEND_BREAK); 1329 ftc -= 2; 1330 etcmode = 1; 1331 } 1332 1333 if ( ISSET(ch->ch_flags, CLMPCC_FLG_END_BREAK) ) { 1334 CLR(ch->ch_flags, CLMPCC_FLG_END_BREAK); 1335 /* Enable embedded transmit commands */ 1336 clmpcc_wrreg(sc, CLMPCC_REG_COR2, 1337 ch->ch_cor2 | CLMPCC_COR2_ETC); 1338 clmpcc_wr_txdata(sc, CLMPCC_ETC_MAGIC); 1339 clmpcc_wr_txdata(sc, CLMPCC_ETC_STOP_BREAK); 1340 ftc -= 2; 1341 etcmode = 1; 1342 } 1343 } 1344 1345 tir = clmpcc_rdreg(sc, CLMPCC_REG_IER); 1346 1347 if ( ftc != oftc ) { 1348 /* 1349 * Enable/disable the Tx FIFO threshold interrupt 1350 * according to how much data is in the FIFO. 1351 * However, always disable the FIFO threshold if 1352 * we've left the channel in 'Embedded Transmit 1353 * Command' mode. 1354 */ 1355 if ( etcmode || ftc >= ch->ch_cor4 ) 1356 tir &= ~CLMPCC_IER_TX_FIFO; 1357 else 1358 tir |= CLMPCC_IER_TX_FIFO; 1359 teoir = 0; 1360 } else { 1361 /* 1362 * No data was sent. 1363 * Disable transmit interrupt. 1364 */ 1365 tir &= ~(CLMPCC_IER_TX_EMPTY|CLMPCC_IER_TX_FIFO); 1366 teoir = CLMPCC_TEOIR_NO_TRANS; 1367 1368 /* 1369 * Request Tx processing in the soft interrupt handler 1370 */ 1371 ch->ch_tx_done = 1; 1372 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS 1373 if ( sc->sc_soft_running == 0 ) { 1374 sc->sc_soft_running = 1; 1375 (sc->sc_softhook)(sc); 1376 } 1377 #else 1378 softintr_schedule(sc->sc_softintr_cookie); 1379 #endif 1380 } 1381 1382 clmpcc_wrreg(sc, CLMPCC_REG_IER, tir); 1383 clmpcc_wrreg(sc, CLMPCC_REG_TEOIR, teoir); 1384 1385 return 1; 1386 } 1387 1388 /* 1389 * Modem change interrupt routine 1390 */ 1391 int 1392 clmpcc_mdintr(arg) 1393 void *arg; 1394 { 1395 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg; 1396 u_char mir; 1397 1398 /* Modem status interrupt active? */ 1399 mir = clmpcc_rdreg(sc, CLMPCC_REG_MIR); 1400 1401 /* 1402 * If we're using auto-vectored interrupts, we have to 1403 * verify if the chip is generating the interrupt. 1404 */ 1405 if ( sc->sc_vector_base == 0 && (mir & CLMPCC_MIR_MACT) == 0 ) 1406 return 0; 1407 1408 /* Dummy read of the interrupt status register */ 1409 (void) clmpcc_rdreg(sc, CLMPCC_REG_MISR); 1410 1411 /* Retrieve current status of modem lines. */ 1412 sc->sc_chans[mir & CLMPCC_MIR_MCN_MASK].ch_control |= 1413 clmpcc_rd_msvr(sc) & CLMPCC_MSVR_CD; 1414 1415 clmpcc_wrreg(sc, CLMPCC_REG_MEOIR, 0); 1416 1417 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS 1418 if ( sc->sc_soft_running == 0 ) { 1419 sc->sc_soft_running = 1; 1420 (sc->sc_softhook)(sc); 1421 } 1422 #else 1423 softintr_schedule(sc->sc_softintr_cookie); 1424 #endif 1425 1426 return 1; 1427 } 1428 1429 void 1430 clmpcc_softintr(arg) 1431 void *arg; 1432 { 1433 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg; 1434 struct clmpcc_chan *ch; 1435 struct tty *tp; 1436 int (*rint) __P((int, struct tty *)); 1437 u_char *get; 1438 u_char reg; 1439 u_int c; 1440 int chan; 1441 1442 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS 1443 sc->sc_soft_running = 0; 1444 #endif 1445 1446 /* Handle Modem state changes too... */ 1447 1448 for (chan = 0; chan < CLMPCC_NUM_CHANS; chan++) { 1449 ch = &sc->sc_chans[chan]; 1450 tp = ch->ch_tty; 1451 1452 get = ch->ch_ibuf_rd; 1453 rint = tp->t_linesw->l_rint; 1454 1455 /* Squirt buffered incoming data into the tty layer */ 1456 while ( get != ch->ch_ibuf_wr ) { 1457 c = get[0]; 1458 c |= ((u_int)get[1]) << 8; 1459 if ( (rint)(c, tp) == -1 ) { 1460 ch->ch_ibuf_rd = ch->ch_ibuf_wr; 1461 break; 1462 } 1463 1464 get += 2; 1465 if ( get == ch->ch_ibuf_end ) 1466 get = ch->ch_ibuf; 1467 1468 ch->ch_ibuf_rd = get; 1469 } 1470 1471 /* 1472 * Is the transmitter idle and in need of attention? 1473 */ 1474 if ( ch->ch_tx_done ) { 1475 ch->ch_tx_done = 0; 1476 1477 if ( ISSET(ch->ch_flags, CLMPCC_FLG_NEED_INIT) ) { 1478 clmpcc_channel_cmd(sc, ch->ch_car, 1479 CLMPCC_CCR_T0_INIT | 1480 CLMPCC_CCR_T0_RX_EN | 1481 CLMPCC_CCR_T0_TX_EN); 1482 CLR(ch->ch_flags, CLMPCC_FLG_NEED_INIT); 1483 1484 /* 1485 * Allow time for the channel to initialise. 1486 * (Empirically derived duration; there must 1487 * be another way to determine the command 1488 * has completed without busy-waiting...) 1489 */ 1490 delay(800); 1491 1492 /* 1493 * Update the tty layer's idea of the carrier 1494 * bit, in case we changed CLOCAL or MDMBUF. 1495 * We don't hang up here; we only do that by 1496 * explicit request. 1497 */ 1498 reg = clmpcc_rd_msvr(sc) & CLMPCC_MSVR_CD; 1499 (*tp->t_linesw->l_modem)(tp, reg != 0); 1500 } 1501 1502 CLR(tp->t_state, TS_BUSY); 1503 if ( ISSET(tp->t_state, TS_FLUSH) ) 1504 CLR(tp->t_state, TS_FLUSH); 1505 else 1506 ndflush(&tp->t_outq, 1507 (int)(ch->ch_obuf_addr - tp->t_outq.c_cf)); 1508 1509 (*tp->t_linesw->l_start)(tp); 1510 } 1511 } 1512 } 1513 1514 1515 /*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX*/ 1516 /*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX*/ 1517 /*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX*/ 1518 /* 1519 * Following are all routines needed for a cd240x channel to act as console 1520 */ 1521 int 1522 clmpcc_cnattach(sc, chan, rate) 1523 struct clmpcc_softc *sc; 1524 int chan; 1525 int rate; 1526 { 1527 cons_sc = sc; 1528 cons_chan = chan; 1529 cons_rate = rate; 1530 1531 return (clmpcc_init(sc)); 1532 } 1533 1534 /* 1535 * The following functions are polled getc and putc routines, for console use. 1536 */ 1537 static int 1538 clmpcc_common_getc(sc, chan) 1539 struct clmpcc_softc *sc; 1540 int chan; 1541 { 1542 u_char old_chan; 1543 u_char old_ier; 1544 u_char ch, rir, risr; 1545 int s; 1546 1547 s = splhigh(); 1548 1549 /* Save the currently active channel */ 1550 old_chan = clmpcc_select_channel(sc, chan); 1551 1552 /* 1553 * We have to put the channel into RX interrupt mode before 1554 * trying to read the Rx data register. So save the previous 1555 * interrupt mode. 1556 */ 1557 old_ier = clmpcc_rdreg(sc, CLMPCC_REG_IER); 1558 clmpcc_wrreg(sc, CLMPCC_REG_IER, CLMPCC_IER_RX_FIFO); 1559 1560 /* Loop until we get a character */ 1561 for (;;) { 1562 /* 1563 * The REN bit will be set in the Receive Interrupt Register 1564 * when the CD240x has a character to process. Remember, 1565 * the RACT bit won't be set until we generate an interrupt 1566 * acknowledge cycle via the MD front-end. 1567 */ 1568 rir = clmpcc_rdreg(sc, CLMPCC_REG_RIR); 1569 if ( (rir & CLMPCC_RIR_REN) == 0 ) 1570 continue; 1571 1572 /* Acknowledge the request */ 1573 if ( sc->sc_iackhook ) 1574 (sc->sc_iackhook)(sc, CLMPCC_IACK_RX); 1575 1576 /* 1577 * Determine if the interrupt is for the required channel 1578 * and if valid data is available. 1579 */ 1580 rir = clmpcc_rdreg(sc, CLMPCC_REG_RIR); 1581 risr = clmpcc_rdreg(sc, CLMPCC_REG_RISR); 1582 if ( (rir & CLMPCC_RIR_RCN_MASK) != chan || 1583 risr != 0 ) { 1584 /* Rx error, or BREAK */ 1585 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, 1586 CLMPCC_REOIR_NO_TRANS); 1587 } else { 1588 /* Dummy read of the FIFO count register */ 1589 (void) clmpcc_rdreg(sc, CLMPCC_REG_RFOC); 1590 1591 /* Fetch the received character */ 1592 ch = clmpcc_rd_rxdata(sc); 1593 1594 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, 0); 1595 break; 1596 } 1597 } 1598 1599 /* Restore the original IER and CAR register contents */ 1600 clmpcc_wrreg(sc, CLMPCC_REG_IER, old_ier); 1601 clmpcc_select_channel(sc, old_chan); 1602 1603 splx(s); 1604 return ch; 1605 } 1606 1607 1608 static void 1609 clmpcc_common_putc(sc, chan, c) 1610 struct clmpcc_softc *sc; 1611 int chan; 1612 int c; 1613 { 1614 u_char old_chan; 1615 int s = splhigh(); 1616 1617 /* Save the currently active channel */ 1618 old_chan = clmpcc_select_channel(sc, chan); 1619 1620 /* 1621 * Since we can only access the Tx Data register from within 1622 * the interrupt handler, the easiest way to get console data 1623 * onto the wire is using one of the Special Transmit Character 1624 * registers. 1625 */ 1626 clmpcc_wrreg(sc, CLMPCC_REG_SCHR4, c); 1627 clmpcc_wrreg(sc, CLMPCC_REG_STCR, CLMPCC_STCR_SSPC(4) | 1628 CLMPCC_STCR_SND_SPC); 1629 1630 /* Wait until the "Send Special Character" command is accepted */ 1631 while ( clmpcc_rdreg(sc, CLMPCC_REG_STCR) != 0 ) 1632 ; 1633 1634 /* Restore the previous channel selected */ 1635 clmpcc_select_channel(sc, old_chan); 1636 1637 splx(s); 1638 } 1639 1640 int 1641 clmpcccngetc(dev) 1642 dev_t dev; 1643 { 1644 return clmpcc_common_getc(cons_sc, cons_chan); 1645 } 1646 1647 /* 1648 * Console kernel output character routine. 1649 */ 1650 void 1651 clmpcccnputc(dev, c) 1652 dev_t dev; 1653 int c; 1654 { 1655 if ( c == '\n' ) 1656 clmpcc_common_putc(cons_sc, cons_chan, '\r'); 1657 1658 clmpcc_common_putc(cons_sc, cons_chan, c); 1659 } 1660