1 /* $NetBSD: cpc700.c,v 1.4 2002/09/27 03:18:11 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart@augustsson.net) at Sandburst Corp. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * The IBM CPC700 is a bridge chip for the PowerPC. It contains 41 * - CPU interface 42 * - DRAM controller 43 * - PCI bus master & slave controller 44 * - interrupt controller 45 * - timer 46 * - two UARTs 47 * - two IIC ports 48 * 49 * This driver handles the overall device and enumeration of the 50 * supported subdevices. NetBSD knows how to handle: 51 * - PCI master 52 * - interrupt controller 53 * - UARTs 54 * Skeleton drivers are provided for the timer and IIC. 55 * 56 * XXX This driver assumes that there is only one instance of it. 57 */ 58 59 #include "pci.h" 60 #include "opt_pci.h" 61 62 #include <sys/param.h> 63 #include <sys/extent.h> 64 #include <sys/device.h> 65 #include <sys/malloc.h> 66 #include <sys/systm.h> 67 68 #include <machine/bus.h> 69 #include "locators.h" 70 71 #include <dev/pci/pcivar.h> 72 #include <dev/pci/pcireg.h> 73 #include <dev/pci/pciconf.h> 74 75 #include <dev/ic/cpc700reg.h> 76 #include <dev/ic/cpc700var.h> 77 #include <dev/ic/cpc700uic.h> 78 79 union attach_args { 80 const char *busname; /* first elem of all */ 81 struct pcibus_attach_args pba; 82 struct cpcbus_attach_args cba; 83 }; 84 85 86 void 87 cpc_attach(struct device *self, pci_chipset_tag_t pc, bus_space_tag_t mem, 88 bus_space_tag_t pciio, bus_dma_tag_t tag, int attachpci, 89 uint freq); 90 91 static bus_space_tag_t the_cpc_tag; 92 static bus_space_handle_t the_cpc_handle; 93 #define INL(a) bus_space_read_stream_4(the_cpc_tag, the_cpc_handle, (a)) 94 #define OUTL(a, d) bus_space_write_stream_4(the_cpc_tag, the_cpc_handle, (a), d) 95 96 static int 97 cpc_print(void *aux, const char *pnp) 98 { 99 struct cpcbus_attach_args *caa = aux; 100 101 if (pnp) 102 printf("%s at %s", caa->cpca_name, pnp); 103 104 printf(" addr 0x%08x", caa->cpca_addr); 105 if (caa->cpca_irq != CPCBUSCF_IRQ_DEFAULT) 106 printf(" irq %d", caa->cpca_irq); 107 108 return (UNCONF); 109 } 110 111 static int 112 cpcpci_print(void *aux, const char *pnp) 113 { 114 union attach_args *aa = aux; 115 116 if (pnp) 117 printf("%s at %s", aa->busname, pnp); 118 119 return (UNCONF); 120 } 121 122 static int 123 cpc_submatch(struct device *parent, struct cfdata *cf, void *aux) 124 { 125 struct cpcbus_attach_args *caa = aux; 126 127 if (cf->cf_loc[CPCBUSCF_ADDR] != caa->cpca_addr) 128 return (0); 129 130 return (config_match(parent, cf, aux)); 131 } 132 133 /* 134 * Attach the cpc. 135 */ 136 void 137 cpc_attach(struct device *self, pci_chipset_tag_t pc, bus_space_tag_t mem, 138 bus_space_tag_t pciio, bus_dma_tag_t dma, int attachpci, 139 uint freq) 140 { 141 union attach_args aa; 142 int i; 143 pcitag_t tag; 144 pcireg_t erren; 145 static struct { 146 const char *name; 147 bus_addr_t addr; 148 int irq; 149 } devs[] = { 150 { "com", CPC_COM0, CPC_IB_UART_0 }, 151 { "com", CPC_COM1, CPC_IB_UART_1 }, 152 { "cpctim", CPC_TIMER, CPCBUSCF_IRQ_DEFAULT }, 153 { "cpciic", CPC_IIC0, CPC_IB_IIC_0 }, 154 { "cpciic", CPC_IIC1, CPC_IB_IIC_1 }, 155 { NULL, 0 } 156 }; 157 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 158 struct extent *ioext, *memext; 159 #ifdef PCI_CONFIGURE_VERBOSE 160 extern int pci_conf_debug; 161 162 pci_conf_debug = 1; 163 #endif 164 #endif 165 166 printf(": IBM CPC700\n"); 167 168 the_cpc_tag = mem; 169 if (bus_space_map(mem, CPC_UIC_BASE, CPC_UIC_SIZE, 0, 170 &the_cpc_handle)) { 171 printf("%s: can't map i/o space\n", self->dv_xname); 172 return; 173 } 174 175 aa.cba.cpca_tag = mem; 176 aa.cba.cpca_freq = freq; 177 for (i = 0; devs[i].name; i++) { 178 aa.cba.cpca_name = devs[i].name; 179 aa.cba.cpca_addr = devs[i].addr; 180 aa.cba.cpca_irq = devs[i].irq; 181 config_found_sm(self, &aa.cba, cpc_print, cpc_submatch); 182 } 183 184 tag = pci_make_tag(pc, 0, 0, 0); 185 186 aa.pba.pba_busname = "pci"; 187 aa.pba.pba_iot = pciio; 188 aa.pba.pba_memt = mem; 189 aa.pba.pba_dmat = dma; 190 aa.pba.pba_pc = 0; 191 aa.pba.pba_flags = PCI_FLAGS_MEM_ENABLED | PCI_FLAGS_IO_ENABLED; 192 aa.pba.pba_bus = 0; 193 194 /* Save PCI error condition reg. */ 195 erren = pci_conf_read(pc, tag, CPC_PCI_BRDGERR); 196 pci_conf_write(pc, tag, CPC_PCI_BRDGERR, 0); 197 198 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 199 ioext = extent_create("pciio", CPC_PCI_IO_START, CPC_PCI_IO_END, 200 M_DEVBUF, NULL, 0, EX_NOWAIT); 201 memext = extent_create("pcimem", CPC_PCI_MEM_BASE, CPC_PCI_MEM_END, 202 M_DEVBUF, NULL, 0, EX_NOWAIT); 203 204 pci_configure_bus(0, ioext, memext, NULL, 0, 32); 205 206 extent_destroy(ioext); 207 extent_destroy(memext); 208 #endif 209 210 config_found(self, &aa.pba, cpcpci_print); 211 212 /* Restore error triggers, and clear errors */ 213 pci_conf_write(pc, tag, CPC_PCI_BRDGERR, erren | CPC_PCI_CLEARERR); 214 } 215 216 /***************************************************************************/ 217 218 /* 219 * Interrupt controller. 220 */ 221 222 void 223 cpc700_init_intr(bus_space_tag_t bt, bus_space_handle_t bh, 224 u_int32_t active, u_int32_t level) 225 { 226 /* XXX */ 227 the_cpc_tag = bt; 228 the_cpc_handle = bh; 229 /* 230 * See CPC700 manual for information about what 231 * interrupts have which properties. 232 */ 233 OUTL(CPC_UIC_SR, 0xffffffff); /* clear all intrs */ 234 OUTL(CPC_UIC_ER, 0x00000000); /* disable all intrs */ 235 OUTL(CPC_UIC_CR, 0xffffffff); /* gen INT not MCP */ 236 OUTL(CPC_UIC_PR, 0xffff8000 | active); /* 0 = active low */ 237 OUTL(CPC_UIC_TR, 0xc0000000 | level); /* 0 = level intr */ 238 OUTL(CPC_UIC_VR, CPC_UIC_CVR_PRI); /* intr 0 is highest */ 239 } 240 241 int 242 cpc700_read_irq(void) 243 { 244 int irq; 245 u_int32_t irqs; 246 247 irqs = INL(CPC_UIC_MSR); 248 for (irq = 0; irq < ICU_LEN; irq++) { 249 if (irqs & CPC_INTR_MASK(irq)) 250 return (irq); 251 } 252 return (-1); 253 } 254 255 void 256 cpc700_eoi(int irq) 257 { 258 OUTL(CPC_UIC_SR, CPC_INTR_MASK(irq)); 259 } 260 261 void 262 cpc700_disable_irq(int irq) 263 { 264 u_int32_t reg; 265 266 reg = INL(CPC_UIC_ER); 267 reg &= ~CPC_INTR_MASK(irq); 268 OUTL(CPC_UIC_ER, reg); 269 } 270 271 void 272 cpc700_enable_irq(int irq) 273 { 274 u_int32_t reg; 275 276 reg = INL(CPC_UIC_ER); 277 reg |= CPC_INTR_MASK(irq); 278 OUTL(CPC_UIC_ER, reg); 279 } 280