1 /* $NetBSD: cpc700reg.h,v 1.1 2002/05/21 02:58:25 augustss Exp $ */ 2 3 /* 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart@augustsson.net) at Sandburst Corp. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* PCI memory space */ 40 #define CPC_PCI_MEM_BASE 0x80000000 41 #define CPC_PCI_MEM_END 0xf7ffffff 42 43 /* PCI IO space */ 44 #define CPC_PCI_IO_BASE 0xf8000000 45 #define CPC_PCI_IO_START 0xf8800000 /* for allocation */ 46 #define CPC_PCI_IO_END 0xfbffffff 47 48 /* PCI config space */ 49 #define CPC_PCICFGADR 0xfec00000 50 #define CPC_PCI_CONFIG_ENABLE 0x80000000 51 #define CPC_PCICFGDATA 0xfec00004 52 53 /* Config space regs */ 54 #define CPC_PCI_BRDGERR 0x48 55 #define CPC_PCI_CLEARERR 0x0000ff00 56 57 /* PCI interrupt acknowledge & special cycle */ 58 #define CPC_INTR_ACK 0xfed00000 59 60 #define CPC_PMM0_LOCAL 0xff400000 61 #define CPC_PMM0_MASK_ATTR 0xff400004 62 #define CPC_PMM0_PCI_LOW 0xff400008 63 #define CPC_PMM0_PCI_HIGH 0xff40000c 64 #define CPC_PMM1_LOCAL 0xff400010 65 #define CPC_PMM1_MASK_ATTR 0xff400014 66 #define CPC_PMM1_PCI_LOW 0xff400018 67 #define CPC_PMM1_PCI_HIGH 0xff40001c 68 #define CPC_PMM2_LOCAL 0xff400020 69 #define CPC_PMM2_MASK_ATTR 0xff400024 70 #define CPC_PMM2_PCI_LOW 0xff400028 71 #define CPC_PMM2_PCI_HIGH 0xff40002c 72 #define CPC_PTM1_LOCAL 0xff400030 73 #define CPC_PTM1_MEMSIZE 0xff400034 74 #define CPC_PTM2_LOCAL 0xff400038 75 #define CPC_PTM2_MEMSIZE 0xff40003c 76 77 /* serial ports */ 78 #define CPC_COM0 0xff600300 79 #define CPC_COM1 0xff600400 80 #define CPC_COM_SPEED(bus) ((bus) / (2 * 4)) 81 82 /* interrup controller */ 83 #define CPC_UIC_BASE 0xff500880 84 #define CPC_UIC_SIZE 0x00000024 85 #define CPC_UIC_SR 0x00000000 /* UIC status (read/clear) */ 86 #define CPC_UIC_SRS 0x00000004 /* UIC status (set) */ 87 #define CPC_UIC_ER 0x00000008 /* UIC enable */ 88 #define CPC_UIC_CR 0x0000000c /* UIC critical */ 89 #define CPC_UIC_PR 0x00000010 /* UIC polarity 0=low, 1=high*/ 90 #define CPC_UIC_TR 0x00000014 /* UIC trigger 0=level; 1=edge */ 91 #define CPC_UIC_MSR 0x00000018 /* UIC masked status */ 92 #define CPC_UIC_VR 0x0000001c /* UIC vector */ 93 #define CPC_UIC_VCR 0x00000020 /* UIC vector configuration */ 94 #define CPC_UIC_CVR_PRI 0x00000001 /* 0=intr31 high, 1=intr0 high */ 95 /* 96 * if intr0 high then interrupt vector at (vcr&~3) + N*512 97 * if intr31 high then interrupt vector at (vcr&~3) + (31-N)*512 98 */ 99 100 /* UIC interrupt bits. Note, MSB is bit 0 */ 101 /* Internal */ 102 #define CPC_IB_ECC 0 103 #define CPC_IB_PCI_WR_RANGE 1 104 #define CPC_IB_PCI_WR_CMD 2 105 #define CPC_IB_UART_0 3 106 #define CPC_IB_UART_1 4 107 #define CPC_IB_IIC_0 5 108 #define CPC_IB_IIC_1 6 109 /* 6-16 GPT compare&capture */ 110 /* 20-31 external */ 111 #define CPC_IB_EXT0 20 112 #define CPC_IB_EXT1 21 113 #define CPC_IB_EXT2 22 114 #define CPC_IB_EXT3 23 115 #define CPC_IB_EXT4 24 116 #define CPC_IB_EXT5 25 117 #define CPC_IB_EXT6 26 118 #define CPC_IB_EXT7 27 119 #define CPC_IB_EXT8 28 120 #define CPC_IB_EXT9 29 121 #define CPC_IB_EXT10 30 122 #define CPC_IB_EXT11 31 123 124 #define CPC_INTR_MASK(irq) (0x80000000 >> (irq)) 125 126 127 /* IIC */ 128 #define CPC_IIC0 0xff620000 129 #define CPC_IIC1 0xff630000 130 #define CPC_IIC_SIZE 0x00000014 131 /* offsets from base */ 132 #define CPC_IIC_MDBUF 0x00000000 133 #define CPC_IIC_SDBUF 0x00000002 134 #define CPC_IIC_LMADR 0x00000004 135 #define CPC_IIC_HNADR 0x00000005 136 #define CPC_IIC_CNTL 0x00000006 137 #define CPC_IIC_MDCNTL 0x00000007 138 #define CPC_IIC_STS 0x00000008 139 #define CPC_IIC_EXTSTS 0x00000009 140 #define CPC_IIC_LSADR 0x0000000a 141 #define CPC_IIC_HSADR 0x0000000b 142 #define CPC_IIC_CLKDIV 0x0000000c 143 #define CPC_IIC_INTRMSK 0x0000000d 144 #define CPC_IIC_FRCNT 0x0000000e 145 #define CPC_IIC_TCNTLSS 0x0000000f 146 #define CPC_IIC_DIRECTCNTL 0x00000010 147 148 /* timer */ 149 #define CPC_TIMER 0xff650000 150 #define CPC_GPTTBC 0x00000000 151