1 /* $NetBSD: cs89x0.c,v 1.32 2010/11/13 13:52:00 uebayasi Exp $ */ 2 3 /* 4 * Copyright (c) 2004 Christopher Gilbert 5 * All rights reserved. 6 * 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 3. The name of the company nor the name of the author may be used to 13 * endorse or promote products derived from this software without specific 14 * prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * Copyright 1997 31 * Digital Equipment Corporation. All rights reserved. 32 * 33 * This software is furnished under license and may be used and 34 * copied only in accordance with the following terms and conditions. 35 * Subject to these conditions, you may download, copy, install, 36 * use, modify and distribute this software in source and/or binary 37 * form. No title or ownership is transferred hereby. 38 * 39 * 1) Any source code used, modified or distributed must reproduce 40 * and retain this copyright notice and list of conditions as 41 * they appear in the source file. 42 * 43 * 2) No right is granted to use any trade name, trademark, or logo of 44 * Digital Equipment Corporation. Neither the "Digital Equipment 45 * Corporation" name nor any trademark or logo of Digital Equipment 46 * Corporation may be used to endorse or promote products derived 47 * from this software without the prior written permission of 48 * Digital Equipment Corporation. 49 * 50 * 3) This software is provided "AS-IS" and any express or implied 51 * warranties, including but not limited to, any implied warranties 52 * of merchantability, fitness for a particular purpose, or 53 * non-infringement are disclaimed. In no event shall DIGITAL be 54 * liable for any damages whatsoever, and in particular, DIGITAL 55 * shall not be liable for special, indirect, consequential, or 56 * incidental damages or damages for lost profits, loss of 57 * revenue or loss of use, whether such damages arise in contract, 58 * negligence, tort, under statute, in equity, at law or otherwise, 59 * even if advised of the possibility of such damage. 60 */ 61 62 /* 63 **++ 64 ** FACILITY 65 ** 66 ** Device Driver for the Crystal CS8900 ISA Ethernet Controller. 67 ** 68 ** ABSTRACT 69 ** 70 ** This module provides standard ethernet access for INET protocols 71 ** only. 72 ** 73 ** AUTHORS 74 ** 75 ** Peter Dettori SEA - Software Engineering. 76 ** 77 ** CREATION DATE: 78 ** 79 ** 13-Feb-1997. 80 ** 81 ** MODIFICATION HISTORY (Digital): 82 ** 83 ** Revision 1.27 1998/01/20 17:59:40 cgd 84 ** update for moved headers 85 ** 86 ** Revision 1.26 1998/01/12 19:29:36 cgd 87 ** use arm32/isa versions of isadma code. 88 ** 89 ** Revision 1.25 1997/12/12 01:35:27 cgd 90 ** convert to use new arp code (from Brini) 91 ** 92 ** Revision 1.24 1997/12/10 22:31:56 cgd 93 ** trim some fat (get rid of ability to explicitly supply enet addr, since 94 ** it was never used and added a bunch of code which really doesn't belong in 95 ** an enet driver), and clean up slightly. 96 ** 97 ** Revision 1.23 1997/10/06 16:42:12 cgd 98 ** copyright notices 99 ** 100 ** Revision 1.22 1997/06/20 19:38:01 chaiken 101 ** fixes some smartcard problems 102 ** 103 ** Revision 1.21 1997/06/10 02:56:20 grohn 104 ** Added call to ledNetActive 105 ** 106 ** Revision 1.20 1997/06/05 00:47:06 dettori 107 ** Changed cs_process_rx_dma to reset and re-initialise the 108 ** ethernet chip when DMA gets out of sync, or mbufs 109 ** can't be allocated. 110 ** 111 ** Revision 1.19 1997/06/03 03:09:58 dettori 112 ** Turn off sc_txbusy flag when a transmit underrun 113 ** occurs. 114 ** 115 ** Revision 1.18 1997/06/02 00:04:35 dettori 116 ** redefined the transmit table to get around the nfs_timer bug while we are 117 ** looking into it further. 118 ** 119 ** Also changed interrupts from EDGE to LEVEL. 120 ** 121 ** Revision 1.17 1997/05/27 23:31:01 dettori 122 ** Pulled out changes to DMAMODE defines. 123 ** 124 ** Revision 1.16 1997/05/23 04:25:16 cgd 125 ** reformat log so it fits in 80cols 126 ** 127 ** Revision 1.15 1997/05/23 04:22:18 cgd 128 ** remove the existing copyright notice (which Peter Dettori indicated 129 ** was incorrect, copied from an existing NetBSD file only so that the 130 ** file would have a copyright notice on it, and which he'd intended to 131 ** replace). Replace it with a Digital copyright notice, cloned from 132 ** ess.c. It's not really correct either (it indicates that the source 133 ** is Digital confidential!), but is better than nothing and more 134 ** correct than what was there before. 135 ** 136 ** Revision 1.14 1997/05/23 04:12:50 cgd 137 ** use an adaptive transmit start algorithm: start by telling the chip 138 ** to start transmitting after 381 bytes have been fed to it. if that 139 ** gets transmit underruns, ramp down to 1021 bytes then "whole 140 ** packet." If successful at a given level for a while, try the next 141 ** more agressive level. This code doesn't ever try to start 142 ** transmitting after 5 bytes have been sent to the NIC, because 143 ** that underruns rather regularly. The back-off and ramp-up mechanism 144 ** could probably be tuned a little bit, but this works well enough to 145 ** support > 1MB/s transmit rates on a clear ethernet (which is about 146 ** 20-25% better than the driver had previously been getting). 147 ** 148 ** Revision 1.13 1997/05/22 21:06:54 cgd 149 ** redo cs_copy_tx_frame() from scratch. It had a fatal flaw: it was blindly 150 ** casting from u_int8_t * to u_int16_t * without worrying about alignment 151 ** issues. This would cause bogus data to be spit out for mbufs with 152 ** misaligned data. For instance, it caused the following bits to appear 153 ** on the wire: 154 ** ... etBND 1S2C .SHA(K) R ... 155 ** 11112222333344445555 156 ** which should have appeared as: 157 ** ... NetBSD 1.2C (SHARK) ... 158 ** 11112222333344445555 159 ** Note the apparent 'rotate' of the bytes in the word, which was due to 160 ** incorrect unaligned accesses. This data corruption was the cause of 161 ** incoming telnet/rlogin hangs. 162 ** 163 ** Revision 1.12 1997/05/22 01:55:32 cgd 164 ** reformat log so it fits in 80cols 165 ** 166 ** Revision 1.11 1997/05/22 01:50:27 cgd 167 ** * enable input packet address checking in the BPF+IFF_PROMISCUOUS case, 168 ** so packets aimed at other hosts don't get sent to ether_input(). 169 ** * Add a static const char *rcsid initialized with an RCS Id tag, so that 170 ** you can easily tell (`strings`) what version of the driver is in your 171 ** kernel binary. 172 ** * get rid of ether_cmp(). It was inconsistently used, not necessarily 173 ** safe, and not really a performance win anyway. (It was only used when 174 ** setting up the multicast logical address filter, which is an 175 ** infrequent event. It could have been used in the IFF_PROMISCUOUS 176 ** address check above, but the benefit of it vs. memcmp would be 177 ** inconsequential, there.) Use memcmp() instead. 178 ** * restructure csStartOuput to avoid the following bugs in the case where 179 ** txWait was being set: 180 ** * it would accidentally drop the outgoing packet if told to wait 181 ** but the outgoing packet queue was empty. 182 ** * it would bpf_mtap() the outgoing packet multiple times (once for 183 ** each time it was told to wait), and would also recalculate 184 ** the length of the outgoing packet each time it was told to 185 ** wait. 186 ** While there, rename txWait to txLoop, since with the new structure of 187 ** the code, the latter name makes more sense. 188 ** 189 ** Revision 1.10 1997/05/19 02:03:20 cgd 190 ** Set RX_CTL in cs_set_ladr_filt(), rather than cs_initChip(). cs_initChip() 191 ** is the only caller of cs_set_ladr_filt(), and always calls it, so this 192 ** ends up being logically the same. In cs_set_ladr_filt(), if IFF_PROMISC 193 ** is set, enable promiscuous mode (and set IFF_ALLMULTI), otherwise behave 194 ** as before. 195 ** 196 ** Revision 1.9 1997/05/19 01:45:37 cgd 197 ** create a new function, cs_ether_input(), which does received-packet 198 ** BPF and ether_input processing. This code used to be in three places, 199 ** and centralizing it will make adding IFF_PROMISC support much easier. 200 ** Also, in cs_copy_tx_frame(), put it some (currently disabled) code to 201 ** do copies with bus_space_write_region_2(). It's more correct, and 202 ** potentially more efficient. That function needs to be gutted (to 203 ** deal properly with alignment issues, which it currently does wrong), 204 ** however, and the change doesn't gain much, so there's no point in 205 ** enabling it now. 206 ** 207 ** Revision 1.8 1997/05/19 01:17:10 cgd 208 ** fix a comment re: the setting of the TxConfig register. Clean up 209 ** interface counter maintenance (make it use standard idiom). 210 ** 211 **-- 212 */ 213 214 #include <sys/cdefs.h> 215 __KERNEL_RCSID(0, "$NetBSD: cs89x0.c,v 1.32 2010/11/13 13:52:00 uebayasi Exp $"); 216 217 #include "opt_inet.h" 218 219 #include <sys/param.h> 220 #include <sys/systm.h> 221 #include <sys/mbuf.h> 222 #include <sys/syslog.h> 223 #include <sys/socket.h> 224 #include <sys/device.h> 225 #include <sys/malloc.h> 226 #include <sys/ioctl.h> 227 #include <sys/errno.h> 228 229 #include "rnd.h" 230 #if NRND > 0 231 #include <sys/rnd.h> 232 #endif 233 234 #include <net/if.h> 235 #include <net/if_ether.h> 236 #include <net/if_media.h> 237 #ifdef INET 238 #include <netinet/in.h> 239 #include <netinet/if_inarp.h> 240 #endif 241 242 #include <net/bpf.h> 243 #include <net/bpfdesc.h> 244 245 #include <sys/bus.h> 246 #include <sys/intr.h> 247 248 #include <dev/ic/cs89x0reg.h> 249 #include <dev/ic/cs89x0var.h> 250 251 #ifdef SHARK 252 #include <shark/shark/sequoia.h> 253 #endif 254 255 /* 256 * MACRO DEFINITIONS 257 */ 258 #define CS_OUTPUT_LOOP_MAX 100 /* max times round notorious tx loop */ 259 260 /* 261 * FUNCTION PROTOTYPES 262 */ 263 static void cs_get_default_media(struct cs_softc *); 264 static int cs_get_params(struct cs_softc *); 265 static int cs_get_enaddr(struct cs_softc *); 266 static int cs_reset_chip(struct cs_softc *); 267 static void cs_reset(struct cs_softc *); 268 static int cs_ioctl(struct ifnet *, u_long, void *); 269 static void cs_initChip(struct cs_softc *); 270 static void cs_buffer_event(struct cs_softc *, u_int16_t); 271 static void cs_transmit_event(struct cs_softc *, u_int16_t); 272 static void cs_receive_event(struct cs_softc *, u_int16_t); 273 static void cs_process_receive(struct cs_softc *); 274 static void cs_process_rx_early(struct cs_softc *); 275 static void cs_start_output(struct ifnet *); 276 static void cs_copy_tx_frame(struct cs_softc *, struct mbuf *); 277 static void cs_set_ladr_filt(struct cs_softc *, struct ethercom *); 278 static u_int16_t cs_hash_index(char *); 279 static void cs_counter_event(struct cs_softc *, u_int16_t); 280 281 static int cs_mediachange(struct ifnet *); 282 static void cs_mediastatus(struct ifnet *, struct ifmediareq *); 283 284 static bool cs_shutdown(device_t, int); 285 static int cs_enable(struct cs_softc *); 286 static void cs_disable(struct cs_softc *); 287 static void cs_stop(struct ifnet *, int); 288 static int cs_scan_eeprom(struct cs_softc *); 289 static int cs_read_pktpg_from_eeprom(struct cs_softc *, int, u_int16_t *); 290 291 292 /* 293 * GLOBAL DECLARATIONS 294 */ 295 296 /* 297 * Xmit-early table. 298 * 299 * To get better performance, we tell the chip to start packet 300 * transmission before the whole packet is copied to the chip. 301 * However, this can fail under load. When it fails, we back off 302 * to a safer setting for a little while. 303 * 304 * txcmd is the value of txcmd used to indicate when to start transmission. 305 * better is the next 'better' state in the table. 306 * better_count is the number of output packets before transition to the 307 * better state. 308 * worse is the next 'worse' state in the table. 309 * 310 * Transition to the next worse state happens automatically when a 311 * transmittion underrun occurs. 312 */ 313 struct cs_xmit_early { 314 u_int16_t txcmd; 315 int better; 316 int better_count; 317 int worse; 318 } cs_xmit_early_table[3] = { 319 { TX_CMD_START_381, 0, INT_MAX, 1, }, 320 { TX_CMD_START_1021, 0, 50000, 2, }, 321 { TX_CMD_START_ALL, 1, 5000, 2, }, 322 }; 323 324 int cs_default_media[] = { 325 IFM_ETHER|IFM_10_2, 326 IFM_ETHER|IFM_10_5, 327 IFM_ETHER|IFM_10_T, 328 IFM_ETHER|IFM_10_T|IFM_FDX, 329 }; 330 int cs_default_nmedia = sizeof(cs_default_media) / sizeof(cs_default_media[0]); 331 332 int 333 cs_attach(struct cs_softc *sc, u_int8_t *enaddr, int *media, 334 int nmedia, int defmedia) 335 { 336 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 337 const char *chipname, *medname; 338 u_int16_t reg; 339 int i; 340 341 /* Start out in IO mode */ 342 sc->sc_memorymode = FALSE; 343 344 /* make sure we're right */ 345 for (i = 0; i < 10000; i++) { 346 reg = CS_READ_PACKET_PAGE(sc, PKTPG_EISA_NUM); 347 if (reg == EISA_NUM_CRYSTAL) { 348 break; 349 } 350 } 351 if (i == 10000) { 352 aprint_error_dev(sc->sc_dev, "wrong id(0x%x)\n", reg); 353 return 1; /* XXX should panic? */ 354 } 355 356 reg = CS_READ_PACKET_PAGE(sc, PKTPG_PRODUCT_ID); 357 sc->sc_prodid = reg & PROD_ID_MASK; 358 sc->sc_prodrev = (reg & PROD_REV_MASK) >> 8; 359 360 switch (sc->sc_prodid) { 361 case PROD_ID_CS8900: 362 chipname = "CS8900"; 363 break; 364 case PROD_ID_CS8920: 365 chipname = "CS8920"; 366 break; 367 case PROD_ID_CS8920M: 368 chipname = "CS8920M"; 369 break; 370 default: 371 panic("cs_attach: impossible"); 372 } 373 374 /* 375 * the first thing to do is check that the mbuf cluster size is 376 * greater than the MTU for an ethernet frame. The code depends on 377 * this and to port this to a OS where this was not the case would 378 * not be straightforward. 379 * 380 * we need 1 byte spare because our 381 * packet read loop can overrun. 382 * and we may need pad bytes to align ip header. 383 */ 384 if (MCLBYTES < ETHER_MAX_LEN + 1 + 385 ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header)) { 386 printf("%s: MCLBYTES too small for Ethernet frame\n", 387 device_xname(sc->sc_dev)); 388 return 1; 389 } 390 391 /* Start out not transmitting */ 392 sc->sc_txbusy = FALSE; 393 394 /* Set up early transmit threshhold */ 395 sc->sc_xe_ent = 0; 396 sc->sc_xe_togo = cs_xmit_early_table[sc->sc_xe_ent].better_count; 397 398 /* Initialize ifnet structure. */ 399 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 400 ifp->if_softc = sc; 401 ifp->if_start = cs_start_output; 402 ifp->if_init = cs_init; 403 ifp->if_ioctl = cs_ioctl; 404 ifp->if_stop = cs_stop; 405 ifp->if_watchdog = NULL; /* no watchdog at this stage */ 406 ifp->if_flags = IFF_SIMPLEX | IFF_NOTRAILERS | 407 IFF_BROADCAST | IFF_MULTICAST; 408 IFQ_SET_READY(&ifp->if_snd); 409 410 /* Initialize ifmedia structures. */ 411 ifmedia_init(&sc->sc_media, 0, cs_mediachange, cs_mediastatus); 412 413 if (media != NULL) { 414 for (i = 0; i < nmedia; i++) 415 ifmedia_add(&sc->sc_media, media[i], 0, NULL); 416 ifmedia_set(&sc->sc_media, defmedia); 417 } else { 418 for (i = 0; i < cs_default_nmedia; i++) 419 ifmedia_add(&sc->sc_media, cs_default_media[i], 420 0, NULL); 421 cs_get_default_media(sc); 422 } 423 424 if (sc->sc_cfgflags & CFGFLG_PARSE_EEPROM) { 425 if (cs_scan_eeprom(sc) == CS_ERROR) { 426 /* failed to scan the eeprom, pretend there isn't an eeprom */ 427 aprint_error_dev(sc->sc_dev, "unable to scan EEPROM\n"); 428 sc->sc_cfgflags |= CFGFLG_NOT_EEPROM; 429 } 430 } 431 432 if ((sc->sc_cfgflags & CFGFLG_NOT_EEPROM) == 0) { 433 /* Get parameters from the EEPROM */ 434 if (cs_get_params(sc) == CS_ERROR) { 435 aprint_error_dev(sc->sc_dev, 436 "unable to get settings from EEPROM\n"); 437 return 1; 438 } 439 } 440 441 if (enaddr != NULL) 442 memcpy(sc->sc_enaddr, enaddr, sizeof(sc->sc_enaddr)); 443 else if ((sc->sc_cfgflags & CFGFLG_NOT_EEPROM) == 0) { 444 /* Get and store the Ethernet address */ 445 if (cs_get_enaddr(sc) == CS_ERROR) { 446 aprint_error_dev(sc->sc_dev, 447 "unable to read Ethernet address\n"); 448 return 1; 449 } 450 } else { 451 #if 1 452 int j; 453 uint v; 454 455 for (j = 0; j < 6; j += 2) { 456 v = CS_READ_PACKET_PAGE(sc, PKTPG_IND_ADDR + j); 457 sc->sc_enaddr[j + 0] = v; 458 sc->sc_enaddr[j + 1] = v >> 8; 459 } 460 #else 461 printf("%s: no Ethernet address!\n", device_xname(sc->sc_dev)); 462 return 1; 463 #endif 464 } 465 466 switch (IFM_SUBTYPE(sc->sc_media.ifm_cur->ifm_media)) { 467 case IFM_10_2: 468 medname = "BNC"; 469 break; 470 case IFM_10_5: 471 medname = "AUI"; 472 break; 473 case IFM_10_T: 474 if (sc->sc_media.ifm_cur->ifm_media & IFM_FDX) 475 medname = "UTP <full-duplex>"; 476 else 477 medname = "UTP"; 478 break; 479 default: 480 panic("cs_attach: impossible"); 481 } 482 printf("%s: %s rev. %c, address %s, media %s\n", 483 device_xname(sc->sc_dev), 484 chipname, sc->sc_prodrev + 'A', ether_sprintf(sc->sc_enaddr), 485 medname); 486 487 if (sc->sc_dma_attach) 488 (*sc->sc_dma_attach)(sc); 489 490 /* Attach the interface. */ 491 if_attach(ifp); 492 ether_ifattach(ifp, sc->sc_enaddr); 493 494 #if NRND > 0 495 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 496 RND_TYPE_NET, 0); 497 #endif 498 sc->sc_cfgflags |= CFGFLG_ATTACHED; 499 500 if (pmf_device_register1(sc->sc_dev, NULL, NULL, cs_shutdown)) 501 pmf_class_network_register(sc->sc_dev, ifp); 502 else 503 aprint_error_dev(sc->sc_dev, 504 "couldn't establish power handler\n"); 505 506 /* Reset the chip */ 507 if (cs_reset_chip(sc) == CS_ERROR) { 508 aprint_error_dev(sc->sc_dev, "reset failed\n"); 509 cs_detach(sc); 510 return 1; 511 } 512 513 return 0; 514 } 515 516 int 517 cs_detach(struct cs_softc *sc) 518 { 519 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 520 521 if (sc->sc_cfgflags & CFGFLG_ATTACHED) { 522 #if NRND > 0 523 rnd_detach_source(&sc->rnd_source); 524 #endif 525 ether_ifdetach(ifp); 526 if_detach(ifp); 527 sc->sc_cfgflags &= ~CFGFLG_ATTACHED; 528 } 529 530 #if 0 531 /* 532 * XXX not necessary 533 */ 534 if (sc->sc_cfgflags & CFGFLG_DMA_MODE) { 535 isa_dmamem_unmap(sc->sc_ic, sc->sc_drq, sc->sc_dmabase, sc->sc_dmasize); 536 isa_dmamem_free(sc->sc_ic, sc->sc_drq, sc->sc_dmaaddr, sc->sc_dmasize); 537 isa_dmamap_destroy(sc->sc_ic, sc->sc_drq); 538 sc->sc_cfgflags &= ~CFGFLG_DMA_MODE; 539 } 540 #endif 541 542 pmf_device_deregister(sc->sc_dev); 543 544 return 0; 545 } 546 547 bool 548 cs_shutdown(device_t self, int howto) 549 { 550 struct cs_softc *sc; 551 552 sc = device_private(self); 553 cs_reset(sc); 554 555 return true; 556 } 557 558 void 559 cs_get_default_media(struct cs_softc *sc) 560 { 561 u_int16_t adp_cfg, xmit_ctl; 562 563 if (cs_verify_eeprom(sc) == CS_ERROR) { 564 aprint_error_dev(sc->sc_dev, 565 "cs_get_default_media: EEPROM missing or bad\n"); 566 goto fakeit; 567 } 568 569 if (cs_read_eeprom(sc, EEPROM_ADPTR_CFG, &adp_cfg) == CS_ERROR) { 570 aprint_error_dev(sc->sc_dev, 571 "unable to read adapter config from EEPROM\n"); 572 goto fakeit; 573 } 574 575 if (cs_read_eeprom(sc, EEPROM_XMIT_CTL, &xmit_ctl) == CS_ERROR) { 576 aprint_error_dev(sc->sc_dev, 577 "unable to read transmit control from EEPROM\n"); 578 goto fakeit; 579 } 580 581 switch (adp_cfg & ADPTR_CFG_MEDIA) { 582 case ADPTR_CFG_AUI: 583 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_5); 584 break; 585 case ADPTR_CFG_10BASE2: 586 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_2); 587 break; 588 case ADPTR_CFG_10BASET: 589 default: 590 if (xmit_ctl & XMIT_CTL_FDX) 591 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_T|IFM_FDX); 592 else 593 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_T); 594 break; 595 } 596 return; 597 598 fakeit: 599 aprint_error_dev(sc->sc_dev, 600 "WARNING: default media setting may be inaccurate\n"); 601 /* XXX Arbitrary... */ 602 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_T); 603 } 604 605 /* 606 * cs_scan_eeprom 607 * 608 * Attempt to take a complete copy of the eeprom into main memory. 609 * this will allow faster parsing of the eeprom data. 610 * 611 * Only tested against a 8920M's eeprom, but the data sheet for the 612 * 8920A indicates that is uses the same layout. 613 */ 614 int 615 cs_scan_eeprom(struct cs_softc *sc) 616 { 617 u_int16_t result; 618 int i; 619 int eeprom_size; 620 u_int8_t checksum = 0; 621 622 if (cs_verify_eeprom(sc) == CS_ERROR) { 623 aprint_error_dev(sc->sc_dev, 624 "cs_scan_params: EEPROM missing or bad\n"); 625 return (CS_ERROR); 626 } 627 628 /* 629 * read the 0th word from the eeprom, it will tell us the length 630 * and if the eeprom is valid 631 */ 632 cs_read_eeprom(sc, 0, &result); 633 634 /* check the eeprom signature */ 635 if ((result & 0xE000) != 0xA000) { 636 /* empty eeprom */ 637 return (CS_ERROR); 638 } 639 640 /* 641 * take the eeprom size (note the read value doesn't include the header 642 * word) 643 */ 644 eeprom_size = (result & 0xff) + 2; 645 646 sc->eeprom_data = malloc(eeprom_size, M_DEVBUF, M_WAITOK); 647 if (sc->eeprom_data == NULL) { 648 /* no memory, treat this as if there's no eeprom */ 649 return (CS_ERROR); 650 } 651 652 sc->eeprom_size = eeprom_size; 653 654 /* read the eeprom into the buffer, also calculate the checksum */ 655 for (i = 0; i < (eeprom_size >> 1); i++) { 656 cs_read_eeprom(sc, i, &(sc->eeprom_data[i])); 657 checksum += (sc->eeprom_data[i] & 0xff00) >> 8; 658 checksum += (sc->eeprom_data[i] & 0x00ff); 659 } 660 661 /* 662 * validate checksum calculation, the sum of all the bytes should be 0, 663 * as the high byte of the last word is the 2's complement of the 664 * sum to that point. 665 */ 666 if (checksum != 0) { 667 aprint_error_dev(sc->sc_dev, "eeprom checksum failure\n"); 668 return (CS_ERROR); 669 } 670 671 return (CS_OK); 672 } 673 674 static int 675 cs_read_pktpg_from_eeprom(struct cs_softc *sc, int pktpg, u_int16_t *pValue) 676 { 677 int x, maxword; 678 679 /* Check that we have eeprom data */ 680 if ((sc->eeprom_data == NULL) || (sc->eeprom_size < 2)) 681 return (CS_ERROR); 682 683 /* 684 * We only want to read the data words, the last word contains the 685 * checksum 686 */ 687 maxword = (sc->eeprom_size - 2) >> 1; 688 689 /* start 1 word in, as the first word is the length and signature */ 690 x = 1; 691 692 while ( x < (maxword)) { 693 u_int16_t header; 694 int group_size; 695 int offset; 696 int offset_max; 697 698 /* read in the group header word */ 699 header = sc->eeprom_data[x]; 700 x++; /* skip group header */ 701 702 /* 703 * size of group in words is in the top 4 bits, note that it 704 * is one less than the number of words 705 */ 706 group_size = header & 0xF000; 707 708 /* 709 * CS8900 Data sheet says this should be 0x01ff, 710 * but my cs8920 eeprom has higher offsets, 711 * perhaps the 8920 allows higher offsets, otherwise 712 * it's writing to places that it shouldn't 713 */ 714 /* work out the offsets this group covers */ 715 offset = header & 0x0FFF; 716 offset_max = offset + (group_size << 1); 717 718 /* check if the pkgpg we're after is in this group */ 719 if ((offset <= pktpg) && (pktpg <= offset_max)) { 720 /* the pkgpg value we want is in here */ 721 int eeprom_location; 722 723 eeprom_location = ((pktpg - offset) >> 1) ; 724 725 *pValue = sc->eeprom_data[x + eeprom_location]; 726 return (CS_OK); 727 } else { 728 /* skip this group (+ 1 for first entry) */ 729 x += group_size + 1; 730 } 731 } 732 733 /* 734 * if we've fallen out here then we don't have a value in the EEPROM 735 * for this pktpg so return an error 736 */ 737 return (CS_ERROR); 738 } 739 740 int 741 cs_get_params(struct cs_softc *sc) 742 { 743 u_int16_t isaConfig; 744 u_int16_t adapterConfig; 745 746 if (cs_verify_eeprom(sc) == CS_ERROR) { 747 aprint_error_dev(sc->sc_dev, 748 "cs_get_params: EEPROM missing or bad\n"); 749 return (CS_ERROR); 750 } 751 752 if (sc->sc_cfgflags & CFGFLG_PARSE_EEPROM) { 753 /* Get ISA configuration from the EEPROM */ 754 if (cs_read_pktpg_from_eeprom(sc, PKTPG_BUS_CTL, &isaConfig) 755 == CS_ERROR) { 756 /* eeprom doesn't have this value, use data sheet default */ 757 isaConfig = 0x0017; 758 } 759 760 /* Get adapter configuration from the EEPROM */ 761 if (cs_read_pktpg_from_eeprom(sc, PKTPG_SELF_CTL, &adapterConfig) 762 == CS_ERROR) { 763 /* eeprom doesn't have this value, use data sheet default */ 764 adapterConfig = 0x0015; 765 } 766 767 /* Copy the USE_SA flag */ 768 if (isaConfig & BUS_CTL_USE_SA) 769 sc->sc_cfgflags |= CFGFLG_USE_SA; 770 771 /* Copy the IO Channel Ready flag */ 772 if (isaConfig & BUS_CTL_IOCHRDY) 773 sc->sc_cfgflags |= CFGFLG_IOCHRDY; 774 775 /* Copy the DC/DC Polarity flag */ 776 if (adapterConfig & SELF_CTL_HCB1) 777 sc->sc_cfgflags |= CFGFLG_DCDC_POL; 778 } else { 779 /* Get ISA configuration from the EEPROM */ 780 if (cs_read_eeprom(sc, EEPROM_ISA_CFG, &isaConfig) == CS_ERROR) 781 goto eeprom_bad; 782 783 /* Get adapter configuration from the EEPROM */ 784 if (cs_read_eeprom(sc, EEPROM_ADPTR_CFG, &adapterConfig) == CS_ERROR) 785 goto eeprom_bad; 786 787 /* Copy the USE_SA flag */ 788 if (isaConfig & ISA_CFG_USE_SA) 789 sc->sc_cfgflags |= CFGFLG_USE_SA; 790 791 /* Copy the IO Channel Ready flag */ 792 if (isaConfig & ISA_CFG_IOCHRDY) 793 sc->sc_cfgflags |= CFGFLG_IOCHRDY; 794 795 /* Copy the DC/DC Polarity flag */ 796 if (adapterConfig & ADPTR_CFG_DCDC_POL) 797 sc->sc_cfgflags |= CFGFLG_DCDC_POL; 798 } 799 800 return (CS_OK); 801 eeprom_bad: 802 aprint_error_dev(sc->sc_dev, 803 "cs_get_params: unable to read from EEPROM\n"); 804 return (CS_ERROR); 805 } 806 807 int 808 cs_get_enaddr(struct cs_softc *sc) 809 { 810 uint16_t myea[ETHER_ADDR_LEN / sizeof(uint16_t)]; 811 int i; 812 813 if (cs_verify_eeprom(sc) == CS_ERROR) { 814 aprint_error_dev(sc->sc_dev, 815 "cs_get_enaddr: EEPROM missing or bad\n"); 816 return (CS_ERROR); 817 } 818 819 /* Get Ethernet address from the EEPROM */ 820 if (sc->sc_cfgflags & CFGFLG_PARSE_EEPROM) { 821 if (cs_read_pktpg_from_eeprom(sc, PKTPG_IND_ADDR, &myea[0]) 822 == CS_ERROR) 823 goto eeprom_bad; 824 if (cs_read_pktpg_from_eeprom(sc, PKTPG_IND_ADDR + 2, &myea[1]) 825 == CS_ERROR) 826 goto eeprom_bad; 827 if (cs_read_pktpg_from_eeprom(sc, PKTPG_IND_ADDR + 4, &myea[2]) 828 == CS_ERROR) 829 goto eeprom_bad; 830 } else { 831 if (cs_read_eeprom(sc, EEPROM_IND_ADDR_H, &myea[0]) == CS_ERROR) 832 goto eeprom_bad; 833 if (cs_read_eeprom(sc, EEPROM_IND_ADDR_M, &myea[1]) == CS_ERROR) 834 goto eeprom_bad; 835 if (cs_read_eeprom(sc, EEPROM_IND_ADDR_L, &myea[2]) == CS_ERROR) 836 goto eeprom_bad; 837 } 838 839 for (i = 0; i < __arraycount(myea); i++) { 840 sc->sc_enaddr[i * 2 + 0] = myea[i]; 841 sc->sc_enaddr[i * 2 + 1] = myea[i] >> 8; 842 } 843 844 return (CS_OK); 845 846 eeprom_bad: 847 aprint_error_dev(sc->sc_dev, 848 "cs_get_enaddr: unable to read from EEPROM\n"); 849 return (CS_ERROR); 850 } 851 852 int 853 cs_reset_chip(struct cs_softc *sc) 854 { 855 int intState; 856 int x; 857 858 /* Disable interrupts at the CPU so reset command is atomic */ 859 intState = splnet(); 860 861 /* 862 * We are now resetting the chip 863 * 864 * A spurious interrupt is generated by the chip when it is reset. This 865 * variable informs the interrupt handler to ignore this interrupt. 866 */ 867 sc->sc_resetting = TRUE; 868 869 /* Issue a reset command to the chip */ 870 CS_WRITE_PACKET_PAGE(sc, PKTPG_SELF_CTL, SELF_CTL_RESET); 871 872 /* Re-enable interrupts at the CPU */ 873 splx(intState); 874 875 /* The chip is always in IO mode after a reset */ 876 sc->sc_memorymode = FALSE; 877 878 /* If transmission was in progress, it is not now */ 879 sc->sc_txbusy = FALSE; 880 881 /* 882 * there was a delay(125); here, but it seems uneccesary 125 usec is 883 * 1/8000 of a second, not 1/8 of a second. the data sheet advises 884 * 1/10 of a second here, but the SI_BUSY and INIT_DONE loops below 885 * should be sufficient. 886 */ 887 888 /* Transition SBHE to switch chip from 8-bit to 16-bit */ 889 IO_READ_1(sc, PORT_PKTPG_PTR + 0); 890 IO_READ_1(sc, PORT_PKTPG_PTR + 1); 891 IO_READ_1(sc, PORT_PKTPG_PTR + 0); 892 IO_READ_1(sc, PORT_PKTPG_PTR + 1); 893 894 /* Wait until the EEPROM is not busy */ 895 for (x = 0; x < MAXLOOP; x++) { 896 if (!(CS_READ_PACKET_PAGE(sc, PKTPG_SELF_ST) & SELF_ST_SI_BUSY)) 897 break; 898 } 899 900 if (x == MAXLOOP) 901 return CS_ERROR; 902 903 /* Wait until initialization is done */ 904 for (x = 0; x < MAXLOOP; x++) { 905 if (CS_READ_PACKET_PAGE(sc, PKTPG_SELF_ST) & SELF_ST_INIT_DONE) 906 break; 907 } 908 909 if (x == MAXLOOP) 910 return CS_ERROR; 911 912 /* Reset is no longer in progress */ 913 sc->sc_resetting = FALSE; 914 915 return CS_OK; 916 } 917 918 int 919 cs_verify_eeprom(struct cs_softc *sc) 920 { 921 u_int16_t self_status; 922 923 /* Verify that the EEPROM is present and OK */ 924 self_status = CS_READ_PACKET_PAGE_IO(sc, PKTPG_SELF_ST); 925 if (((self_status & SELF_ST_EEP_PRES) && 926 (self_status & SELF_ST_EEP_OK)) == 0) 927 return (CS_ERROR); 928 929 return (CS_OK); 930 } 931 932 int 933 cs_read_eeprom(struct cs_softc *sc, int offset, u_int16_t *pValue) 934 { 935 int x; 936 937 /* Ensure that the EEPROM is not busy */ 938 for (x = 0; x < MAXLOOP; x++) { 939 if (!(CS_READ_PACKET_PAGE_IO(sc, PKTPG_SELF_ST) & 940 SELF_ST_SI_BUSY)) 941 break; 942 } 943 944 if (x == MAXLOOP) 945 return (CS_ERROR); 946 947 /* Issue the command to read the offset within the EEPROM */ 948 CS_WRITE_PACKET_PAGE_IO(sc, PKTPG_EEPROM_CMD, 949 offset | EEPROM_CMD_READ); 950 951 /* Wait until the command is completed */ 952 for (x = 0; x < MAXLOOP; x++) { 953 if (!(CS_READ_PACKET_PAGE_IO(sc, PKTPG_SELF_ST) & 954 SELF_ST_SI_BUSY)) 955 break; 956 } 957 958 if (x == MAXLOOP) 959 return (CS_ERROR); 960 961 /* Get the EEPROM data from the EEPROM Data register */ 962 *pValue = CS_READ_PACKET_PAGE_IO(sc, PKTPG_EEPROM_DATA); 963 964 return (CS_OK); 965 } 966 967 void 968 cs_initChip(struct cs_softc *sc) 969 { 970 u_int16_t busCtl; 971 u_int16_t selfCtl; 972 u_int16_t v; 973 u_int16_t isaId; 974 int i; 975 int media = IFM_SUBTYPE(sc->sc_media.ifm_cur->ifm_media); 976 977 /* Disable reception and transmission of frames */ 978 CS_WRITE_PACKET_PAGE(sc, PKTPG_LINE_CTL, 979 CS_READ_PACKET_PAGE(sc, PKTPG_LINE_CTL) & 980 ~LINE_CTL_RX_ON & ~LINE_CTL_TX_ON); 981 982 /* Disable interrupt at the chip */ 983 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 984 CS_READ_PACKET_PAGE(sc, PKTPG_BUS_CTL) & ~BUS_CTL_INT_ENBL); 985 986 /* If IOCHRDY is enabled then clear the bit in the busCtl register */ 987 busCtl = CS_READ_PACKET_PAGE(sc, PKTPG_BUS_CTL); 988 if (sc->sc_cfgflags & CFGFLG_IOCHRDY) { 989 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 990 busCtl & ~BUS_CTL_IOCHRDY); 991 } else { 992 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 993 busCtl | BUS_CTL_IOCHRDY); 994 } 995 996 /* Set the Line Control register to match the media type */ 997 if (media == IFM_10_T) 998 CS_WRITE_PACKET_PAGE(sc, PKTPG_LINE_CTL, LINE_CTL_10BASET); 999 else 1000 CS_WRITE_PACKET_PAGE(sc, PKTPG_LINE_CTL, LINE_CTL_AUI_ONLY); 1001 1002 /* 1003 * Set the BSTATUS/HC1 pin to be used as HC1. HC1 is used to 1004 * enable the DC/DC converter 1005 */ 1006 selfCtl = SELF_CTL_HC1E; 1007 1008 /* If the media type is 10Base2 */ 1009 if (media == IFM_10_2) { 1010 /* 1011 * Enable the DC/DC converter if it has a low enable. 1012 */ 1013 if ((sc->sc_cfgflags & CFGFLG_DCDC_POL) == 0) 1014 /* 1015 * Set the HCB1 bit, which causes the HC1 pin to go 1016 * low. 1017 */ 1018 selfCtl |= SELF_CTL_HCB1; 1019 } else { /* Media type is 10BaseT or AUI */ 1020 /* 1021 * Disable the DC/DC converter if it has a high enable. 1022 */ 1023 if ((sc->sc_cfgflags & CFGFLG_DCDC_POL) != 0) { 1024 /* 1025 * Set the HCB1 bit, which causes the HC1 pin to go 1026 * low. 1027 */ 1028 selfCtl |= SELF_CTL_HCB1; 1029 } 1030 } 1031 CS_WRITE_PACKET_PAGE(sc, PKTPG_SELF_CTL, selfCtl); 1032 1033 /* enable normal link pulse */ 1034 if (sc->sc_prodid == PROD_ID_CS8920 || sc->sc_prodid == PROD_ID_CS8920M) 1035 CS_WRITE_PACKET_PAGE(sc, PKTPG_AUTONEG_CTL, AUTOCTL_NLP_ENABLE); 1036 1037 /* Enable full-duplex, if appropriate */ 1038 if (sc->sc_media.ifm_cur->ifm_media & IFM_FDX) 1039 CS_WRITE_PACKET_PAGE(sc, PKTPG_TEST_CTL, TEST_CTL_FDX); 1040 1041 /* RX_CTL set in cs_set_ladr_filt(), below */ 1042 1043 /* enable all transmission interrupts */ 1044 CS_WRITE_PACKET_PAGE(sc, PKTPG_TX_CFG, TX_CFG_ALL_IE); 1045 1046 /* Accept all receive interrupts */ 1047 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, RX_CFG_ALL_IE); 1048 1049 /* 1050 * Configure Operational Modes 1051 * 1052 * I have turned off the BUF_CFG_RX_MISS_IE, to speed things up, this is 1053 * a better way to do it because the card has a counter which can be 1054 * read to update the RX_MISS counter. This saves many interrupts. 1055 * 1056 * I have turned on the tx and rx overflow interrupts to counter using 1057 * the receive miss interrupt. This is a better estimate of errors 1058 * and requires lower system overhead. 1059 */ 1060 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUF_CFG, BUF_CFG_TX_UNDR_IE | 1061 BUF_CFG_RX_DMA_IE); 1062 1063 if (sc->sc_dma_chipinit) 1064 (*sc->sc_dma_chipinit)(sc); 1065 1066 /* If memory mode is enabled */ 1067 if (sc->sc_cfgflags & CFGFLG_MEM_MODE) { 1068 /* If external logic is present for address decoding */ 1069 if (CS_READ_PACKET_PAGE(sc, PKTPG_SELF_ST) & SELF_ST_EL_PRES) { 1070 /* 1071 * Program the external logic to decode address bits 1072 * SA20-SA23 1073 */ 1074 CS_WRITE_PACKET_PAGE(sc, PKTPG_EEPROM_CMD, 1075 ((sc->sc_pktpgaddr & 0xffffff) >> 20) | 1076 EEPROM_CMD_ELSEL); 1077 } 1078 1079 /* 1080 * Write the packet page base physical address to the memory 1081 * base register. 1082 */ 1083 CS_WRITE_PACKET_PAGE(sc, PKTPG_MEM_BASE + 0, 1084 sc->sc_pktpgaddr & 0xFFFF); 1085 CS_WRITE_PACKET_PAGE(sc, PKTPG_MEM_BASE + 2, 1086 sc->sc_pktpgaddr >> 16); 1087 busCtl = BUS_CTL_MEM_MODE; 1088 1089 /* tell the chip to read the addresses off the SA pins */ 1090 if (sc->sc_cfgflags & CFGFLG_USE_SA) { 1091 busCtl |= BUS_CTL_USE_SA; 1092 } 1093 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 1094 CS_READ_PACKET_PAGE(sc, PKTPG_BUS_CTL) | busCtl); 1095 1096 /* We are in memory mode now! */ 1097 sc->sc_memorymode = TRUE; 1098 1099 /* 1100 * wait here (10ms) for the chip to swap over. this is the 1101 * maximum time that this could take. 1102 */ 1103 delay(10000); 1104 1105 /* Verify that we can read from the chip */ 1106 isaId = CS_READ_PACKET_PAGE(sc, PKTPG_EISA_NUM); 1107 1108 /* 1109 * As a last minute sanity check before actually using mapped 1110 * memory we verify that we can read the isa number from the 1111 * chip in memory mode. 1112 */ 1113 if (isaId != EISA_NUM_CRYSTAL) { 1114 aprint_error_dev(sc->sc_dev, 1115 "failed to enable memory mode\n"); 1116 sc->sc_memorymode = FALSE; 1117 } else { 1118 /* 1119 * we are in memory mode so if we aren't using DMA, 1120 * then program the chip to interrupt early. 1121 */ 1122 if ((sc->sc_cfgflags & CFGFLG_DMA_MODE) == 0) { 1123 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUF_CFG, 1124 BUF_CFG_RX_DEST_IE | 1125 BUF_CFG_RX_MISS_OVER_IE | 1126 BUF_CFG_TX_COL_OVER_IE); 1127 } 1128 } 1129 1130 } 1131 1132 /* Put Ethernet address into the Individual Address register */ 1133 for (i = 0; i < 6; i += 2) { 1134 v = sc->sc_enaddr[i + 0] | (sc->sc_enaddr[i + 1]) << 8; 1135 CS_WRITE_PACKET_PAGE(sc, PKTPG_IND_ADDR + i, v); 1136 } 1137 1138 if (sc->sc_irq != -1) { 1139 /* Set the interrupt level in the chip */ 1140 if (sc->sc_prodid == PROD_ID_CS8900) { 1141 if (sc->sc_irq == 5) { 1142 CS_WRITE_PACKET_PAGE(sc, PKTPG_INT_NUM, 3); 1143 } else { 1144 CS_WRITE_PACKET_PAGE(sc, PKTPG_INT_NUM, (sc->sc_irq) - 10); 1145 } 1146 } 1147 else { /* CS8920 */ 1148 CS_WRITE_PACKET_PAGE(sc, PKTPG_8920_INT_NUM, sc->sc_irq); 1149 } 1150 } 1151 1152 /* write the multicast mask to the address filter register */ 1153 cs_set_ladr_filt(sc, &sc->sc_ethercom); 1154 1155 /* Enable reception and transmission of frames */ 1156 CS_WRITE_PACKET_PAGE(sc, PKTPG_LINE_CTL, 1157 CS_READ_PACKET_PAGE(sc, PKTPG_LINE_CTL) | 1158 LINE_CTL_RX_ON | LINE_CTL_TX_ON); 1159 1160 /* Enable interrupt at the chip */ 1161 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 1162 CS_READ_PACKET_PAGE(sc, PKTPG_BUS_CTL) | BUS_CTL_INT_ENBL); 1163 } 1164 1165 int 1166 cs_init(struct ifnet *ifp) 1167 { 1168 int intState; 1169 int error = CS_OK; 1170 struct cs_softc *sc = ifp->if_softc; 1171 1172 if (cs_enable(sc)) 1173 goto out; 1174 1175 cs_stop(ifp, 0); 1176 1177 intState = splnet(); 1178 1179 #if 0 1180 /* Mark the interface as down */ 1181 sc->sc_ethercom.ec_if.if_flags &= ~(IFF_UP | IFF_RUNNING); 1182 #endif 1183 1184 #ifdef CS_DEBUG 1185 /* Enable debugging */ 1186 sc->sc_ethercom.ec_if.if_flags |= IFF_DEBUG; 1187 #endif 1188 1189 /* Reset the chip */ 1190 if ((error = cs_reset_chip(sc)) == CS_OK) { 1191 /* Initialize the chip */ 1192 cs_initChip(sc); 1193 1194 /* Mark the interface as running */ 1195 sc->sc_ethercom.ec_if.if_flags |= IFF_RUNNING; 1196 sc->sc_ethercom.ec_if.if_flags &= ~IFF_OACTIVE; 1197 sc->sc_ethercom.ec_if.if_timer = 0; 1198 1199 /* Assume we have carrier until we are told otherwise. */ 1200 sc->sc_carrier = 1; 1201 } else { 1202 aprint_error_dev(sc->sc_dev, "unable to reset chip\n"); 1203 } 1204 1205 splx(intState); 1206 out: 1207 if (error == CS_OK) 1208 return 0; 1209 return EIO; 1210 } 1211 1212 void 1213 cs_set_ladr_filt(struct cs_softc *sc, struct ethercom *ec) 1214 { 1215 struct ifnet *ifp = &ec->ec_if; 1216 struct ether_multi *enm; 1217 struct ether_multistep step; 1218 u_int16_t af[4]; 1219 u_int16_t port, mask, index; 1220 1221 /* 1222 * Set up multicast address filter by passing all multicast addresses 1223 * through a crc generator, and then using the high order 6 bits as an 1224 * index into the 64 bit logical address filter. The high order bit 1225 * selects the word, while the rest of the bits select the bit within 1226 * the word. 1227 */ 1228 if (ifp->if_flags & IFF_PROMISC) { 1229 /* accept all valid frames. */ 1230 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CTL, 1231 RX_CTL_PROMISC_A | RX_CTL_RX_OK_A | 1232 RX_CTL_IND_A | RX_CTL_BCAST_A | RX_CTL_MCAST_A); 1233 ifp->if_flags |= IFF_ALLMULTI; 1234 return; 1235 } 1236 1237 /* 1238 * accept frames if a. crc valid, b. individual address match c. 1239 * broadcast address,and d. multicast addresses matched in the hash 1240 * filter 1241 */ 1242 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CTL, 1243 RX_CTL_RX_OK_A | RX_CTL_IND_A | RX_CTL_BCAST_A | RX_CTL_MCAST_A); 1244 1245 1246 /* 1247 * start off with all multicast flag clear, set it if we need to 1248 * later, otherwise we will leave it. 1249 */ 1250 ifp->if_flags &= ~IFF_ALLMULTI; 1251 af[0] = af[1] = af[2] = af[3] = 0x0000; 1252 1253 /* 1254 * Loop through all the multicast addresses unless we get a range of 1255 * addresses, in which case we will just accept all packets. 1256 * Justification for this is given in the next comment. 1257 */ 1258 ETHER_FIRST_MULTI(step, ec, enm); 1259 while (enm != NULL) { 1260 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1261 sizeof enm->enm_addrlo)) { 1262 /* 1263 * We must listen to a range of multicast addresses. 1264 * For now, just accept all multicasts, rather than 1265 * trying to set only those filter bits needed to match 1266 * the range. (At this time, the only use of address 1267 * ranges is for IP multicast routing, for which the 1268 * range is big enough to require all bits set.) 1269 */ 1270 ifp->if_flags |= IFF_ALLMULTI; 1271 af[0] = af[1] = af[2] = af[3] = 0xffff; 1272 break; 1273 } else { 1274 /* 1275 * we have got an individual address so just set that 1276 * bit. 1277 */ 1278 index = cs_hash_index(enm->enm_addrlo); 1279 1280 /* Set the bit the Logical address filter. */ 1281 port = (u_int16_t) (index >> 4); 1282 mask = (u_int16_t) (1 << (index & 0xf)); 1283 af[port] |= mask; 1284 1285 ETHER_NEXT_MULTI(step, enm); 1286 } 1287 } 1288 1289 /* now program the chip with the addresses */ 1290 CS_WRITE_PACKET_PAGE(sc, PKTPG_LOG_ADDR + 0, af[0]); 1291 CS_WRITE_PACKET_PAGE(sc, PKTPG_LOG_ADDR + 2, af[1]); 1292 CS_WRITE_PACKET_PAGE(sc, PKTPG_LOG_ADDR + 4, af[2]); 1293 CS_WRITE_PACKET_PAGE(sc, PKTPG_LOG_ADDR + 6, af[3]); 1294 return; 1295 } 1296 1297 u_int16_t 1298 cs_hash_index(char *addr) 1299 { 1300 uint32_t crc; 1301 uint16_t hash_code; 1302 1303 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 1304 1305 hash_code = crc >> 26; 1306 return (hash_code); 1307 } 1308 1309 void 1310 cs_reset(struct cs_softc *sc) 1311 { 1312 1313 /* Mark the interface as down */ 1314 sc->sc_ethercom.ec_if.if_flags &= ~IFF_RUNNING; 1315 1316 /* Reset the chip */ 1317 cs_reset_chip(sc); 1318 } 1319 1320 int 1321 cs_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1322 { 1323 struct cs_softc *sc = ifp->if_softc; 1324 struct ifreq *ifr = data; 1325 int state; 1326 int result; 1327 1328 state = splnet(); 1329 1330 result = 0; /* only set if something goes wrong */ 1331 1332 switch (cmd) { 1333 case SIOCGIFMEDIA: 1334 case SIOCSIFMEDIA: 1335 result = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1336 break; 1337 1338 default: 1339 result = ether_ioctl(ifp, cmd, data); 1340 if (result == ENETRESET) { 1341 if (ifp->if_flags & IFF_RUNNING) { 1342 /* 1343 * Multicast list has changed. Set the 1344 * hardware filter accordingly. 1345 */ 1346 cs_set_ladr_filt(sc, &sc->sc_ethercom); 1347 } 1348 result = 0; 1349 } 1350 break; 1351 } 1352 1353 splx(state); 1354 1355 return result; 1356 } 1357 1358 int 1359 cs_mediachange(struct ifnet *ifp) 1360 { 1361 1362 /* 1363 * Current media is already set up. Just reset the interface 1364 * to let the new value take hold. 1365 */ 1366 cs_init(ifp); 1367 return (0); 1368 } 1369 1370 void 1371 cs_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1372 { 1373 struct cs_softc *sc = ifp->if_softc; 1374 1375 /* 1376 * The currently selected media is always the active media. 1377 */ 1378 ifmr->ifm_active = sc->sc_media.ifm_cur->ifm_media; 1379 1380 if (ifp->if_flags & IFF_UP) { 1381 /* Interface up, status is valid. */ 1382 ifmr->ifm_status = IFM_AVALID | 1383 (sc->sc_carrier ? IFM_ACTIVE : 0); 1384 } 1385 else ifmr->ifm_status = 0; 1386 } 1387 1388 int 1389 cs_intr(void *arg) 1390 { 1391 struct cs_softc *sc = arg; 1392 u_int16_t Event; 1393 #if NRND > 0 1394 u_int16_t rndEvent; 1395 #endif 1396 1397 /*printf("cs_intr %p\n", sc);*/ 1398 /* Ignore any interrupts that happen while the chip is being reset */ 1399 if (sc->sc_resetting) { 1400 printf("%s: cs_intr: reset in progress\n", 1401 device_xname(sc->sc_dev)); 1402 return 1; 1403 } 1404 1405 /* Read an event from the Interrupt Status Queue */ 1406 if (sc->sc_memorymode) 1407 Event = CS_READ_PACKET_PAGE(sc, PKTPG_ISQ); 1408 else 1409 Event = CS_READ_PORT(sc, PORT_ISQ); 1410 1411 if ((Event & REG_NUM_MASK) == 0 || Event == 0xffff) 1412 return 0; /* not ours */ 1413 1414 #if NRND > 0 1415 rndEvent = Event; 1416 #endif 1417 1418 /* Process all the events in the Interrupt Status Queue */ 1419 while ((Event & REG_NUM_MASK) != 0 && Event != 0xffff) { 1420 /* Dispatch to an event handler based on the register number */ 1421 switch (Event & REG_NUM_MASK) { 1422 case REG_NUM_RX_EVENT: 1423 cs_receive_event(sc, Event); 1424 break; 1425 case REG_NUM_TX_EVENT: 1426 cs_transmit_event(sc, Event); 1427 break; 1428 case REG_NUM_BUF_EVENT: 1429 cs_buffer_event(sc, Event); 1430 break; 1431 case REG_NUM_TX_COL: 1432 case REG_NUM_RX_MISS: 1433 cs_counter_event(sc, Event); 1434 break; 1435 default: 1436 printf("%s: unknown interrupt event 0x%x\n", 1437 device_xname(sc->sc_dev), Event); 1438 break; 1439 } 1440 1441 /* Read another event from the Interrupt Status Queue */ 1442 if (sc->sc_memorymode) 1443 Event = CS_READ_PACKET_PAGE(sc, PKTPG_ISQ); 1444 else 1445 Event = CS_READ_PORT(sc, PORT_ISQ); 1446 } 1447 1448 /* have handled the interrupt */ 1449 #if NRND > 0 1450 rnd_add_uint32(&sc->rnd_source, rndEvent); 1451 #endif 1452 return 1; 1453 } 1454 1455 void 1456 cs_counter_event(struct cs_softc *sc, u_int16_t cntEvent) 1457 { 1458 struct ifnet *ifp; 1459 u_int16_t errorCount; 1460 1461 ifp = &sc->sc_ethercom.ec_if; 1462 1463 switch (cntEvent & REG_NUM_MASK) { 1464 case REG_NUM_TX_COL: 1465 /* 1466 * the count should be read before an overflow occurs. 1467 */ 1468 errorCount = CS_READ_PACKET_PAGE(sc, PKTPG_TX_COL); 1469 /* 1470 * the tramsit event routine always checks the number of 1471 * collisions for any packet so we don't increment any 1472 * counters here, as they should already have been 1473 * considered. 1474 */ 1475 break; 1476 case REG_NUM_RX_MISS: 1477 /* 1478 * the count should be read before an overflow occurs. 1479 */ 1480 errorCount = CS_READ_PACKET_PAGE(sc, PKTPG_RX_MISS); 1481 /* 1482 * Increment the input error count, the first 6bits are the 1483 * register id. 1484 */ 1485 ifp->if_ierrors += ((errorCount & 0xffC0) >> 6); 1486 break; 1487 default: 1488 /* do nothing */ 1489 break; 1490 } 1491 } 1492 1493 void 1494 cs_buffer_event(struct cs_softc *sc, u_int16_t bufEvent) 1495 { 1496 1497 /* 1498 * multiple events can be in the buffer event register at one time so 1499 * a standard switch statement will not suffice, here every event 1500 * must be checked. 1501 */ 1502 1503 /* 1504 * if 128 bits have been rxed by the time we get here, the dest event 1505 * will be cleared and 128 event will be set. 1506 */ 1507 if ((bufEvent & (BUF_EVENT_RX_DEST | BUF_EVENT_RX_128)) != 0) { 1508 cs_process_rx_early(sc); 1509 } 1510 1511 if (bufEvent & BUF_EVENT_RX_DMA) { 1512 /* process the receive data */ 1513 if (sc->sc_dma_process_rx) 1514 (*sc->sc_dma_process_rx)(sc); 1515 else 1516 /* should panic? */ 1517 aprint_error_dev(sc->sc_dev, "unexpected DMA event\n"); 1518 } 1519 1520 if (bufEvent & BUF_EVENT_TX_UNDR) { 1521 #if 0 1522 /* 1523 * This can happen occasionally, and it's not worth worrying 1524 * about. 1525 */ 1526 printf("%s: transmit underrun (%d -> %d)\n", 1527 device_xname(sc->sc_dev), sc->sc_xe_ent, 1528 cs_xmit_early_table[sc->sc_xe_ent].worse); 1529 #endif 1530 sc->sc_xe_ent = cs_xmit_early_table[sc->sc_xe_ent].worse; 1531 sc->sc_xe_togo = 1532 cs_xmit_early_table[sc->sc_xe_ent].better_count; 1533 1534 /* had an underrun, transmit is finished */ 1535 sc->sc_txbusy = FALSE; 1536 } 1537 1538 if (bufEvent & BUF_EVENT_SW_INT) { 1539 printf("%s: software initiated interrupt\n", 1540 device_xname(sc->sc_dev)); 1541 } 1542 } 1543 1544 void 1545 cs_transmit_event(struct cs_softc *sc, u_int16_t txEvent) 1546 { 1547 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1548 1549 /* If there were any errors transmitting this frame */ 1550 if (txEvent & (TX_EVENT_LOSS_CRS | TX_EVENT_SQE_ERR | TX_EVENT_OUT_WIN | 1551 TX_EVENT_JABBER | TX_EVENT_16_COLL)) { 1552 /* Increment the output error count */ 1553 ifp->if_oerrors++; 1554 1555 /* Note carrier loss. */ 1556 if (txEvent & TX_EVENT_LOSS_CRS) 1557 sc->sc_carrier = 0; 1558 1559 /* If debugging is enabled then log error messages */ 1560 if (ifp->if_flags & IFF_DEBUG) { 1561 if (txEvent & TX_EVENT_LOSS_CRS) { 1562 aprint_error_dev(sc->sc_dev, "lost carrier\n"); 1563 } 1564 if (txEvent & TX_EVENT_SQE_ERR) { 1565 aprint_error_dev(sc->sc_dev, "SQE error\n"); 1566 } 1567 if (txEvent & TX_EVENT_OUT_WIN) { 1568 aprint_error_dev(sc->sc_dev, 1569 "out-of-window collision\n"); 1570 } 1571 if (txEvent & TX_EVENT_JABBER) { 1572 aprint_error_dev(sc->sc_dev, "jabber\n"); 1573 } 1574 if (txEvent & TX_EVENT_16_COLL) { 1575 aprint_error_dev(sc->sc_dev, "16 collisions\n"); 1576 } 1577 } 1578 } 1579 else { 1580 /* Transmission successful, carrier is up. */ 1581 sc->sc_carrier = 1; 1582 #ifdef SHARK 1583 ledNetActive(); 1584 #endif 1585 } 1586 1587 /* Add the number of collisions for this frame */ 1588 if (txEvent & TX_EVENT_16_COLL) { 1589 ifp->if_collisions += 16; 1590 } else { 1591 ifp->if_collisions += ((txEvent & TX_EVENT_COLL_MASK) >> 11); 1592 } 1593 1594 ifp->if_opackets++; 1595 1596 /* Transmission is no longer in progress */ 1597 sc->sc_txbusy = FALSE; 1598 1599 /* If there is more to transmit */ 1600 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) { 1601 /* Start the next transmission */ 1602 cs_start_output(ifp); 1603 } 1604 } 1605 1606 void 1607 cs_print_rx_errors(struct cs_softc *sc, u_int16_t rxEvent) 1608 { 1609 1610 if (rxEvent & RX_EVENT_RUNT) 1611 aprint_error_dev(sc->sc_dev, "runt\n"); 1612 1613 if (rxEvent & RX_EVENT_X_DATA) 1614 aprint_error_dev(sc->sc_dev, "extra data\n"); 1615 1616 if (rxEvent & RX_EVENT_CRC_ERR) { 1617 if (rxEvent & RX_EVENT_DRIBBLE) 1618 aprint_error_dev(sc->sc_dev, "alignment error\n"); 1619 else 1620 aprint_error_dev(sc->sc_dev, "CRC error\n"); 1621 } else { 1622 if (rxEvent & RX_EVENT_DRIBBLE) 1623 aprint_error_dev(sc->sc_dev, "dribble bits\n"); 1624 } 1625 } 1626 1627 void 1628 cs_receive_event(struct cs_softc *sc, u_int16_t rxEvent) 1629 { 1630 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1631 1632 /* If the frame was not received OK */ 1633 if (!(rxEvent & RX_EVENT_RX_OK)) { 1634 /* Increment the input error count */ 1635 ifp->if_ierrors++; 1636 1637 /* 1638 * If debugging is enabled then log error messages. 1639 */ 1640 if (ifp->if_flags & IFF_DEBUG) { 1641 if (rxEvent != REG_NUM_RX_EVENT) { 1642 cs_print_rx_errors(sc, rxEvent); 1643 1644 /* 1645 * Must read the length of all received 1646 * frames 1647 */ 1648 CS_READ_PACKET_PAGE(sc, PKTPG_RX_LENGTH); 1649 1650 /* Skip the received frame */ 1651 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 1652 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | 1653 RX_CFG_SKIP); 1654 } else { 1655 aprint_error_dev(sc->sc_dev, "implied skip\n"); 1656 } 1657 } 1658 } else { 1659 /* 1660 * process the received frame and pass it up to the upper 1661 * layers. 1662 */ 1663 cs_process_receive(sc); 1664 } 1665 } 1666 1667 void 1668 cs_ether_input(struct cs_softc *sc, struct mbuf *m) 1669 { 1670 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1671 1672 ifp->if_ipackets++; 1673 1674 /* 1675 * Check if there's a BPF listener on this interface. 1676 * If so, hand off the raw packet to BPF. 1677 */ 1678 bpf_mtap(ifp, m); 1679 1680 /* Pass the packet up. */ 1681 (*ifp->if_input)(ifp, m); 1682 } 1683 1684 void 1685 cs_process_receive(struct cs_softc *sc) 1686 { 1687 struct ifnet *ifp; 1688 struct mbuf *m; 1689 int totlen; 1690 u_int16_t *pBuff, *pBuffLimit; 1691 int pad; 1692 unsigned int frameOffset = 0; /* XXX: gcc */ 1693 1694 #ifdef SHARK 1695 ledNetActive(); 1696 #endif 1697 1698 ifp = &sc->sc_ethercom.ec_if; 1699 1700 /* Received a packet; carrier is up. */ 1701 sc->sc_carrier = 1; 1702 1703 if (sc->sc_memorymode) { 1704 /* Initialize the frame offset */ 1705 frameOffset = PKTPG_RX_LENGTH; 1706 1707 /* Get the length of the received frame */ 1708 totlen = CS_READ_PACKET_PAGE(sc, frameOffset); 1709 frameOffset += 2; 1710 } 1711 else { 1712 /* drop status */ 1713 CS_READ_PORT(sc, PORT_RXTX_DATA); 1714 1715 /* Get the length of the received frame */ 1716 totlen = CS_READ_PORT(sc, PORT_RXTX_DATA); 1717 } 1718 1719 if (totlen > ETHER_MAX_LEN) { 1720 aprint_error_dev(sc->sc_dev, "invalid packet length %d\n", 1721 totlen); 1722 1723 /* skip the received frame */ 1724 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 1725 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP); 1726 return; 1727 } 1728 1729 MGETHDR(m, M_DONTWAIT, MT_DATA); 1730 if (m == 0) { 1731 aprint_error_dev(sc->sc_dev, 1732 "cs_process_receive: unable to allocate mbuf\n"); 1733 ifp->if_ierrors++; 1734 /* 1735 * couldn't allocate an mbuf so things are not good, may as 1736 * well drop the packet I think. 1737 * 1738 * have already read the length so we should be right to skip 1739 * the packet. 1740 */ 1741 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 1742 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP); 1743 return; 1744 } 1745 m->m_pkthdr.rcvif = ifp; 1746 m->m_pkthdr.len = totlen; 1747 1748 /* number of bytes to align ip header on word boundary for ipintr */ 1749 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 1750 1751 /* 1752 * alloc mbuf cluster if we need. 1753 * we need 1 byte spare because following 1754 * packet read loop can overrun. 1755 */ 1756 if (totlen + pad + 1 > MHLEN) { 1757 MCLGET(m, M_DONTWAIT); 1758 if ((m->m_flags & M_EXT) == 0) { 1759 /* couldn't allocate an mbuf cluster */ 1760 aprint_error_dev(sc->sc_dev, 1761 "cs_process_receive: " 1762 "unable to allocate a cluster\n"); 1763 m_freem(m); 1764 1765 /* skip the received frame */ 1766 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 1767 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP); 1768 return; 1769 } 1770 } 1771 1772 /* align ip header on word boundary for ipintr */ 1773 m->m_data += pad; 1774 1775 m->m_len = totlen; 1776 pBuff = mtod(m, u_int16_t *); 1777 1778 /* now read the data from the chip */ 1779 if (sc->sc_memorymode) { 1780 pBuffLimit = pBuff + (totlen + 1) / 2; /* don't want to go over */ 1781 while (pBuff < pBuffLimit) { 1782 *pBuff++ = CS_READ_PACKET_PAGE(sc, frameOffset); 1783 frameOffset += 2; 1784 } 1785 } 1786 else { 1787 IO_READ_MULTI_2(sc, PORT_RXTX_DATA, pBuff, (totlen + 1)>>1); 1788 } 1789 1790 cs_ether_input(sc, m); 1791 } 1792 1793 void 1794 cs_process_rx_early(struct cs_softc *sc) 1795 { 1796 struct ifnet *ifp; 1797 struct mbuf *m; 1798 u_int16_t frameCount, oldFrameCount; 1799 u_int16_t rxEvent; 1800 u_int16_t *pBuff; 1801 int pad; 1802 unsigned int frameOffset; 1803 1804 1805 ifp = &sc->sc_ethercom.ec_if; 1806 1807 /* Initialize the frame offset */ 1808 frameOffset = PKTPG_RX_FRAME; 1809 frameCount = 0; 1810 1811 MGETHDR(m, M_DONTWAIT, MT_DATA); 1812 if (m == 0) { 1813 aprint_error_dev(sc->sc_dev, 1814 "cs_process_rx_early: unable to allocate mbuf\n"); 1815 ifp->if_ierrors++; 1816 /* 1817 * couldn't allocate an mbuf so things are not good, may as 1818 * well drop the packet I think. 1819 * 1820 * have already read the length so we should be right to skip 1821 * the packet. 1822 */ 1823 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 1824 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP); 1825 return; 1826 } 1827 m->m_pkthdr.rcvif = ifp; 1828 /* 1829 * save processing by always using a mbuf cluster, guaranteed to fit 1830 * packet 1831 */ 1832 MCLGET(m, M_DONTWAIT); 1833 if ((m->m_flags & M_EXT) == 0) { 1834 /* couldn't allocate an mbuf cluster */ 1835 aprint_error_dev(sc->sc_dev, 1836 "cs_process_rx_early: unable to allocate a cluster\n"); 1837 m_freem(m); 1838 /* skip the frame */ 1839 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 1840 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP); 1841 return; 1842 } 1843 1844 /* align ip header on word boundary for ipintr */ 1845 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 1846 m->m_data += pad; 1847 1848 /* set up the buffer pointer to point to the data area */ 1849 pBuff = mtod(m, u_int16_t *); 1850 1851 /* 1852 * now read the frame byte counter until we have finished reading the 1853 * frame 1854 */ 1855 oldFrameCount = 0; 1856 frameCount = CS_READ_PACKET_PAGE(sc, PKTPG_FRAME_BYTE_COUNT); 1857 while ((frameCount != 0) && (frameCount < MCLBYTES)) { 1858 for (; oldFrameCount < frameCount; oldFrameCount += 2) { 1859 *pBuff++ = CS_READ_PACKET_PAGE(sc, frameOffset); 1860 frameOffset += 2; 1861 } 1862 1863 /* read the new count from the chip */ 1864 frameCount = CS_READ_PACKET_PAGE(sc, PKTPG_FRAME_BYTE_COUNT); 1865 } 1866 1867 /* update the mbuf counts */ 1868 m->m_len = oldFrameCount; 1869 m->m_pkthdr.len = oldFrameCount; 1870 1871 /* now check the Rx Event register */ 1872 rxEvent = CS_READ_PACKET_PAGE(sc, PKTPG_RX_EVENT); 1873 1874 if ((rxEvent & RX_EVENT_RX_OK) != 0) { 1875 /* 1876 * do an implied skip, it seems to be more reliable than a 1877 * forced skip. 1878 */ 1879 rxEvent = CS_READ_PACKET_PAGE(sc, PKTPG_RX_STATUS); 1880 rxEvent = CS_READ_PACKET_PAGE(sc, PKTPG_RX_LENGTH); 1881 1882 /* 1883 * now read the RX_EVENT register to perform an implied skip. 1884 */ 1885 rxEvent = CS_READ_PACKET_PAGE(sc, PKTPG_RX_EVENT); 1886 1887 cs_ether_input(sc, m); 1888 } else { 1889 m_freem(m); 1890 ifp->if_ierrors++; 1891 } 1892 } 1893 1894 void 1895 cs_start_output(struct ifnet *ifp) 1896 { 1897 struct cs_softc *sc; 1898 struct mbuf *pMbuf; 1899 struct mbuf *pMbufChain; 1900 u_int16_t BusStatus; 1901 u_int16_t Length; 1902 int txLoop = 0; 1903 int dropout = 0; 1904 1905 sc = ifp->if_softc; 1906 1907 /* check that the interface is up and running */ 1908 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) { 1909 return; 1910 } 1911 1912 /* Don't interrupt a transmission in progress */ 1913 if (sc->sc_txbusy) { 1914 return; 1915 } 1916 1917 /* this loop will only run through once if transmission is successful */ 1918 /* 1919 * While there are packets to transmit and a transmit is not in 1920 * progress 1921 */ 1922 while (sc->sc_txbusy == 0 && dropout == 0) { 1923 IFQ_DEQUEUE(&ifp->if_snd, pMbufChain); 1924 if (pMbufChain == NULL) 1925 break; 1926 1927 /* 1928 * If BPF is listening on this interface, let it see the packet 1929 * before we commit it to the wire. 1930 */ 1931 bpf_mtap(ifp, pMbufChain); 1932 1933 /* Find the total length of the data to transmit */ 1934 Length = 0; 1935 for (pMbuf = pMbufChain; pMbuf != NULL; pMbuf = pMbuf->m_next) 1936 Length += pMbuf->m_len; 1937 1938 do { 1939 /* 1940 * Request that the transmit be started after all 1941 * data has been copied 1942 * 1943 * In IO mode must write to the IO port not the packet 1944 * page address 1945 * 1946 * If this is changed to start transmission after a 1947 * small amount of data has been copied you tend to 1948 * get packet missed errors i think because the ISA 1949 * bus is too slow. Or possibly the copy routine is 1950 * not streamlined enough. 1951 */ 1952 if (sc->sc_memorymode) { 1953 CS_WRITE_PACKET_PAGE(sc, PKTPG_TX_CMD, 1954 cs_xmit_early_table[sc->sc_xe_ent].txcmd); 1955 CS_WRITE_PACKET_PAGE(sc, PKTPG_TX_LENGTH, Length); 1956 } 1957 else { 1958 CS_WRITE_PORT(sc, PORT_TX_CMD, 1959 cs_xmit_early_table[sc->sc_xe_ent].txcmd); 1960 CS_WRITE_PORT(sc, PORT_TX_LENGTH, Length); 1961 } 1962 1963 /* 1964 * Adjust early-transmit machinery. 1965 */ 1966 if (--sc->sc_xe_togo == 0) { 1967 sc->sc_xe_ent = 1968 cs_xmit_early_table[sc->sc_xe_ent].better; 1969 sc->sc_xe_togo = 1970 cs_xmit_early_table[sc->sc_xe_ent].better_count; 1971 } 1972 /* 1973 * Read the BusStatus register which indicates 1974 * success of the request 1975 */ 1976 BusStatus = CS_READ_PACKET_PAGE(sc, PKTPG_BUS_ST); 1977 1978 /* 1979 * If there was an error in the transmit bid free the 1980 * mbuf and go on. This is presuming that mbuf is 1981 * corrupt. 1982 */ 1983 if (BusStatus & BUS_ST_TX_BID_ERR) { 1984 aprint_error_dev(sc->sc_dev, 1985 "transmit bid error (too big)"); 1986 1987 /* Discard the bad mbuf chain */ 1988 m_freem(pMbufChain); 1989 sc->sc_ethercom.ec_if.if_oerrors++; 1990 1991 /* Loop up to transmit the next chain */ 1992 txLoop = 0; 1993 } else { 1994 if (BusStatus & BUS_ST_RDY4TXNOW) { 1995 /* 1996 * The chip is ready for transmission 1997 * now 1998 */ 1999 /* 2000 * Copy the frame to the chip to 2001 * start transmission 2002 */ 2003 cs_copy_tx_frame(sc, pMbufChain); 2004 2005 /* Free the mbuf chain */ 2006 m_freem(pMbufChain); 2007 2008 /* Transmission is now in progress */ 2009 sc->sc_txbusy = TRUE; 2010 txLoop = 0; 2011 } else { 2012 /* 2013 * if we get here we want to try 2014 * again with the same mbuf, until 2015 * the chip lets us transmit. 2016 */ 2017 txLoop++; 2018 if (txLoop > CS_OUTPUT_LOOP_MAX) { 2019 /* Free the mbuf chain */ 2020 m_freem(pMbufChain); 2021 /* 2022 * Transmission is not in 2023 * progress 2024 */ 2025 sc->sc_txbusy = FALSE; 2026 /* 2027 * Increment the output error 2028 * count 2029 */ 2030 ifp->if_oerrors++; 2031 /* 2032 * exit the routine and drop 2033 * the packet. 2034 */ 2035 txLoop = 0; 2036 dropout = 1; 2037 } 2038 } 2039 } 2040 } while (txLoop); 2041 } 2042 } 2043 2044 void 2045 cs_copy_tx_frame(struct cs_softc *sc, struct mbuf *m0) 2046 { 2047 struct mbuf *m; 2048 int len, leftover, frameoff; 2049 u_int16_t dbuf; 2050 u_int8_t *p; 2051 #ifdef DIAGNOSTIC 2052 u_int8_t *lim; 2053 #endif 2054 2055 /* Initialize frame pointer and data port address */ 2056 frameoff = PKTPG_TX_FRAME; 2057 2058 /* start out with no leftover data */ 2059 leftover = 0; 2060 dbuf = 0; 2061 2062 /* Process the chain of mbufs */ 2063 for (m = m0; m != NULL; m = m->m_next) { 2064 /* 2065 * Process all of the data in a single mbuf. 2066 */ 2067 p = mtod(m, u_int8_t *); 2068 len = m->m_len; 2069 #ifdef DIAGNOSTIC 2070 lim = p + len; 2071 #endif 2072 2073 while (len > 0) { 2074 if (leftover) { 2075 /* 2076 * Data left over (from mbuf or realignment). 2077 * Buffer the next byte, and write it and 2078 * the leftover data out. 2079 */ 2080 dbuf |= *p++ << 8; 2081 len--; 2082 if (sc->sc_memorymode) { 2083 CS_WRITE_PACKET_PAGE(sc, frameoff, dbuf); 2084 frameoff += 2; 2085 } 2086 else { 2087 CS_WRITE_PORT(sc, PORT_RXTX_DATA, dbuf); 2088 } 2089 leftover = 0; 2090 } else if ((long) p & 1) { 2091 /* 2092 * Misaligned data. Buffer the next byte. 2093 */ 2094 dbuf = *p++; 2095 len--; 2096 leftover = 1; 2097 } else { 2098 /* 2099 * Aligned data. This is the case we like. 2100 * 2101 * Write-region out as much as we can, then 2102 * buffer the remaining byte (if any). 2103 */ 2104 leftover = len & 1; 2105 len &= ~1; 2106 if (sc->sc_memorymode) { 2107 MEM_WRITE_REGION_2(sc, frameoff, 2108 (u_int16_t *) p, len >> 1); 2109 frameoff += len; 2110 } 2111 else { 2112 IO_WRITE_MULTI_2(sc, 2113 PORT_RXTX_DATA, (u_int16_t *)p, len >> 1); 2114 } 2115 p += len; 2116 2117 if (leftover) 2118 dbuf = *p++; 2119 len = 0; 2120 } 2121 } 2122 if (len < 0) 2123 panic("cs_copy_tx_frame: negative len"); 2124 #ifdef DIAGNOSTIC 2125 if (p != lim) 2126 panic("cs_copy_tx_frame: p != lim"); 2127 #endif 2128 } 2129 if (leftover) { 2130 if (sc->sc_memorymode) { 2131 CS_WRITE_PACKET_PAGE(sc, frameoff, dbuf); 2132 } 2133 else { 2134 CS_WRITE_PORT(sc, PORT_RXTX_DATA, dbuf); 2135 } 2136 } 2137 } 2138 2139 static int 2140 cs_enable(struct cs_softc *sc) 2141 { 2142 2143 if (CS_IS_ENABLED(sc) == 0) { 2144 if (sc->sc_enable != NULL) { 2145 int error; 2146 2147 error = (*sc->sc_enable)(sc); 2148 if (error) 2149 return (error); 2150 } 2151 sc->sc_cfgflags |= CFGFLG_ENABLED; 2152 } 2153 2154 return (0); 2155 } 2156 2157 static void 2158 cs_disable(struct cs_softc *sc) 2159 { 2160 2161 if (CS_IS_ENABLED(sc)) { 2162 if (sc->sc_disable != NULL) 2163 (*sc->sc_disable)(sc); 2164 2165 sc->sc_cfgflags &= ~CFGFLG_ENABLED; 2166 } 2167 } 2168 2169 static void 2170 cs_stop(struct ifnet *ifp, int disable) 2171 { 2172 struct cs_softc *sc = ifp->if_softc; 2173 2174 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 0); 2175 CS_WRITE_PACKET_PAGE(sc, PKTPG_TX_CFG, 0); 2176 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUF_CFG, 0); 2177 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 0); 2178 2179 if (disable) { 2180 cs_disable(sc); 2181 } 2182 2183 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2184 } 2185 2186 int 2187 cs_activate(device_t self, enum devact act) 2188 { 2189 struct cs_softc *sc = device_private(self); 2190 2191 switch (act) { 2192 case DVACT_DEACTIVATE: 2193 if_deactivate(&sc->sc_ethercom.ec_if); 2194 return 0; 2195 default: 2196 return EOPNOTSUPP; 2197 } 2198 } 2199