1 /* $NetBSD: cs89x0reg.h,v 1.1 2001/11/26 19:17:08 yamt Exp $ */ 2 3 /* 4 * Copyright 1997 5 * Digital Equipment Corporation. All rights reserved. 6 * 7 * This software is furnished under license and may be used and 8 * copied only in accordance with the following terms and conditions. 9 * Subject to these conditions, you may download, copy, install, 10 * use, modify and distribute this software in source and/or binary 11 * form. No title or ownership is transferred hereby. 12 * 13 * 1) Any source code used, modified or distributed must reproduce 14 * and retain this copyright notice and list of conditions as 15 * they appear in the source file. 16 * 17 * 2) No right is granted to use any trade name, trademark, or logo of 18 * Digital Equipment Corporation. Neither the "Digital Equipment 19 * Corporation" name nor any trademark or logo of Digital Equipment 20 * Corporation may be used to endorse or promote products derived 21 * from this software without the prior written permission of 22 * Digital Equipment Corporation. 23 * 24 * 3) This software is provided "AS-IS" and any express or implied 25 * warranties, including but not limited to, any implied warranties 26 * of merchantability, fitness for a particular purpose, or 27 * non-infringement are disclaimed. In no event shall DIGITAL be 28 * liable for any damages whatsoever, and in particular, DIGITAL 29 * shall not be liable for special, indirect, consequential, or 30 * incidental damages or damages for lost profits, loss of 31 * revenue or loss of use, whether such damages arise in contract, 32 * negligence, tort, under statute, in equity, at law or otherwise, 33 * even if advised of the possibility of such damage. 34 */ 35 36 /* 37 **++ 38 ** FACILITY Crystal CS8900 Ethernet driver register description 39 ** 40 ** ABSTRACT 41 ** 42 ** This module provides CS8900 register definitions 43 ** 44 ** AUTHORS 45 ** 46 ** Peter Dettori SEA - Software Engineering. 47 ** 48 ** CREATION DATE: 49 ** 50 ** 13-Feb-1997. 51 ** 52 ** MODIFICATION HISTORY: 53 ** 54 **-- 55 */ 56 57 #ifndef _DEV_IC_CS89X0REG_H_ 58 #define _DEV_IC_CS89X0REG_H_ 59 60 /* 61 * The CS8900 has 8 2-byte registers in I/O space. 62 */ 63 #define CS8900_IOSIZE 16 64 65 /* 66 * The CS8900 has a 4k memory space. 67 */ 68 #define CS8900_MEMSIZE 4096 69 70 /* 71 * Size of the DMA area used for packet reception. 72 */ 73 #if 0 74 #define CS8900_DMASIZE (64*1024) 75 #else 76 #define CS8900_DMASIZE (16*1024) 77 #endif 78 79 /* 80 * Validate various parameters. 81 */ 82 #define CS8900_MEMBASE_ISVALID(x) (((x) & (CS8900_MEMSIZE - 1)) == 0) 83 #define CS8900_IRQ_ISVALID(x) ((x) == 5 || (x) == 10 || \ 84 (x) == 11 || (x) == 12) 85 86 /* Chip Identification (PacketPage registers) */ 87 88 #define EISA_NUM_CRYSTAL 0x630E 89 #define PROD_ID_MASK 0xE000 90 #define PROD_ID_CS8900 0x0000 91 #define PROD_ID_CS8920 0x4000 92 #define PROD_ID_CS8920M 0x6000 93 #define PROD_REV_MASK 0x1F00 94 95 96 /* IO Port Offsets */ 97 98 #define PORT_RXTX_DATA 0x0000 99 #define PORT_RXTX_DATA_1 0x0002 100 #define PORT_TX_CMD 0x0004 101 #define PORT_TX_LENGTH 0x0006 102 #define PORT_ISQ 0x0008 103 #define PORT_PKTPG_PTR 0x000A 104 #define PORT_PKTPG_DATA 0x000C 105 #define PORT_PKTPG_DATA_1 0x000E 106 107 108 /* PacketPage Offsets */ 109 110 #define PKTPG_EISA_NUM 0x0000 111 #define PKTPG_PRODUCT_ID 0x0002 112 #define PKTPG_IO_BASE 0x0020 113 #define PKTPG_INT_NUM 0x0022 114 #define PKTPG_DMA_CHANNEL 0x0024 115 #define PKTPG_DMA_START_FRAME 0x0026 116 #define PKTPG_DMA_FRAME_COUNT 0x0028 117 #define PKTPG_DMA_BYTE_COUNT 0x002A 118 #define PKTPG_MEM_BASE 0x002C 119 #define PKTPG_EEPROM_CMD 0x0040 120 #define PKTPG_EEPROM_DATA 0x0042 121 #define PKTPG_FRAME_BYTE_COUNT 0x0050 122 #define PKTPG_RX_CFG 0x0102 123 #define PKTPG_RX_CTL 0x0104 124 #define PKTPG_TX_CFG 0x0106 125 #define PKTPG_BUF_CFG 0x010A 126 #define PKTPG_LINE_CTL 0x0112 127 #define PKTPG_SELF_CTL 0x0114 128 #define PKTPG_BUS_CTL 0x0116 129 #define PKTPG_TEST_CTL 0x0118 130 #define PKTPG_AUTONEG_CTL 0x011C 131 #define PKTPG_ISQ 0x0120 132 #define PKTPG_RX_EVENT 0x0124 133 #define PKTPG_TX_EVENT 0x0128 134 #define PKTPG_BUF_EVENT 0x012C 135 #define PKTPG_RX_MISS 0x0130 136 #define PKTPG_TX_COL 0x0132 137 #define PKTPG_LINE_ST 0x0134 138 #define PKTPG_SELF_ST 0x0136 139 #define PKTPG_BUS_ST 0x0138 140 #define PKTPG_TDR 0x013c 141 #define PKTPG_AUTONEG_ST 0x013e 142 #define PKTPG_TX_CMD 0x0144 143 #define PKTPG_TX_LENGTH 0x0146 144 #define PKTPG_LOG_ADDR 0x0150 /* logical address filter hash tbl */ 145 #define PKTPG_IND_ADDR 0x0158 146 #define PKTPG_8920_INT_NUM 0x0370 147 #define PKTPG_8920_DMA_CHANNEL 0x0374 148 #define PKTPG_RX_STATUS 0x0400 149 #define PKTPG_RX_LENGTH 0x0402 150 #define PKTPG_RX_FRAME 0x0404 151 #define PKTPG_TX_FRAME 0x0A00 152 153 154 /* EEPROM Offsets */ 155 156 #define EEPROM_IND_ADDR_H 0x001C 157 #define EEPROM_IND_ADDR_M 0x001D 158 #define EEPROM_IND_ADDR_L 0x001E 159 #define EEPROM_ISA_CFG 0x001F 160 #define EEPROM_MEM_BASE 0x0020 161 #define EEPROM_XMIT_CTL 0x0023 162 #define EEPROM_ADPTR_CFG 0x0024 163 164 165 /* Register Numbers */ 166 167 #define REG_NUM_MASK 0x003F 168 #define REG_NUM_RX_EVENT 0x0004 169 #define REG_NUM_TX_EVENT 0x0008 170 #define REG_NUM_BUF_EVENT 0x000C 171 #define REG_NUM_RX_MISS 0x0010 172 #define REG_NUM_TX_COL 0x0012 173 174 175 /* Self Control Register */ 176 177 #define SELF_CTL_RESET 0x0040 178 #define SELF_CTL_HC1E 0x2000 179 #define SELF_CTL_HCB1 0x8000 180 181 182 /* Self Status Register */ 183 184 #define SELF_ST_INIT_DONE 0x0080 185 #define SELF_ST_SI_BUSY 0x0100 186 #define SELF_ST_EEP_PRES 0x0200 187 #define SELF_ST_EEP_OK 0x0400 188 #define SELF_ST_EL_PRES 0x0800 189 190 191 /* EEPROM Command Register */ 192 193 #define EEPROM_CMD_READ 0x0200 194 #define EEPROM_CMD_ELSEL 0x0400 195 196 197 /* Bus Control Register */ 198 199 #define BUS_CTL_RESET_DMA 0x0040 200 #define BUS_CTL_USE_SA 0x0200 201 #define BUS_CTL_MEM_MODE 0x0400 202 #define BUS_CTL_DMA_BURST 0x0800 203 #define BUS_CTL_IOCHRDY 0x1000 204 #define BUS_CTL_DMA_SIZE 0x2000 205 #define BUS_CTL_INT_ENBL 0x8000 206 207 208 /* Bus Status Register */ 209 210 #define BUS_ST_TX_BID_ERR 0x0080 211 #define BUS_ST_RDY4TXNOW 0x0100 212 213 214 /* Line Control Register */ 215 216 #define LINE_CTL_RX_ON 0x0040 217 #define LINE_CTL_TX_ON 0x0080 218 #define LINE_CTL_AUI_ONLY 0x0100 219 #define LINE_CTL_10BASET 0x0000 220 #define LINE_CTL_AUTO_SEL 0x0200 221 222 223 /* Test Control Register */ 224 225 #define TEST_CTL_DIS_LT 0x0080 226 #define TEST_CTL_ENDEC_LP 0x0200 227 #define TEST_CTL_AUI_LOOP 0x0400 228 #define TEST_CTL_DIS_BKOFF 0x0800 229 #define TEST_CTL_FDX 0x4000 230 231 232 /* Receiver Configuration Register */ 233 234 #define RX_CFG_SKIP 0x0040 235 #define RX_CFG_RX_OK_IE 0x0100 236 #define RX_CFG_RX_DMA_ONLY 0x0200 237 #define RX_CFG_CRC_ERR_IE 0x1000 238 #define RX_CFG_RUNT_IE 0x2000 239 #define RX_CFG_X_DATA_IE 0x4000 240 #define RX_CFG_ALL_IE 0x7100 241 242 243 /* Receiver Event Register */ 244 245 #define RX_EVENT_DRIBBLE 0x0080 246 #define RX_EVENT_RX_OK 0x0100 247 #define RX_EVENT_IND_ADDR 0x0400 248 #define RX_EVENT_BCAST 0x0800 249 #define RX_EVENT_CRC_ERR 0x1000 250 #define RX_EVENT_RUNT 0x2000 251 #define RX_EVENT_X_DATA 0x4000 252 253 254 /* Receiver Control Register */ 255 256 #define RX_CTL_INDHASH_A 0x0040 257 #define RX_CTL_PROMISC_A 0x0080 258 #define RX_CTL_RX_OK_A 0x0100 259 #define RX_CTL_MCAST_A 0x0200 260 #define RX_CTL_IND_A 0x0400 261 #define RX_CTL_BCAST_A 0x0800 262 #define RX_CTL_CRC_ERR_A 0x1000 263 #define RX_CTL_RUNT_A 0x2000 264 #define RX_CTL_X_DATA_A 0x4000 265 266 267 /* Transmit Configuration Register */ 268 269 #define TX_CFG_LOSS_CRS_IE 0x0040 270 #define TX_CFG_SQE_ERR_IE 0x0080 271 #define TX_CFG_TX_OK_IE 0x0100 272 #define TX_CFG_OUT_WIN_IE 0x0200 273 #define TX_CFG_JABBER_IE 0x0400 274 #define TX_CFG_16_COLL_IE 0x8000 275 #define TX_CFG_ALL_IE 0x8FC0 276 277 278 279 /* Transmit Configuration Register */ 280 281 #define TX_EVENT_LOSS_CRS 0x0040 282 #define TX_EVENT_SQE_ERR 0x0080 283 #define TX_EVENT_TX_OK 0x0100 284 #define TX_EVENT_OUT_WIN 0x0200 285 #define TX_EVENT_JABBER 0x0400 286 #define TX_EVENT_COLL_MASK 0x7800 287 #define TX_EVENT_16_COLL 0x8000 288 289 290 /* Transmit Command Register */ 291 292 #define TX_CMD_START_5 0x0000 293 #define TX_CMD_START_381 0x0080 294 #define TX_CMD_START_1021 0x0040 295 #define TX_CMD_START_ALL 0x00C0 296 #define TX_CMD_FORCE 0x0100 297 #define TX_CMD_ONE_COLL 0x0200 298 #define TX_CMD_NO_CRC 0x1000 299 #define TX_CMD_NO_PAD 0x2000 300 301 302 /* Buffer Configuration Register */ 303 304 #define BUF_CFG_SW_INT 0x0040 305 #define BUF_CFG_RX_DMA_IE 0x0080 306 #define BUF_CFG_RDY4TX_IE 0x0100 307 #define BUF_CFG_RX_MISS_IE 0x0400 308 #define BUF_CFG_TX_UNDR_IE 0x0200 309 #define BUF_CFG_RX_128_IE 0x0800 310 #define BUF_CFG_TX_COL_OVER_IE 0x1000 311 #define BUF_CFG_RX_MISS_OVER_IE 0x2000 312 #define BUF_CFG_RX_DEST_IE 0x8000 313 314 /* Buffer Event Register */ 315 316 #define BUF_EVENT_SW_INT 0x0040 317 #define BUF_EVENT_RX_DMA 0x0080 318 #define BUF_EVENT_RDY4TX 0x0100 319 #define BUF_EVENT_TX_UNDR 0x0200 320 #define BUF_EVENT_RX_MISS 0x0400 321 #define BUF_EVENT_RX_128 0x0800 322 #define BUF_EVENT_RX_DEST 0x8000 323 324 325 /* Autonegotiation Control Register */ 326 327 #define AUTOCTL_NEG_NOW 0x0040 328 #define AUTOCTL_ALLOW_FDX 0x0080 329 #define AUTOCTL_NEG_ENABLE 0x0100 330 #define AUTOCTL_NLP_ENABLE 0x0200 331 #define AUTOCTL_FORCE_FDX 0x8000 332 333 334 /* Autonegotiation Status Register */ 335 336 #define AUTOST_NEG_BUSY 0x0080 337 #define AUTOST_FLP_LINK 0x0100 338 #define AUTOST_FLP_LINK_GOOD 0x0800 339 #define AUTOST_LINK_FAULT 0x1000 340 #define AUTOST_HDX_ACTIVE 0x4000 341 #define AUTOST_FDX_ACTIVE 0x8000 342 343 344 /* ISA Configuration from EEPROM */ 345 346 #define ISA_CFG_IRQ_MASK 0x000F 347 #define ISA_CFG_USE_SA 0x0080 348 #define ISA_CFG_IOCHRDY 0x0100 349 #define ISA_CFG_MEM_MODE 0x8000 350 351 352 /* Memory Base from EEPROM */ 353 354 #define MEM_BASE_MASK 0xFFF0 355 356 357 /* Adpater Configuration from EEPROM */ 358 359 #define ADPTR_CFG_MEDIA 0x0060 360 #define ADPTR_CFG_10BASET 0x0020 361 #define ADPTR_CFG_AUI 0x0040 362 #define ADPTR_CFG_10BASE2 0x0060 363 #define ADPTR_CFG_DCDC_POL 0x0080 364 365 366 /* Transmission Control from EEPROM */ 367 368 #define XMIT_CTL_FDX 0x8000 369 370 371 /* Miscellaneous definitions */ 372 373 #define MAXLOOP 0x8888 374 #define RXBUFCOUNT 16 375 #define MC_LOANED 5 376 377 #endif /* _DEV_IC_CS89X0REG_H_ */ 378