1 /* $NetBSD: dp83932.c,v 1.5 2001/11/13 13:14:36 lukem Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Device driver for the National Semiconductor DP83932 41 * Systems-Oriented Network Interface Controller (SONIC). 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: dp83932.c,v 1.5 2001/11/13 13:14:36 lukem Exp $"); 46 47 #include "bpfilter.h" 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/mbuf.h> 52 #include <sys/malloc.h> 53 #include <sys/kernel.h> 54 #include <sys/socket.h> 55 #include <sys/ioctl.h> 56 #include <sys/errno.h> 57 #include <sys/device.h> 58 59 #include <uvm/uvm_extern.h> 60 61 #include <net/if.h> 62 #include <net/if_dl.h> 63 #include <net/if_ether.h> 64 65 #if NBPFILTER > 0 66 #include <net/bpf.h> 67 #endif 68 69 #include <machine/bus.h> 70 #include <machine/intr.h> 71 72 #include <dev/ic/dp83932reg.h> 73 #include <dev/ic/dp83932var.h> 74 75 void sonic_start(struct ifnet *); 76 void sonic_watchdog(struct ifnet *); 77 int sonic_ioctl(struct ifnet *, u_long, caddr_t); 78 int sonic_init(struct ifnet *); 79 void sonic_stop(struct ifnet *, int); 80 81 void sonic_shutdown(void *); 82 83 void sonic_reset(struct sonic_softc *); 84 void sonic_rxdrain(struct sonic_softc *); 85 int sonic_add_rxbuf(struct sonic_softc *, int); 86 void sonic_set_filter(struct sonic_softc *); 87 88 uint16_t sonic_txintr(struct sonic_softc *); 89 void sonic_rxintr(struct sonic_softc *); 90 91 int sonic_copy_small = 0; 92 93 /* 94 * sonic_attach: 95 * 96 * Attach a SONIC interface to the system. 97 */ 98 void 99 sonic_attach(struct sonic_softc *sc, const uint8_t *enaddr) 100 { 101 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 102 int i, rseg, error; 103 bus_dma_segment_t seg; 104 size_t cdatasize; 105 106 /* 107 * Allocate the control data structures, and create and load the 108 * DMA map for it. 109 */ 110 if (sc->sc_32bit) 111 cdatasize = sizeof(struct sonic_control_data32); 112 else 113 cdatasize = sizeof(struct sonic_control_data16); 114 115 if ((error = bus_dmamem_alloc(sc->sc_dmat, cdatasize, 116 PAGE_SIZE, (64 * 1024), &seg, 1, &rseg, 117 BUS_DMA_NOWAIT)) != 0) { 118 printf("%s: unable to allocate control data, error = %d\n", 119 sc->sc_dev.dv_xname, error); 120 goto fail_0; 121 } 122 123 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 124 cdatasize, (caddr_t *) &sc->sc_cdata16, 125 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 126 printf("%s: unable to map control data, error = %d\n", 127 sc->sc_dev.dv_xname, error); 128 goto fail_1; 129 } 130 131 if ((error = bus_dmamap_create(sc->sc_dmat, 132 cdatasize, 1, cdatasize, 0, BUS_DMA_NOWAIT, 133 &sc->sc_cddmamap)) != 0) { 134 printf("%s: unable to create control data DMA map, " 135 "error = %d\n", sc->sc_dev.dv_xname, error); 136 goto fail_2; 137 } 138 139 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 140 sc->sc_cdata16, cdatasize, NULL, BUS_DMA_NOWAIT)) != 0) { 141 printf("%s: unable to load control data DMA map, error = %d\n", 142 sc->sc_dev.dv_xname, error); 143 goto fail_3; 144 } 145 146 /* 147 * Create the transmit buffer DMA maps. 148 */ 149 for (i = 0; i < SONIC_NTXDESC; i++) { 150 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 151 SONIC_NTXFRAGS, MCLBYTES, 0, BUS_DMA_NOWAIT, 152 &sc->sc_txsoft[i].ds_dmamap)) != 0) { 153 printf("%s: unable to create tx DMA map %d, " 154 "error = %d\n", sc->sc_dev.dv_xname, i, error); 155 goto fail_4; 156 } 157 } 158 159 /* 160 * Create the receive buffer DMA maps. 161 */ 162 for (i = 0; i < SONIC_NRXDESC; i++) { 163 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 164 MCLBYTES, 0, BUS_DMA_NOWAIT, 165 &sc->sc_rxsoft[i].ds_dmamap)) != 0) { 166 printf("%s: unable to create rx DMA map %d, " 167 "error = %d\n", sc->sc_dev.dv_xname, i, error); 168 goto fail_5; 169 } 170 sc->sc_rxsoft[i].ds_mbuf = NULL; 171 } 172 173 /* 174 * Reset the chip to a known state. 175 */ 176 sonic_reset(sc); 177 178 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 179 ether_sprintf(enaddr)); 180 181 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 182 ifp->if_softc = sc; 183 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 184 ifp->if_ioctl = sonic_ioctl; 185 ifp->if_start = sonic_start; 186 ifp->if_watchdog = sonic_watchdog; 187 ifp->if_init = sonic_init; 188 ifp->if_stop = sonic_stop; 189 IFQ_SET_READY(&ifp->if_snd); 190 191 /* 192 * Attach the interface. 193 */ 194 if_attach(ifp); 195 ether_ifattach(ifp, enaddr); 196 197 /* 198 * Make sure the interface is shutdown during reboot. 199 */ 200 sc->sc_sdhook = shutdownhook_establish(sonic_shutdown, sc); 201 if (sc->sc_sdhook == NULL) 202 printf("%s: WARNING: unable to establish shutdown hook\n", 203 sc->sc_dev.dv_xname); 204 return; 205 206 /* 207 * Free any resources we've allocated during the failed attach 208 * attempt. Do this in reverse order and fall through. 209 */ 210 fail_5: 211 for (i = 0; i < SONIC_NRXDESC; i++) { 212 if (sc->sc_rxsoft[i].ds_dmamap != NULL) 213 bus_dmamap_destroy(sc->sc_dmat, 214 sc->sc_rxsoft[i].ds_dmamap); 215 } 216 fail_4: 217 for (i = 0; i < SONIC_NTXDESC; i++) { 218 if (sc->sc_txsoft[i].ds_dmamap != NULL) 219 bus_dmamap_destroy(sc->sc_dmat, 220 sc->sc_txsoft[i].ds_dmamap); 221 } 222 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 223 fail_3: 224 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 225 fail_2: 226 bus_dmamem_unmap(sc->sc_dmat, (caddr_t) sc->sc_cdata16, cdatasize); 227 fail_1: 228 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 229 fail_0: 230 return; 231 } 232 233 /* 234 * sonic_shutdown: 235 * 236 * Make sure the interface is stopped at reboot. 237 */ 238 void 239 sonic_shutdown(void *arg) 240 { 241 struct sonic_softc *sc = arg; 242 243 sonic_stop(&sc->sc_ethercom.ec_if, 1); 244 } 245 246 /* 247 * sonic_start: [ifnet interface function] 248 * 249 * Start packet transmission on the interface. 250 */ 251 void 252 sonic_start(struct ifnet *ifp) 253 { 254 struct sonic_softc *sc = ifp->if_softc; 255 struct mbuf *m0, *m; 256 struct sonic_tda16 *tda16; 257 struct sonic_tda32 *tda32; 258 struct sonic_descsoft *ds; 259 bus_dmamap_t dmamap; 260 int error, olasttx, nexttx, opending, seg, totlen, olseg; 261 262 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 263 return; 264 265 /* 266 * Remember the previous txpending and the current "last txdesc 267 * used" index. 268 */ 269 opending = sc->sc_txpending; 270 olasttx = sc->sc_txlast; 271 272 /* 273 * Loop through the send queue, setting up transmit descriptors 274 * until we drain the queue, or use up all available transmit 275 * descriptors. Leave one at the end for sanity's sake. 276 */ 277 while (sc->sc_txpending < (SONIC_NTXDESC - 1)) { 278 /* 279 * Grab a packet off the queue. 280 */ 281 IFQ_POLL(&ifp->if_snd, m0); 282 if (m0 == NULL) 283 break; 284 m = NULL; 285 286 /* 287 * Get the next available transmit descriptor. 288 */ 289 nexttx = SONIC_NEXTTX(sc->sc_txlast); 290 ds = &sc->sc_txsoft[nexttx]; 291 dmamap = ds->ds_dmamap; 292 293 /* 294 * Load the DMA map. If this fails, the packet either 295 * didn't fit in the allotted number of frags, or we were 296 * short on resources. In this case, we'll copy and try 297 * again. 298 */ 299 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 300 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 301 MGETHDR(m, M_DONTWAIT, MT_DATA); 302 if (m == NULL) { 303 printf("%s: unable to allocate Tx mbuf\n", 304 sc->sc_dev.dv_xname); 305 break; 306 } 307 if (m0->m_pkthdr.len > MHLEN) { 308 MCLGET(m, M_DONTWAIT); 309 if ((m->m_flags & M_EXT) == 0) { 310 printf("%s: unable to allocate Tx " 311 "cluster\n", sc->sc_dev.dv_xname); 312 m_freem(m); 313 break; 314 } 315 } 316 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 317 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 318 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 319 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 320 if (error) { 321 printf("%s: unable to load Tx buffer, " 322 "error = %d\n", sc->sc_dev.dv_xname, error); 323 m_freem(m); 324 break; 325 } 326 } 327 IFQ_DEQUEUE(&ifp->if_snd, m0); 328 if (m != NULL) { 329 m_freem(m0); 330 m0 = m; 331 } 332 333 /* 334 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 335 */ 336 337 /* Sync the DMA map. */ 338 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 339 BUS_DMASYNC_PREWRITE); 340 341 /* 342 * Store a pointer to the packet so we can free it later. 343 */ 344 ds->ds_mbuf = m0; 345 346 /* 347 * Initialize the transmit descriptor. 348 */ 349 totlen = 0; 350 if (sc->sc_32bit) { 351 tda32 = &sc->sc_tda32[nexttx]; 352 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 353 tda32->tda_frags[seg].frag_ptr1 = 354 htosonic32(sc, 355 (dmamap->dm_segs[seg].ds_addr >> 16) & 356 0xffff); 357 tda32->tda_frags[seg].frag_ptr0 = 358 htosonic32(sc, 359 dmamap->dm_segs[seg].ds_addr & 0xffff); 360 tda32->tda_frags[seg].frag_size = 361 htosonic32(sc, dmamap->dm_segs[seg].ds_len); 362 totlen += dmamap->dm_segs[seg].ds_len; 363 } 364 365 /* 366 * Pad the packet out if it's less than the 367 * minimum Ethernet frame size. 368 */ 369 if (totlen < (ETHER_MIN_LEN - ETHER_CRC_LEN)) { 370 tda32->tda_frags[seg - 1].frag_size = 371 htosonic32(sc, 372 dmamap->dm_segs[seg - 1].ds_len + 373 ((ETHER_MIN_LEN - ETHER_CRC_LEN) - totlen)); 374 totlen = ETHER_MIN_LEN - ETHER_CRC_LEN; 375 } 376 377 tda32->tda_status = 0; 378 tda32->tda_pktconfig = 0; 379 tda32->tda_pktsize = htosonic32(sc, totlen); 380 tda32->tda_fragcnt = htosonic32(sc, seg); 381 382 /* Link it up. */ 383 tda32->tda_frags[seg].frag_ptr0 = 384 htosonic32(sc, SONIC_CDTXADDR32(sc, 385 SONIC_NEXTTX(nexttx)) & 0xffff); 386 387 /* Sync the Tx descriptor. */ 388 SONIC_CDTXSYNC32(sc, nexttx, 389 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 390 } else { 391 tda16 = &sc->sc_tda16[nexttx]; 392 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 393 tda16->tda_frags[seg].frag_ptr1 = 394 htosonic16(sc, 395 (dmamap->dm_segs[seg].ds_addr >> 16) & 396 0xffff); 397 tda16->tda_frags[seg].frag_ptr0 = 398 htosonic16(sc, 399 dmamap->dm_segs[seg].ds_addr & 0xffff); 400 tda16->tda_frags[seg].frag_size = 401 htosonic16(sc, dmamap->dm_segs[seg].ds_len); 402 totlen += dmamap->dm_segs[seg].ds_len; 403 } 404 405 /* 406 * Pad the packet out if it's less than the 407 * minimum Ethernet frame size. 408 */ 409 if (totlen < (ETHER_MIN_LEN - ETHER_CRC_LEN)) { 410 tda16->tda_frags[seg - 1].frag_size = 411 htosonic16(sc, 412 dmamap->dm_segs[seg - 1].ds_len + 413 ((ETHER_MIN_LEN - ETHER_CRC_LEN) - totlen)); 414 totlen = ETHER_MIN_LEN - ETHER_CRC_LEN; 415 } 416 417 tda16->tda_status = 0; 418 tda16->tda_pktconfig = 0; 419 tda16->tda_pktsize = htosonic16(sc, totlen); 420 tda16->tda_fragcnt = htosonic16(sc, seg); 421 422 /* Link it up. */ 423 tda16->tda_frags[seg].frag_ptr0 = 424 htosonic16(sc, SONIC_CDTXADDR16(sc, 425 SONIC_NEXTTX(nexttx)) & 0xffff); 426 427 /* Sync the Tx descriptor. */ 428 SONIC_CDTXSYNC16(sc, nexttx, 429 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 430 } 431 432 /* Advance the Tx pointer. */ 433 sc->sc_txpending++; 434 sc->sc_txlast = nexttx; 435 436 #if NBPFILTER > 0 437 /* 438 * Pass the packet to any BPF listeners. 439 */ 440 if (ifp->if_bpf) 441 bpf_mtap(ifp->if_bpf, m0); 442 #endif 443 } 444 445 if (sc->sc_txpending == (SONIC_NTXDESC - 1)) { 446 /* No more slots left; notify upper layer. */ 447 ifp->if_flags |= IFF_OACTIVE; 448 } 449 450 if (sc->sc_txpending != opending) { 451 /* 452 * We enqueued packets. If the transmitter was idle, 453 * reset the txdirty pointer. 454 */ 455 if (opending == 0) 456 sc->sc_txdirty = SONIC_NEXTTX(olasttx); 457 458 /* 459 * Stop the SONIC on the last packet we've set up, 460 * and clear end-of-list on the descriptor previous 461 * to our new chain. 462 * 463 * NOTE: our `seg' variable should still be valid! 464 */ 465 if (sc->sc_32bit) { 466 olseg = 467 sonic32toh(sc, sc->sc_tda32[olasttx].tda_fragcnt); 468 sc->sc_tda32[sc->sc_txlast].tda_frags[seg].frag_ptr0 |= 469 htosonic32(sc, TDA_LINK_EOL); 470 SONIC_CDTXSYNC32(sc, sc->sc_txlast, 471 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 472 sc->sc_tda32[olasttx].tda_frags[olseg].frag_ptr0 &= 473 htosonic32(sc, ~TDA_LINK_EOL); 474 SONIC_CDTXSYNC32(sc, olasttx, 475 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 476 } else { 477 olseg = 478 sonic16toh(sc, sc->sc_tda16[olasttx].tda_fragcnt); 479 sc->sc_tda16[sc->sc_txlast].tda_frags[seg].frag_ptr0 |= 480 htosonic16(sc, TDA_LINK_EOL); 481 SONIC_CDTXSYNC16(sc, sc->sc_txlast, 482 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 483 sc->sc_tda16[olasttx].tda_frags[olseg].frag_ptr0 &= 484 htosonic16(sc, ~TDA_LINK_EOL); 485 SONIC_CDTXSYNC16(sc, olasttx, 486 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 487 } 488 489 /* Start the transmitter. */ 490 CSR_WRITE(sc, SONIC_CR, CR_TXP); 491 492 /* Set a watchdog timer in case the chip flakes out. */ 493 ifp->if_timer = 5; 494 } 495 } 496 497 /* 498 * sonic_watchdog: [ifnet interface function] 499 * 500 * Watchdog timer handler. 501 */ 502 void 503 sonic_watchdog(struct ifnet *ifp) 504 { 505 struct sonic_softc *sc = ifp->if_softc; 506 507 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 508 ifp->if_oerrors++; 509 510 (void) sonic_init(ifp); 511 } 512 513 /* 514 * sonic_ioctl: [ifnet interface function] 515 * 516 * Handle control requests from the operator. 517 */ 518 int 519 sonic_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 520 { 521 int s, error; 522 523 s = splnet(); 524 525 switch (cmd) { 526 default: 527 error = ether_ioctl(ifp, cmd, data); 528 if (error == ENETRESET) { 529 /* 530 * Multicast list has changed; set the hardware 531 * filter accordingly. 532 */ 533 (void) sonic_init(ifp); 534 error = 0; 535 } 536 break; 537 } 538 539 splx(s); 540 return (error); 541 } 542 543 /* 544 * sonic_intr: 545 * 546 * Interrupt service routine. 547 */ 548 int 549 sonic_intr(void *arg) 550 { 551 struct sonic_softc *sc = arg; 552 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 553 uint16_t isr; 554 int handled = 0, wantinit; 555 556 for (wantinit = 0; wantinit == 0;) { 557 isr = CSR_READ(sc, SONIC_ISR) & sc->sc_imr; 558 if (isr == 0) 559 break; 560 CSR_WRITE(sc, SONIC_ISR, isr); /* ACK */ 561 562 handled = 1; 563 564 if (isr & IMR_PRX) 565 sonic_rxintr(sc); 566 567 if (isr & (IMR_PTX|IMR_TXER)) { 568 if (sonic_txintr(sc) & TCR_FU) { 569 printf("%s: transmit FIFO underrun\n", 570 sc->sc_dev.dv_xname); 571 wantinit = 1; 572 } 573 } 574 575 if (isr & (IMR_RFO|IMR_RBA|IMR_RBE|IMR_RDE)) { 576 #define PRINTERR(bit, str) \ 577 if (isr & (bit)) \ 578 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 579 PRINTERR(IMR_RFO, "receive FIFO overrun"); 580 PRINTERR(IMR_RBA, "receive buffer exceeded"); 581 PRINTERR(IMR_RBE, "receive buffers exhausted"); 582 PRINTERR(IMR_RDE, "receive descriptors exhausted"); 583 wantinit = 1; 584 } 585 } 586 587 if (handled) { 588 if (wantinit) 589 (void) sonic_init(ifp); 590 sonic_start(ifp); 591 } 592 593 return (handled); 594 } 595 596 /* 597 * sonic_txintr: 598 * 599 * Helper; handle transmit complete interrupts. 600 */ 601 uint16_t 602 sonic_txintr(struct sonic_softc *sc) 603 { 604 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 605 struct sonic_descsoft *ds; 606 struct sonic_tda32 *tda32; 607 struct sonic_tda16 *tda16; 608 uint16_t status, totstat = 0; 609 int i; 610 611 ifp->if_flags &= ~IFF_OACTIVE; 612 613 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 614 i = SONIC_NEXTTX(i), sc->sc_txpending--) { 615 ds = &sc->sc_txsoft[i]; 616 617 if (sc->sc_32bit) { 618 SONIC_CDTXSYNC32(sc, i, 619 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 620 tda32 = &sc->sc_tda32[i]; 621 status = sonic32toh(sc, tda32->tda_status); 622 } else { 623 SONIC_CDTXSYNC16(sc, i, 624 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 625 tda16 = &sc->sc_tda16[i]; 626 status = sonic16toh(sc, tda16->tda_status); 627 } 628 629 if ((status & ~(TCR_EXDIS|TCR_CRCI|TCR_POWC|TCR_PINT)) == 0) 630 break; 631 632 totstat |= status; 633 634 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 635 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 636 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 637 m_freem(ds->ds_mbuf); 638 ds->ds_mbuf = NULL; 639 640 /* 641 * Check for errors and collisions. 642 */ 643 if (status & TCR_PTX) 644 ifp->if_opackets++; 645 else 646 ifp->if_oerrors++; 647 ifp->if_collisions += TDA_STATUS_NCOL(status); 648 } 649 650 /* Update the dirty transmit buffer pointer. */ 651 sc->sc_txdirty = i; 652 653 /* 654 * Cancel the watchdog timer if there are no pending 655 * transmissions. 656 */ 657 if (sc->sc_txpending == 0) 658 ifp->if_timer = 0; 659 660 return (totstat); 661 } 662 663 /* 664 * sonic_rxintr: 665 * 666 * Helper; handle receive interrupts. 667 */ 668 void 669 sonic_rxintr(struct sonic_softc *sc) 670 { 671 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 672 struct sonic_descsoft *ds; 673 struct sonic_rda32 *rda32; 674 struct sonic_rda16 *rda16; 675 struct mbuf *m; 676 int i, len; 677 uint16_t status, bytecount, ptr0, ptr1, seqno; 678 679 for (i = sc->sc_rxptr;; i = SONIC_NEXTRX(i)) { 680 ds = &sc->sc_rxsoft[i]; 681 682 if (sc->sc_32bit) { 683 SONIC_CDRXSYNC32(sc, i, 684 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 685 rda32 = &sc->sc_rda32[i]; 686 if (rda32->rda_inuse != 0) 687 break; 688 status = sonic32toh(sc, rda32->rda_status); 689 bytecount = sonic32toh(sc, rda32->rda_bytecount); 690 ptr0 = sonic32toh(sc, rda32->rda_pkt_ptr0); 691 ptr1 = sonic32toh(sc, rda32->rda_pkt_ptr1); 692 seqno = sonic32toh(sc, rda32->rda_seqno); 693 } else { 694 SONIC_CDRXSYNC16(sc, i, 695 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 696 rda16 = &sc->sc_rda16[i]; 697 if (rda16->rda_inuse != 0) 698 break; 699 status = sonic16toh(sc, rda16->rda_status); 700 bytecount = sonic16toh(sc, rda16->rda_bytecount); 701 ptr0 = sonic16toh(sc, rda16->rda_pkt_ptr0); 702 ptr1 = sonic16toh(sc, rda16->rda_pkt_ptr1); 703 seqno = sonic16toh(sc, rda16->rda_seqno); 704 } 705 706 /* 707 * Make absolutely sure this is the only packet 708 * in this receive buffer. Our entire Rx buffer 709 * management scheme depends on this, and if the 710 * SONIC didn't follow our rule, it means we've 711 * misconfigured it. 712 */ 713 KASSERT(status & RCR_LPKT); 714 715 /* 716 * Make sure the packet arrived OK. If an error occurred, 717 * update stats and reset the descriptor. The buffer will 718 * be reused the next time the descriptor comes up in the 719 * ring. 720 */ 721 if ((status & RCR_PRX) == 0) { 722 if (status & RCR_FAER) 723 printf("%s: Rx frame alignment error\n", 724 sc->sc_dev.dv_xname); 725 else if (status & RCR_CRCR) 726 printf("%s: Rx CRC error\n", 727 sc->sc_dev.dv_xname); 728 ifp->if_ierrors++; 729 SONIC_INIT_RXDESC(sc, i); 730 continue; 731 } 732 733 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 734 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 735 736 /* 737 * The SONIC includes the CRC with every packet. 738 */ 739 len = bytecount; 740 741 /* 742 * Ok, if the chip is in 32-bit mode, then receive 743 * buffers must be aligned to 32-bit boundaries, 744 * which means the payload is misaligned. In this 745 * case, we must allocate a new mbuf, and copy the 746 * packet into it, scooted forward 2 bytes to ensure 747 * proper alignment. 748 * 749 * Note, in 16-bit mode, we can configure the SONIC 750 * to do what we want, and we have. 751 */ 752 #ifndef __NO_STRICT_ALIGNMENT 753 if (sc->sc_32bit) { 754 MGETHDR(m, M_DONTWAIT, MT_DATA); 755 if (m == NULL) 756 goto dropit; 757 if (len > (MHLEN - 2)) { 758 MCLGET(m, M_DONTWAIT); 759 if ((m->m_flags & M_EXT) == 0) 760 goto dropit; 761 } 762 m->m_data += 2; 763 /* 764 * Note that we use a cluster for incoming frames, 765 * so the buffer is virtually contiguous. 766 */ 767 memcpy(mtod(m, caddr_t), mtod(ds->ds_mbuf, caddr_t), 768 len); 769 SONIC_INIT_RXDESC(sc, i); 770 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 771 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 772 } else 773 #endif /* ! __NO_STRICT_ALIGNMENT */ 774 /* 775 * If the packet is small enough to fit in a single 776 * header mbuf, allocate one and copy the data into 777 * it. This greatly reduces memory consumption when 778 * we receive lots of small packets. 779 */ 780 if (sonic_copy_small != 0 && len <= (MHLEN - 2)) { 781 MGETHDR(m, M_DONTWAIT, MT_DATA); 782 if (m == NULL) 783 goto dropit; 784 m->m_data += 2; 785 /* 786 * Note that we use a cluster for incoming frames, 787 * so the buffer is virtually contiguous. 788 */ 789 memcpy(mtod(m, caddr_t), mtod(ds->ds_mbuf, caddr_t), 790 len); 791 SONIC_INIT_RXDESC(sc, i); 792 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 793 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 794 } else { 795 m = ds->ds_mbuf; 796 if (sonic_add_rxbuf(sc, i) != 0) { 797 dropit: 798 ifp->if_ierrors++; 799 SONIC_INIT_RXDESC(sc, i); 800 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 801 ds->ds_dmamap->dm_mapsize, 802 BUS_DMASYNC_PREREAD); 803 continue; 804 } 805 } 806 807 ifp->if_ipackets++; 808 m->m_flags |= M_HASFCS; 809 m->m_pkthdr.rcvif = ifp; 810 m->m_pkthdr.len = m->m_len = len; 811 812 #if NBPFILTER > 0 813 /* 814 * Pass this up to any BPF listeners. 815 */ 816 if (ifp->if_bpf) 817 bpf_mtap(ifp->if_bpf, m); 818 #endif /* NBPFILTER > 0 */ 819 820 /* Pass it on. */ 821 (*ifp->if_input)(ifp, m); 822 } 823 824 /* Update the receive pointer. */ 825 sc->sc_rxptr = i; 826 CSR_WRITE(sc, SONIC_RWR, SONIC_CDRRADDR(sc, SONIC_PREVRX(i))); 827 } 828 829 /* 830 * sonic_reset: 831 * 832 * Perform a soft reset on the SONIC. 833 */ 834 void 835 sonic_reset(struct sonic_softc *sc) 836 { 837 838 CSR_WRITE(sc, SONIC_CR, 0); /* ensure RST is clear */ 839 CSR_WRITE(sc, SONIC_CR, CR_RST); 840 delay(1000); 841 CSR_WRITE(sc, SONIC_CR, 0); 842 delay(1000); 843 } 844 845 /* 846 * sonic_init: [ifnet interface function] 847 * 848 * Initialize the interface. Must be called at splnet(). 849 */ 850 int 851 sonic_init(struct ifnet *ifp) 852 { 853 struct sonic_softc *sc = ifp->if_softc; 854 struct sonic_descsoft *ds; 855 int i, error = 0; 856 uint16_t reg; 857 858 /* 859 * Cancel any pending I/O. 860 */ 861 sonic_stop(ifp, 0); 862 863 /* 864 * Reset the SONIC to a known state. 865 */ 866 sonic_reset(sc); 867 868 /* 869 * Bring the SONIC into reset state, and program the DCR. 870 * 871 * Note: We don't bother optimizing the transmit and receive 872 * thresholds, here. We just use the most conservative values: 873 * 874 * - Rx: 4 bytes (RFT0,RFT0 == 0,0) 875 * - Tx: 28 bytes (TFT0,TFT1 == 1,1) 876 */ 877 reg = sc->sc_dcr | DCR_TFT0 | DCR_TFT1; 878 if (sc->sc_32bit) 879 reg |= DCR_DW; 880 CSR_WRITE(sc, SONIC_CR, CR_RST); 881 CSR_WRITE(sc, SONIC_DCR, reg); 882 CSR_WRITE(sc, SONIC_DCR2, sc->sc_dcr2); 883 CSR_WRITE(sc, SONIC_CR, 0); 884 885 /* 886 * Initialize the transmit descriptors. 887 */ 888 if (sc->sc_32bit) { 889 for (i = 0; i < SONIC_NTXDESC; i++) { 890 memset(&sc->sc_tda32[i], 0, sizeof(struct sonic_tda32)); 891 SONIC_CDTXSYNC32(sc, i, 892 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 893 } 894 } else { 895 for (i = 0; i < SONIC_NTXDESC; i++) { 896 memset(&sc->sc_tda16[i], 0, sizeof(struct sonic_tda16)); 897 SONIC_CDTXSYNC16(sc, i, 898 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 899 } 900 } 901 sc->sc_txpending = 0; 902 sc->sc_txdirty = 0; 903 sc->sc_txlast = SONIC_NTXDESC - 1; 904 905 /* 906 * Initialize the receive descriptor ring. 907 */ 908 for (i = 0; i < SONIC_NRXDESC; i++) { 909 ds = &sc->sc_rxsoft[i]; 910 if (ds->ds_mbuf == NULL) { 911 if ((error = sonic_add_rxbuf(sc, i)) != 0) { 912 printf("%s: unable to allocate or map Rx " 913 "buffer %d, error = %d\n", 914 sc->sc_dev.dv_xname, i, error); 915 /* 916 * XXX Should attempt to run with fewer receive 917 * XXX buffers instead of just failing. 918 */ 919 sonic_rxdrain(sc); 920 goto out; 921 } 922 } else 923 SONIC_INIT_RXDESC(sc, i); 924 } 925 sc->sc_rxptr = 0; 926 927 /* Give the transmit ring to the SONIC. */ 928 CSR_WRITE(sc, SONIC_UTDAR, (SONIC_CDTXADDR(sc, 0) >> 16) & 0xffff); 929 CSR_WRITE(sc, SONIC_CTDAR, SONIC_CDTXADDR(sc, 0) & 0xffff); 930 931 /* Give the receive descriptor ring to the SONIC. */ 932 CSR_WRITE(sc, SONIC_URDAR, (SONIC_CDRXADDR(sc, 0) >> 16) & 0xffff); 933 CSR_WRITE(sc, SONIC_CRDAR, SONIC_CDRXADDR(sc, 0) & 0xffff); 934 935 /* Give the receive buffer ring to the SONIC. */ 936 CSR_WRITE(sc, SONIC_URRAR, (SONIC_CDRRADDR(sc, 0) >> 16) & 0xffff); 937 CSR_WRITE(sc, SONIC_RSAR, SONIC_CDRRADDR(sc, 0) & 0xffff); 938 if (sc->sc_32bit) 939 CSR_WRITE(sc, SONIC_REAR, 940 (SONIC_CDRRADDR(sc, SONIC_NRXDESC - 1) + 941 sizeof(struct sonic_rra32)) & 0xffff); 942 else 943 CSR_WRITE(sc, SONIC_REAR, 944 (SONIC_CDRRADDR(sc, SONIC_NRXDESC - 1) + 945 sizeof(struct sonic_rra16)) & 0xffff); 946 CSR_WRITE(sc, SONIC_RRR, SONIC_CDRRADDR(sc, 0) & 0xffff); 947 CSR_WRITE(sc, SONIC_RWR, SONIC_CDRRADDR(sc, SONIC_NRXDESC - 1)); 948 949 /* 950 * Set the End-Of-Buffer counter such that only one packet 951 * will be placed into each buffer we provide. Note we are 952 * following the recommendation of section 3.4.4 of the manual 953 * here, and have "lengthened" the receive buffers accordingly. 954 */ 955 if (sc->sc_32bit) 956 CSR_WRITE(sc, SONIC_EOBC, (ETHER_MAX_LEN + 2) / 2); 957 else 958 CSR_WRITE(sc, SONIC_EOBC, (ETHER_MAX_LEN / 2)); 959 960 /* Reset the receive sequence counter. */ 961 CSR_WRITE(sc, SONIC_RSC, 0); 962 963 /* Clear the tally registers. */ 964 CSR_WRITE(sc, SONIC_CRCETC, 0xffff); 965 CSR_WRITE(sc, SONIC_FAET, 0xffff); 966 CSR_WRITE(sc, SONIC_MPT, 0xffff); 967 968 /* Set the receive filter. */ 969 sonic_set_filter(sc); 970 971 /* 972 * Set the interrupt mask register. 973 */ 974 sc->sc_imr = IMR_RFO | IMR_RBA | IMR_RBE | IMR_RDE | 975 IMR_TXER | IMR_PTX | IMR_PRX; 976 CSR_WRITE(sc, SONIC_IMR, sc->sc_imr); 977 978 /* 979 * Start the receive process in motion. Note, we don't 980 * start the transmit process until we actually try to 981 * transmit packets. 982 */ 983 CSR_WRITE(sc, SONIC_CR, CR_RXEN | CR_RRRA); 984 985 /* 986 * ...all done! 987 */ 988 ifp->if_flags |= IFF_RUNNING; 989 ifp->if_flags &= ~IFF_OACTIVE; 990 991 out: 992 if (error) 993 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 994 return (error); 995 } 996 997 /* 998 * sonic_rxdrain: 999 * 1000 * Drain the receive queue. 1001 */ 1002 void 1003 sonic_rxdrain(struct sonic_softc *sc) 1004 { 1005 struct sonic_descsoft *ds; 1006 int i; 1007 1008 for (i = 0; i < SONIC_NRXDESC; i++) { 1009 ds = &sc->sc_rxsoft[i]; 1010 if (ds->ds_mbuf != NULL) { 1011 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1012 m_freem(ds->ds_mbuf); 1013 ds->ds_mbuf = NULL; 1014 } 1015 } 1016 } 1017 1018 /* 1019 * sonic_stop: [ifnet interface function] 1020 * 1021 * Stop transmission on the interface. 1022 */ 1023 void 1024 sonic_stop(struct ifnet *ifp, int disable) 1025 { 1026 struct sonic_softc *sc = ifp->if_softc; 1027 struct sonic_descsoft *ds; 1028 int i; 1029 1030 /* 1031 * Disable interrupts. 1032 */ 1033 CSR_WRITE(sc, SONIC_IMR, 0); 1034 1035 /* 1036 * Stop the transmitter, receiver, and timer. 1037 */ 1038 CSR_WRITE(sc, SONIC_CR, CR_HTX|CR_RXDIS|CR_STP); 1039 for (i = 0; i < 1000; i++) { 1040 if ((CSR_READ(sc, SONIC_CR) & (CR_TXP|CR_RXEN|CR_ST)) == 0) 1041 break; 1042 delay(2); 1043 } 1044 if ((CSR_READ(sc, SONIC_CR) & (CR_TXP|CR_RXEN|CR_ST)) != 0) 1045 printf("%s: SONIC failed to stop\n", sc->sc_dev.dv_xname); 1046 1047 /* 1048 * Release any queued transmit buffers. 1049 */ 1050 for (i = 0; i < SONIC_NTXDESC; i++) { 1051 ds = &sc->sc_txsoft[i]; 1052 if (ds->ds_mbuf != NULL) { 1053 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1054 m_freem(ds->ds_mbuf); 1055 ds->ds_mbuf = NULL; 1056 } 1057 } 1058 1059 if (disable) 1060 sonic_rxdrain(sc); 1061 1062 /* 1063 * Mark the interface down and cancel the watchdog timer. 1064 */ 1065 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1066 ifp->if_timer = 0; 1067 } 1068 1069 /* 1070 * sonic_add_rxbuf: 1071 * 1072 * Add a receive buffer to the indicated descriptor. 1073 */ 1074 int 1075 sonic_add_rxbuf(struct sonic_softc *sc, int idx) 1076 { 1077 struct sonic_descsoft *ds = &sc->sc_rxsoft[idx]; 1078 struct mbuf *m; 1079 int error; 1080 1081 MGETHDR(m, M_DONTWAIT, MT_DATA); 1082 if (m == NULL) 1083 return (ENOBUFS); 1084 1085 MCLGET(m, M_DONTWAIT); 1086 if ((m->m_flags & M_EXT) == 0) { 1087 m_freem(m); 1088 return (ENOBUFS); 1089 } 1090 1091 if (ds->ds_mbuf != NULL) 1092 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1093 1094 ds->ds_mbuf = m; 1095 1096 error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap, 1097 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1098 BUS_DMA_READ|BUS_DMA_NOWAIT); 1099 if (error) { 1100 printf("%s: can't load rx DMA map %d, error = %d\n", 1101 sc->sc_dev.dv_xname, idx, error); 1102 panic("sonic_add_rxbuf"); /* XXX */ 1103 } 1104 1105 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1106 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1107 1108 SONIC_INIT_RXDESC(sc, idx); 1109 1110 return (0); 1111 } 1112 1113 static void 1114 sonic_set_camentry(struct sonic_softc *sc, int entry, const uint8_t *enaddr) 1115 { 1116 1117 if (sc->sc_32bit) { 1118 struct sonic_cda32 *cda = &sc->sc_cda32[entry]; 1119 1120 cda->cda_entry = htosonic32(sc, entry); 1121 cda->cda_addr0 = htosonic32(sc, enaddr[0] | (enaddr[1] << 8)); 1122 cda->cda_addr1 = htosonic32(sc, enaddr[2] | (enaddr[3] << 8)); 1123 cda->cda_addr2 = htosonic32(sc, enaddr[4] | (enaddr[5] << 8)); 1124 } else { 1125 struct sonic_cda16 *cda = &sc->sc_cda16[entry]; 1126 1127 cda->cda_entry = htosonic16(sc, entry); 1128 cda->cda_addr0 = htosonic16(sc, enaddr[0] | (enaddr[1] << 8)); 1129 cda->cda_addr1 = htosonic16(sc, enaddr[2] | (enaddr[3] << 8)); 1130 cda->cda_addr2 = htosonic16(sc, enaddr[4] | (enaddr[5] << 8)); 1131 } 1132 } 1133 1134 /* 1135 * sonic_set_filter: 1136 * 1137 * Set the SONIC receive filter. 1138 */ 1139 void 1140 sonic_set_filter(struct sonic_softc *sc) 1141 { 1142 struct ethercom *ec = &sc->sc_ethercom; 1143 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1144 struct ether_multi *enm; 1145 struct ether_multistep step; 1146 int i, entry = 0; 1147 uint16_t camvalid = 0; 1148 uint16_t rcr = 0; 1149 1150 if (ifp->if_flags & IFF_BROADCAST) 1151 rcr |= RCR_BRD; 1152 1153 if (ifp->if_flags & IFF_PROMISC) { 1154 rcr |= RCR_PRO; 1155 goto allmulti; 1156 } 1157 1158 /* Put our station address in the first CAM slot. */ 1159 sonic_set_camentry(sc, entry, LLADDR(ifp->if_sadl)); 1160 camvalid |= (1U << entry); 1161 entry++; 1162 1163 /* Add the multicast addresses to the CAM. */ 1164 ETHER_FIRST_MULTI(step, ec, enm); 1165 while (enm != NULL) { 1166 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1167 /* 1168 * We must listen to a range of multicast addresses. 1169 * The only way to do this on the SONIC is to enable 1170 * reception of all multicast packets. 1171 */ 1172 goto allmulti; 1173 } 1174 1175 if (entry == 16) { 1176 /* 1177 * Out of CAM slots. Have to enable reception 1178 * of all multicast addresses. 1179 */ 1180 goto allmulti; 1181 } 1182 1183 sonic_set_camentry(sc, entry, enm->enm_addrlo); 1184 camvalid |= (1U << entry); 1185 entry++; 1186 1187 ETHER_NEXT_MULTI(step, enm); 1188 } 1189 1190 ifp->if_flags &= ~IFF_ALLMULTI; 1191 goto setit; 1192 1193 allmulti: 1194 /* Use only the first CAM slot (station address). */ 1195 camvalid = 0x0001; 1196 entry = 1; 1197 rcr |= RCR_AMC; 1198 1199 setit: 1200 /* Load the CAM. */ 1201 SONIC_CDCAMSYNC(sc, BUS_DMASYNC_PREWRITE); 1202 CSR_WRITE(sc, SONIC_CDP, SONIC_CDCAMADDR(sc) & 0xffff); 1203 CSR_WRITE(sc, SONIC_CDC, entry); 1204 CSR_WRITE(sc, SONIC_CR, CR_LCAM); 1205 for (i = 0; i < 10000; i++) { 1206 if ((CSR_READ(sc, SONIC_CR) & CR_LCAM) == 0) 1207 break; 1208 delay(2); 1209 } 1210 if (CSR_READ(sc, SONIC_CR) & CR_LCAM) 1211 printf("%s: CAM load failed\n", sc->sc_dev.dv_xname); 1212 SONIC_CDCAMSYNC(sc, BUS_DMASYNC_POSTWRITE); 1213 1214 /* Set the CAM enable resgiter. */ 1215 CSR_WRITE(sc, SONIC_CER, camvalid); 1216 1217 /* Set the receive control register. */ 1218 CSR_WRITE(sc, SONIC_RCR, rcr); 1219 } 1220